1  /*
2    Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
3    All rights reserved.
4  
5    Redistribution and use in source and binary forms, with or without
6    modification, are permitted provided that the following conditions are met:
7  
8    * Redistributions of source code must retain the above copyright notice,
9      this list of conditions and the following disclaimer.
10    * Redistributions in binary form must reproduce the above copyright notice,
11      this list of conditions and the following disclaimer in the documentation
12  	and/or other materials provided with the distribution.
13    * Neither the name of Trident Microsystems nor Hauppauge Computer Works
14      nor the names of its contributors may be used to endorse or promote
15  	products derived from this software without specific prior written
16  	permission.
17  
18    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21    ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28    POSSIBILITY OF SUCH DAMAGE.
29  */
30  
31  #ifndef __DRXDRIVER_H__
32  #define __DRXDRIVER_H__
33  
34  #include <linux/kernel.h>
35  #include <linux/errno.h>
36  #include <linux/firmware.h>
37  #include <linux/i2c.h>
38  
39  /*
40   * This structure contains the I2C address, the device ID and a user_data pointer.
41   * The user_data pointer can be used for application specific purposes.
42   */
43  struct i2c_device_addr {
44  	u16 i2c_addr;		/* The I2C address of the device. */
45  	u16 i2c_dev_id;		/* The device identifier. */
46  	void *user_data;		/* User data pointer */
47  };
48  
49  /*
50  * \def IS_I2C_10BIT( addr )
51  * \brief Determine if I2C address 'addr' is a 10 bits address or not.
52  * \param addr The I2C address.
53  * \return int.
54  * \retval 0 if address is not a 10 bits I2C address.
55  * \retval 1 if address is a 10 bits I2C address.
56  */
57  #define IS_I2C_10BIT(addr) \
58  	 (((addr) & 0xF8) == 0xF0)
59  
60  /*------------------------------------------------------------------------------
61  Exported FUNCTIONS
62  ------------------------------------------------------------------------------*/
63  
64  /*
65  * \fn drxbsp_i2c_init()
66  * \brief Initialize I2C communication module.
67  * \return int Return status.
68  * \retval 0 Initialization successful.
69  * \retval -EIO Initialization failed.
70  */
71  int drxbsp_i2c_init(void);
72  
73  /*
74  * \fn drxbsp_i2c_term()
75  * \brief Terminate I2C communication module.
76  * \return int Return status.
77  * \retval 0 Termination successful.
78  * \retval -EIO Termination failed.
79  */
80  int drxbsp_i2c_term(void);
81  
82  /*
83  * \fn int drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr,
84  *                                       u16 w_count,
85  *                                       u8 * wData,
86  *                                       struct i2c_device_addr *r_dev_addr,
87  *                                       u16 r_count,
88  *                                       u8 * r_data)
89  * \brief Read and/or write count bytes from I2C bus, store them in data[].
90  * \param w_dev_addr The device i2c address and the device ID to write to
91  * \param w_count   The number of bytes to write
92  * \param wData    The array to write the data to
93  * \param r_dev_addr The device i2c address and the device ID to read from
94  * \param r_count   The number of bytes to read
95  * \param r_data    The array to read the data from
96  * \return int Return status.
97  * \retval 0 Success.
98  * \retval -EIO Failure.
99  * \retval -EINVAL Parameter 'wcount' is not zero but parameter
100  *                                       'wdata' contains NULL.
101  *                                       Idem for 'rcount' and 'rdata'.
102  *                                       Both w_dev_addr and r_dev_addr are NULL.
103  *
104  * This function must implement an atomic write and/or read action on the I2C bus
105  * No other process may use the I2C bus when this function is executing.
106  * The critical section of this function runs from and including the I2C
107  * write, up to and including the I2C read action.
108  *
109  * The device ID can be useful if several devices share an I2C address.
110  * It can be used to control a "switch" on the I2C bus to the correct device.
111  */
112  int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr,
113  					u16 w_count,
114  					u8 *wData,
115  					struct i2c_device_addr *r_dev_addr,
116  					u16 r_count, u8 *r_data);
117  
118  /*
119  * \fn drxbsp_i2c_error_text()
120  * \brief Returns a human readable error.
121  * Counter part of numerical drx_i2c_error_g.
122  *
123  * \return char* Pointer to human readable error text.
124  */
125  char *drxbsp_i2c_error_text(void);
126  
127  /*
128  * \var drx_i2c_error_g;
129  * \brief I2C specific error codes, platform dependent.
130  */
131  extern int drx_i2c_error_g;
132  
133  #define TUNER_MODE_SUB0    0x0001	/* for sub-mode (e.g. RF-AGC setting) */
134  #define TUNER_MODE_SUB1    0x0002	/* for sub-mode (e.g. RF-AGC setting) */
135  #define TUNER_MODE_SUB2    0x0004	/* for sub-mode (e.g. RF-AGC setting) */
136  #define TUNER_MODE_SUB3    0x0008	/* for sub-mode (e.g. RF-AGC setting) */
137  #define TUNER_MODE_SUB4    0x0010	/* for sub-mode (e.g. RF-AGC setting) */
138  #define TUNER_MODE_SUB5    0x0020	/* for sub-mode (e.g. RF-AGC setting) */
139  #define TUNER_MODE_SUB6    0x0040	/* for sub-mode (e.g. RF-AGC setting) */
140  #define TUNER_MODE_SUB7    0x0080	/* for sub-mode (e.g. RF-AGC setting) */
141  
142  #define TUNER_MODE_DIGITAL 0x0100	/* for digital channel (e.g. DVB-T)   */
143  #define TUNER_MODE_ANALOG  0x0200	/* for analog channel  (e.g. PAL)     */
144  #define TUNER_MODE_SWITCH  0x0400	/* during channel switch & scanning   */
145  #define TUNER_MODE_LOCK    0x0800	/* after tuner has locked             */
146  #define TUNER_MODE_6MHZ    0x1000	/* for 6MHz bandwidth channels        */
147  #define TUNER_MODE_7MHZ    0x2000	/* for 7MHz bandwidth channels        */
148  #define TUNER_MODE_8MHZ    0x4000	/* for 8MHz bandwidth channels        */
149  
150  #define TUNER_MODE_SUB_MAX 8
151  #define TUNER_MODE_SUBALL  (TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \
152  			      TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \
153  			      TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \
154  			      TUNER_MODE_SUB6 | TUNER_MODE_SUB7)
155  
156  
157  enum tuner_lock_status {
158  	TUNER_LOCKED,
159  	TUNER_NOT_LOCKED
160  };
161  
162  struct tuner_common {
163  	char *name;	/* Tuner brand & type name */
164  	s32 min_freq_rf;	/* Lowest  RF input frequency, in kHz */
165  	s32 max_freq_rf;	/* Highest RF input frequency, in kHz */
166  
167  	u8 sub_mode;	/* Index to sub-mode in use */
168  	char ***sub_mode_descriptions;	/* Pointer to description of sub-modes */
169  	u8 sub_modes;	/* Number of available sub-modes      */
170  
171  	/* The following fields will be either 0, NULL or false and do not need
172  		initialisation */
173  	void *self_check;	/* gives proof of initialization  */
174  	bool programmed;	/* only valid if self_check is OK  */
175  	s32 r_ffrequency;	/* only valid if programmed       */
176  	s32 i_ffrequency;	/* only valid if programmed       */
177  
178  	void *my_user_data;	/* pointer to associated demod instance */
179  	u16 my_capabilities;	/* value for storing application flags  */
180  };
181  
182  struct tuner_instance;
183  
184  typedef int(*tuner_open_func_t) (struct tuner_instance *tuner);
185  typedef int(*tuner_close_func_t) (struct tuner_instance *tuner);
186  
187  typedef int(*tuner_set_frequency_func_t) (struct tuner_instance *tuner,
188  						u32 mode,
189  						s32
190  						frequency);
191  
192  typedef int(*tuner_get_frequency_func_t) (struct tuner_instance *tuner,
193  						u32 mode,
194  						s32 *
195  						r_ffrequency,
196  						s32 *
197  						i_ffrequency);
198  
199  typedef int(*tuner_lock_status_func_t) (struct tuner_instance *tuner,
200  						enum tuner_lock_status *
201  						lock_stat);
202  
203  typedef int(*tune_ri2c_write_read_func_t) (struct tuner_instance *tuner,
204  						struct i2c_device_addr *
205  						w_dev_addr, u16 w_count,
206  						u8 *wData,
207  						struct i2c_device_addr *
208  						r_dev_addr, u16 r_count,
209  						u8 *r_data);
210  
211  struct tuner_ops {
212  	tuner_open_func_t open_func;
213  	tuner_close_func_t close_func;
214  	tuner_set_frequency_func_t set_frequency_func;
215  	tuner_get_frequency_func_t get_frequency_func;
216  	tuner_lock_status_func_t lock_status_func;
217  	tune_ri2c_write_read_func_t i2c_write_read_func;
218  
219  };
220  
221  struct tuner_instance {
222  	struct i2c_device_addr my_i2c_dev_addr;
223  	struct tuner_common *my_common_attr;
224  	void *my_ext_attr;
225  	struct tuner_ops *my_funct;
226  };
227  
228  int drxbsp_tuner_set_frequency(struct tuner_instance *tuner,
229  					u32 mode,
230  					s32 frequency);
231  
232  int drxbsp_tuner_get_frequency(struct tuner_instance *tuner,
233  					u32 mode,
234  					s32 *r_ffrequency,
235  					s32 *i_ffrequency);
236  
237  int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner,
238  						struct i2c_device_addr *w_dev_addr,
239  						u16 w_count,
240  						u8 *wData,
241  						struct i2c_device_addr *r_dev_addr,
242  						u16 r_count, u8 *r_data);
243  
244  /*************
245  *
246  * This section configures the DRX Data Access Protocols (DAPs).
247  *
248  **************/
249  
250  /*
251  * \def DRXDAP_SINGLE_MASTER
252  * \brief Enable I2C single or I2C multimaster mode on host.
253  *
254  * Set to 1 to enable single master mode
255  * Set to 0 to enable multi master mode
256  *
257  * The actual DAP implementation may be restricted to only one of the modes.
258  * A compiler warning or error will be generated if the DAP implementation
259  * overrides or cannot handle the mode defined below.
260  */
261  #ifndef DRXDAP_SINGLE_MASTER
262  #define DRXDAP_SINGLE_MASTER 1
263  #endif
264  
265  /*
266  * \def DRXDAP_MAX_WCHUNKSIZE
267  * \brief Defines maximum chunksize of an i2c write action by host.
268  *
269  * This indicates the maximum size of data the I2C device driver is able to
270  * write at a time. This includes I2C device address and register addressing.
271  *
272  * This maximum size may be restricted by the actual DAP implementation.
273  * A compiler warning or error will be generated if the DAP implementation
274  * overrides or cannot handle the chunksize defined below.
275  *
276  * Beware that the DAP uses  DRXDAP_MAX_WCHUNKSIZE to create a temporary data
277  * buffer. Do not undefine or choose too large, unless your system is able to
278  * handle a stack buffer of that size.
279  *
280  */
281  #ifndef DRXDAP_MAX_WCHUNKSIZE
282  #define  DRXDAP_MAX_WCHUNKSIZE 60
283  #endif
284  
285  /*
286  * \def DRXDAP_MAX_RCHUNKSIZE
287  * \brief Defines maximum chunksize of an i2c read action by host.
288  *
289  * This indicates the maximum size of data the I2C device driver is able to read
290  * at a time. Minimum value is 2. Also, the read chunk size must be even.
291  *
292  * This maximum size may be restricted by the actual DAP implementation.
293  * A compiler warning or error will be generated if the DAP implementation
294  * overrides or cannot handle the chunksize defined below.
295  */
296  #ifndef DRXDAP_MAX_RCHUNKSIZE
297  #define  DRXDAP_MAX_RCHUNKSIZE 60
298  #endif
299  
300  /*************
301  *
302  * This section describes drxdriver defines.
303  *
304  **************/
305  
306  /*
307  * \def DRX_UNKNOWN
308  * \brief Generic UNKNOWN value for DRX enumerated types.
309  *
310  * Used to indicate that the parameter value is unknown or not yet initialized.
311  */
312  #ifndef DRX_UNKNOWN
313  #define DRX_UNKNOWN (254)
314  #endif
315  
316  /*
317  * \def DRX_AUTO
318  * \brief Generic AUTO value for DRX enumerated types.
319  *
320  * Used to instruct the driver to automatically determine the value of the
321  * parameter.
322  */
323  #ifndef DRX_AUTO
324  #define DRX_AUTO    (255)
325  #endif
326  
327  /*************
328  *
329  * This section describes flag definitions for the device capbilities.
330  *
331  **************/
332  
333  /*
334  * \brief LNA capability flag
335  *
336  * Device has a Low Noise Amplifier
337  *
338  */
339  #define DRX_CAPABILITY_HAS_LNA           (1UL <<  0)
340  /*
341  * \brief OOB-RX capability flag
342  *
343  * Device has OOB-RX
344  *
345  */
346  #define DRX_CAPABILITY_HAS_OOBRX         (1UL <<  1)
347  /*
348  * \brief ATV capability flag
349  *
350  * Device has ATV
351  *
352  */
353  #define DRX_CAPABILITY_HAS_ATV           (1UL <<  2)
354  /*
355  * \brief DVB-T capability flag
356  *
357  * Device has DVB-T
358  *
359  */
360  #define DRX_CAPABILITY_HAS_DVBT          (1UL <<  3)
361  /*
362  * \brief  ITU-B capability flag
363  *
364  * Device has ITU-B
365  *
366  */
367  #define DRX_CAPABILITY_HAS_ITUB          (1UL <<  4)
368  /*
369  * \brief  Audio capability flag
370  *
371  * Device has Audio
372  *
373  */
374  #define DRX_CAPABILITY_HAS_AUD           (1UL <<  5)
375  /*
376  * \brief  SAW switch capability flag
377  *
378  * Device has SAW switch
379  *
380  */
381  #define DRX_CAPABILITY_HAS_SAWSW         (1UL <<  6)
382  /*
383  * \brief  GPIO1 capability flag
384  *
385  * Device has GPIO1
386  *
387  */
388  #define DRX_CAPABILITY_HAS_GPIO1         (1UL <<  7)
389  /*
390  * \brief  GPIO2 capability flag
391  *
392  * Device has GPIO2
393  *
394  */
395  #define DRX_CAPABILITY_HAS_GPIO2         (1UL <<  8)
396  /*
397  * \brief  IRQN capability flag
398  *
399  * Device has IRQN
400  *
401  */
402  #define DRX_CAPABILITY_HAS_IRQN          (1UL <<  9)
403  /*
404  * \brief  8VSB capability flag
405  *
406  * Device has 8VSB
407  *
408  */
409  #define DRX_CAPABILITY_HAS_8VSB          (1UL << 10)
410  /*
411  * \brief  SMA-TX capability flag
412  *
413  * Device has SMATX
414  *
415  */
416  #define DRX_CAPABILITY_HAS_SMATX         (1UL << 11)
417  /*
418  * \brief  SMA-RX capability flag
419  *
420  * Device has SMARX
421  *
422  */
423  #define DRX_CAPABILITY_HAS_SMARX         (1UL << 12)
424  /*
425  * \brief  ITU-A/C capability flag
426  *
427  * Device has ITU-A/C
428  *
429  */
430  #define DRX_CAPABILITY_HAS_ITUAC         (1UL << 13)
431  
432  /*-------------------------------------------------------------------------
433  MACROS
434  -------------------------------------------------------------------------*/
435  /* Macros to stringify the version number */
436  #define DRX_VERSIONSTRING(MAJOR, MINOR, PATCH) \
437  	 DRX_VERSIONSTRING_HELP(MAJOR)"." \
438  	 DRX_VERSIONSTRING_HELP(MINOR)"." \
439  	 DRX_VERSIONSTRING_HELP(PATCH)
440  #define DRX_VERSIONSTRING_HELP(NUM) #NUM
441  
442  /*
443  * \brief Macro to create byte array elements from 16 bit integers.
444  * This macro is used to create byte arrays for block writes.
445  * Block writes speed up I2C traffic between host and demod.
446  * The macro takes care of the required byte order in a 16 bits word.
447  * x->lowbyte(x), highbyte(x)
448  */
449  #define DRX_16TO8(x) ((u8) (((u16)x) & 0xFF)), \
450  			((u8)((((u16)x)>>8)&0xFF))
451  
452  /*
453  * \brief Macro to convert 16 bit register value to a s32
454  */
455  #define DRX_U16TODRXFREQ(x)   ((x & 0x8000) ? \
456  				 ((s32) \
457  				    (((u32) x) | 0xFFFF0000)) : \
458  				 ((s32) x))
459  
460  /*-------------------------------------------------------------------------
461  ENUM
462  -------------------------------------------------------------------------*/
463  
464  /*
465  * \enum enum drx_standard
466  * \brief Modulation standards.
467  */
468  enum drx_standard {
469  	DRX_STANDARD_DVBT = 0, /*< Terrestrial DVB-T.               */
470  	DRX_STANDARD_8VSB,     /*< Terrestrial 8VSB.                */
471  	DRX_STANDARD_NTSC,     /*< Terrestrial\Cable analog NTSC.   */
472  	DRX_STANDARD_PAL_SECAM_BG,
473  				/*< Terrestrial analog PAL/SECAM B/G */
474  	DRX_STANDARD_PAL_SECAM_DK,
475  				/*< Terrestrial analog PAL/SECAM D/K */
476  	DRX_STANDARD_PAL_SECAM_I,
477  				/*< Terrestrial analog PAL/SECAM I   */
478  	DRX_STANDARD_PAL_SECAM_L,
479  				/*< Terrestrial analog PAL/SECAM L
480  					with negative modulation        */
481  	DRX_STANDARD_PAL_SECAM_LP,
482  				/*< Terrestrial analog PAL/SECAM L
483  					with positive modulation        */
484  	DRX_STANDARD_ITU_A,    /*< Cable ITU ANNEX A.               */
485  	DRX_STANDARD_ITU_B,    /*< Cable ITU ANNEX B.               */
486  	DRX_STANDARD_ITU_C,    /*< Cable ITU ANNEX C.               */
487  	DRX_STANDARD_ITU_D,    /*< Cable ITU ANNEX D.               */
488  	DRX_STANDARD_FM,       /*< Terrestrial\Cable FM radio       */
489  	DRX_STANDARD_DTMB,     /*< Terrestrial DTMB standard (China)*/
490  	DRX_STANDARD_UNKNOWN = DRX_UNKNOWN,
491  				/*< Standard unknown.                */
492  	DRX_STANDARD_AUTO = DRX_AUTO
493  				/*< Autodetect standard.             */
494  };
495  
496  /*
497  * \enum enum drx_standard
498  * \brief Modulation sub-standards.
499  */
500  enum drx_substandard {
501  	DRX_SUBSTANDARD_MAIN = 0, /*< Main subvariant of standard   */
502  	DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA,
503  	DRX_SUBSTANDARD_ATV_DK_POLAND,
504  	DRX_SUBSTANDARD_ATV_DK_CHINA,
505  	DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN,
506  					/*< Sub-standard unknown.         */
507  	DRX_SUBSTANDARD_AUTO = DRX_AUTO
508  					/*< Auto (default) sub-standard   */
509  };
510  
511  /*
512  * \enum enum drx_bandwidth
513  * \brief Channel bandwidth or channel spacing.
514  */
515  enum drx_bandwidth {
516  	DRX_BANDWIDTH_8MHZ = 0,	 /*< Bandwidth 8 MHz.   */
517  	DRX_BANDWIDTH_7MHZ,	 /*< Bandwidth 7 MHz.   */
518  	DRX_BANDWIDTH_6MHZ,	 /*< Bandwidth 6 MHz.   */
519  	DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN,
520  					/*< Bandwidth unknown. */
521  	DRX_BANDWIDTH_AUTO = DRX_AUTO
522  					/*< Auto Set Bandwidth */
523  };
524  
525  /*
526  * \enum enum drx_mirror
527  * \brief Indicate if channel spectrum is mirrored or not.
528  */
529  enum drx_mirror {
530  	DRX_MIRROR_NO = 0,   /*< Spectrum is not mirrored.           */
531  	DRX_MIRROR_YES,	     /*< Spectrum is mirrored.               */
532  	DRX_MIRROR_UNKNOWN = DRX_UNKNOWN,
533  				/*< Unknown if spectrum is mirrored.    */
534  	DRX_MIRROR_AUTO = DRX_AUTO
535  				/*< Autodetect if spectrum is mirrored. */
536  };
537  
538  /*
539  * \enum enum drx_modulation
540  * \brief Constellation type of the channel.
541  */
542  enum drx_modulation {
543  	DRX_CONSTELLATION_BPSK = 0,  /*< Modulation is BPSK.       */
544  	DRX_CONSTELLATION_QPSK,	     /*< Constellation is QPSK.    */
545  	DRX_CONSTELLATION_PSK8,	     /*< Constellation is PSK8.    */
546  	DRX_CONSTELLATION_QAM16,     /*< Constellation is QAM16.   */
547  	DRX_CONSTELLATION_QAM32,     /*< Constellation is QAM32.   */
548  	DRX_CONSTELLATION_QAM64,     /*< Constellation is QAM64.   */
549  	DRX_CONSTELLATION_QAM128,    /*< Constellation is QAM128.  */
550  	DRX_CONSTELLATION_QAM256,    /*< Constellation is QAM256.  */
551  	DRX_CONSTELLATION_QAM512,    /*< Constellation is QAM512.  */
552  	DRX_CONSTELLATION_QAM1024,   /*< Constellation is QAM1024. */
553  	DRX_CONSTELLATION_QPSK_NR,   /*< Constellation is QPSK_NR  */
554  	DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
555  					/*< Constellation unknown.    */
556  	DRX_CONSTELLATION_AUTO = DRX_AUTO
557  					/*< Autodetect constellation. */
558  };
559  
560  /*
561  * \enum enum drx_hierarchy
562  * \brief Hierarchy of the channel.
563  */
564  enum drx_hierarchy {
565  	DRX_HIERARCHY_NONE = 0,	/*< None hierarchical channel.     */
566  	DRX_HIERARCHY_ALPHA1,	/*< Hierarchical channel, alpha=1. */
567  	DRX_HIERARCHY_ALPHA2,	/*< Hierarchical channel, alpha=2. */
568  	DRX_HIERARCHY_ALPHA4,	/*< Hierarchical channel, alpha=4. */
569  	DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN,
570  				/*< Hierarchy unknown.             */
571  	DRX_HIERARCHY_AUTO = DRX_AUTO
572  				/*< Autodetect hierarchy.          */
573  };
574  
575  /*
576  * \enum enum drx_priority
577  * \brief Channel priority in case of hierarchical transmission.
578  */
579  enum drx_priority {
580  	DRX_PRIORITY_LOW = 0,  /*< Low priority channel.  */
581  	DRX_PRIORITY_HIGH,     /*< High priority channel. */
582  	DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN
583  				/*< Priority unknown.      */
584  };
585  
586  /*
587  * \enum enum drx_coderate
588  * \brief Channel priority in case of hierarchical transmission.
589  */
590  enum drx_coderate {
591  		DRX_CODERATE_1DIV2 = 0,	/*< Code rate 1/2nd.      */
592  		DRX_CODERATE_2DIV3,	/*< Code rate 2/3nd.      */
593  		DRX_CODERATE_3DIV4,	/*< Code rate 3/4nd.      */
594  		DRX_CODERATE_5DIV6,	/*< Code rate 5/6nd.      */
595  		DRX_CODERATE_7DIV8,	/*< Code rate 7/8nd.      */
596  		DRX_CODERATE_UNKNOWN = DRX_UNKNOWN,
597  					/*< Code rate unknown.    */
598  		DRX_CODERATE_AUTO = DRX_AUTO
599  					/*< Autodetect code rate. */
600  };
601  
602  /*
603  * \enum enum drx_guard
604  * \brief Guard interval of a channel.
605  */
606  enum drx_guard {
607  	DRX_GUARD_1DIV32 = 0, /*< Guard interval 1/32nd.     */
608  	DRX_GUARD_1DIV16,     /*< Guard interval 1/16th.     */
609  	DRX_GUARD_1DIV8,      /*< Guard interval 1/8th.      */
610  	DRX_GUARD_1DIV4,      /*< Guard interval 1/4th.      */
611  	DRX_GUARD_UNKNOWN = DRX_UNKNOWN,
612  				/*< Guard interval unknown.    */
613  	DRX_GUARD_AUTO = DRX_AUTO
614  				/*< Autodetect guard interval. */
615  };
616  
617  /*
618  * \enum enum drx_fft_mode
619  * \brief FFT mode.
620  */
621  enum drx_fft_mode {
622  	DRX_FFTMODE_2K = 0,    /*< 2K FFT mode.         */
623  	DRX_FFTMODE_4K,	       /*< 4K FFT mode.         */
624  	DRX_FFTMODE_8K,	       /*< 8K FFT mode.         */
625  	DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN,
626  				/*< FFT mode unknown.    */
627  	DRX_FFTMODE_AUTO = DRX_AUTO
628  				/*< Autodetect FFT mode. */
629  };
630  
631  /*
632  * \enum enum drx_classification
633  * \brief Channel classification.
634  */
635  enum drx_classification {
636  	DRX_CLASSIFICATION_GAUSS = 0, /*< Gaussion noise.            */
637  	DRX_CLASSIFICATION_HVY_GAUSS, /*< Heavy Gaussion noise.      */
638  	DRX_CLASSIFICATION_COCHANNEL, /*< Co-channel.                */
639  	DRX_CLASSIFICATION_STATIC,    /*< Static echo.               */
640  	DRX_CLASSIFICATION_MOVING,    /*< Moving echo.               */
641  	DRX_CLASSIFICATION_ZERODB,    /*< Zero dB echo.              */
642  	DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN,
643  					/*< Unknown classification     */
644  	DRX_CLASSIFICATION_AUTO = DRX_AUTO
645  					/*< Autodetect classification. */
646  };
647  
648  /*
649  * /enum enum drx_interleave_mode
650  * /brief Interleave modes
651  */
652  enum drx_interleave_mode {
653  	DRX_INTERLEAVEMODE_I128_J1 = 0,
654  	DRX_INTERLEAVEMODE_I128_J1_V2,
655  	DRX_INTERLEAVEMODE_I128_J2,
656  	DRX_INTERLEAVEMODE_I64_J2,
657  	DRX_INTERLEAVEMODE_I128_J3,
658  	DRX_INTERLEAVEMODE_I32_J4,
659  	DRX_INTERLEAVEMODE_I128_J4,
660  	DRX_INTERLEAVEMODE_I16_J8,
661  	DRX_INTERLEAVEMODE_I128_J5,
662  	DRX_INTERLEAVEMODE_I8_J16,
663  	DRX_INTERLEAVEMODE_I128_J6,
664  	DRX_INTERLEAVEMODE_RESERVED_11,
665  	DRX_INTERLEAVEMODE_I128_J7,
666  	DRX_INTERLEAVEMODE_RESERVED_13,
667  	DRX_INTERLEAVEMODE_I128_J8,
668  	DRX_INTERLEAVEMODE_RESERVED_15,
669  	DRX_INTERLEAVEMODE_I12_J17,
670  	DRX_INTERLEAVEMODE_I5_J4,
671  	DRX_INTERLEAVEMODE_B52_M240,
672  	DRX_INTERLEAVEMODE_B52_M720,
673  	DRX_INTERLEAVEMODE_B52_M48,
674  	DRX_INTERLEAVEMODE_B52_M0,
675  	DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN,
676  					/*< Unknown interleave mode    */
677  	DRX_INTERLEAVEMODE_AUTO = DRX_AUTO
678  					/*< Autodetect interleave mode */
679  };
680  
681  /*
682  * \enum enum drx_carrier_mode
683  * \brief Channel Carrier Mode.
684  */
685  enum drx_carrier_mode {
686  	DRX_CARRIER_MULTI = 0,		/*< Multi carrier mode       */
687  	DRX_CARRIER_SINGLE,		/*< Single carrier mode      */
688  	DRX_CARRIER_UNKNOWN = DRX_UNKNOWN,
689  					/*< Carrier mode unknown.    */
690  	DRX_CARRIER_AUTO = DRX_AUTO	/*< Autodetect carrier mode  */
691  };
692  
693  /*
694  * \enum enum drx_frame_mode
695  * \brief Channel Frame Mode.
696  */
697  enum drx_frame_mode {
698  	DRX_FRAMEMODE_420 = 0,	 /*< 420 with variable PN  */
699  	DRX_FRAMEMODE_595,	 /*< 595                   */
700  	DRX_FRAMEMODE_945,	 /*< 945 with variable PN  */
701  	DRX_FRAMEMODE_420_FIXED_PN,
702  					/*< 420 with fixed PN     */
703  	DRX_FRAMEMODE_945_FIXED_PN,
704  					/*< 945 with fixed PN     */
705  	DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN,
706  					/*< Frame mode unknown.   */
707  	DRX_FRAMEMODE_AUTO = DRX_AUTO
708  					/*< Autodetect frame mode */
709  };
710  
711  /*
712  * \enum enum drx_tps_frame
713  * \brief Frame number in current super-frame.
714  */
715  enum drx_tps_frame {
716  	DRX_TPS_FRAME1 = 0,	  /*< TPS frame 1.       */
717  	DRX_TPS_FRAME2,		  /*< TPS frame 2.       */
718  	DRX_TPS_FRAME3,		  /*< TPS frame 3.       */
719  	DRX_TPS_FRAME4,		  /*< TPS frame 4.       */
720  	DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN
721  					/*< TPS frame unknown. */
722  };
723  
724  /*
725  * \enum enum drx_ldpc
726  * \brief TPS LDPC .
727  */
728  enum drx_ldpc {
729  	DRX_LDPC_0_4 = 0,	  /*< LDPC 0.4           */
730  	DRX_LDPC_0_6,		  /*< LDPC 0.6           */
731  	DRX_LDPC_0_8,		  /*< LDPC 0.8           */
732  	DRX_LDPC_UNKNOWN = DRX_UNKNOWN,
733  					/*< LDPC unknown.      */
734  	DRX_LDPC_AUTO = DRX_AUTO  /*< Autodetect LDPC    */
735  };
736  
737  /*
738  * \enum enum drx_pilot_mode
739  * \brief Pilot modes in DTMB.
740  */
741  enum drx_pilot_mode {
742  	DRX_PILOT_ON = 0,	  /*< Pilot On             */
743  	DRX_PILOT_OFF,		  /*< Pilot Off            */
744  	DRX_PILOT_UNKNOWN = DRX_UNKNOWN,
745  					/*< Pilot unknown.       */
746  	DRX_PILOT_AUTO = DRX_AUTO /*< Autodetect Pilot     */
747  };
748  
749  /*
750   * enum drxu_code_action - indicate if firmware has to be uploaded or verified.
751   * @UCODE_UPLOAD:	Upload the microcode image to device
752   * @UCODE_VERIFY:	Compare microcode image with code on device
753   */
754  enum drxu_code_action {
755  	UCODE_UPLOAD,
756  	UCODE_VERIFY
757  };
758  
759  /*
760  * \enum enum drx_lock_status * \brief Used to reflect current lock status of demodulator.
761  *
762  * The generic lock states have device dependent semantics.
763  
764  		DRX_NEVER_LOCK = 0,
765  			      **< Device will never lock on this signal *
766  		DRX_NOT_LOCKED,
767  			      **< Device has no lock at all             *
768  		DRX_LOCK_STATE_1,
769  			      **< Generic lock state                    *
770  		DRX_LOCK_STATE_2,
771  			      **< Generic lock state                    *
772  		DRX_LOCK_STATE_3,
773  			      **< Generic lock state                    *
774  		DRX_LOCK_STATE_4,
775  			      **< Generic lock state                    *
776  		DRX_LOCK_STATE_5,
777  			      **< Generic lock state                    *
778  		DRX_LOCK_STATE_6,
779  			      **< Generic lock state                    *
780  		DRX_LOCK_STATE_7,
781  			      **< Generic lock state                    *
782  		DRX_LOCK_STATE_8,
783  			      **< Generic lock state                    *
784  		DRX_LOCK_STATE_9,
785  			      **< Generic lock state                    *
786  		DRX_LOCKED    **< Device is in lock                     *
787  */
788  
789  enum drx_lock_status {
790  	DRX_NEVER_LOCK = 0,
791  	DRX_NOT_LOCKED,
792  	DRX_LOCK_STATE_1,
793  	DRX_LOCK_STATE_2,
794  	DRX_LOCK_STATE_3,
795  	DRX_LOCK_STATE_4,
796  	DRX_LOCK_STATE_5,
797  	DRX_LOCK_STATE_6,
798  	DRX_LOCK_STATE_7,
799  	DRX_LOCK_STATE_8,
800  	DRX_LOCK_STATE_9,
801  	DRX_LOCKED
802  };
803  
804  /*
805  * \enum enum drx_uio* \brief Used to address a User IO (UIO).
806  */
807  enum drx_uio {
808  	DRX_UIO1,
809  	DRX_UIO2,
810  	DRX_UIO3,
811  	DRX_UIO4,
812  	DRX_UIO5,
813  	DRX_UIO6,
814  	DRX_UIO7,
815  	DRX_UIO8,
816  	DRX_UIO9,
817  	DRX_UIO10,
818  	DRX_UIO11,
819  	DRX_UIO12,
820  	DRX_UIO13,
821  	DRX_UIO14,
822  	DRX_UIO15,
823  	DRX_UIO16,
824  	DRX_UIO17,
825  	DRX_UIO18,
826  	DRX_UIO19,
827  	DRX_UIO20,
828  	DRX_UIO21,
829  	DRX_UIO22,
830  	DRX_UIO23,
831  	DRX_UIO24,
832  	DRX_UIO25,
833  	DRX_UIO26,
834  	DRX_UIO27,
835  	DRX_UIO28,
836  	DRX_UIO29,
837  	DRX_UIO30,
838  	DRX_UIO31,
839  	DRX_UIO32,
840  	DRX_UIO_MAX = DRX_UIO32
841  };
842  
843  /*
844  * \enum enum drxuio_mode * \brief Used to configure the modus oprandi of a UIO.
845  *
846  * DRX_UIO_MODE_FIRMWARE is an old uio mode.
847  * It is replaced by the modes DRX_UIO_MODE_FIRMWARE0 .. DRX_UIO_MODE_FIRMWARE9.
848  * To be backward compatible DRX_UIO_MODE_FIRMWARE is equivalent to
849  * DRX_UIO_MODE_FIRMWARE0.
850  */
851  enum drxuio_mode {
852  	DRX_UIO_MODE_DISABLE = 0x01,
853  			    /*< not used, pin is configured as input */
854  	DRX_UIO_MODE_READWRITE = 0x02,
855  			    /*< used for read/write by application   */
856  	DRX_UIO_MODE_FIRMWARE = 0x04,
857  			    /*< controlled by firmware, function 0   */
858  	DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE,
859  					    /*< same as above        */
860  	DRX_UIO_MODE_FIRMWARE1 = 0x08,
861  			    /*< controlled by firmware, function 1   */
862  	DRX_UIO_MODE_FIRMWARE2 = 0x10,
863  			    /*< controlled by firmware, function 2   */
864  	DRX_UIO_MODE_FIRMWARE3 = 0x20,
865  			    /*< controlled by firmware, function 3   */
866  	DRX_UIO_MODE_FIRMWARE4 = 0x40,
867  			    /*< controlled by firmware, function 4   */
868  	DRX_UIO_MODE_FIRMWARE5 = 0x80
869  			    /*< controlled by firmware, function 5   */
870  };
871  
872  /*
873  * \enum enum drxoob_downstream_standard * \brief Used to select OOB standard.
874  *
875  * Based on ANSI 55-1 and 55-2
876  */
877  enum drxoob_downstream_standard {
878  	DRX_OOB_MODE_A = 0,
879  		       /*< ANSI 55-1   */
880  	DRX_OOB_MODE_B_GRADE_A,
881  		       /*< ANSI 55-2 A */
882  	DRX_OOB_MODE_B_GRADE_B
883  		       /*< ANSI 55-2 B */
884  };
885  
886  /*-------------------------------------------------------------------------
887  STRUCTS
888  -------------------------------------------------------------------------*/
889  
890  /*============================================================================*/
891  /*============================================================================*/
892  /*== CTRL CFG related data structures ========================================*/
893  /*============================================================================*/
894  /*============================================================================*/
895  
896  #ifndef DRX_CFG_BASE
897  #define DRX_CFG_BASE          0
898  #endif
899  
900  #define DRX_CFG_MPEG_OUTPUT         (DRX_CFG_BASE +  0)	/* MPEG TS output    */
901  #define DRX_CFG_PKTERR              (DRX_CFG_BASE +  1)	/* Packet Error      */
902  #define DRX_CFG_SYMCLK_OFFS         (DRX_CFG_BASE +  2)	/* Symbol Clk Offset */
903  #define DRX_CFG_SMA                 (DRX_CFG_BASE +  3)	/* Smart Antenna     */
904  #define DRX_CFG_PINSAFE             (DRX_CFG_BASE +  4)	/* Pin safe mode     */
905  #define DRX_CFG_SUBSTANDARD         (DRX_CFG_BASE +  5)	/* substandard       */
906  #define DRX_CFG_AUD_VOLUME          (DRX_CFG_BASE +  6)	/* volume            */
907  #define DRX_CFG_AUD_RDS             (DRX_CFG_BASE +  7)	/* rds               */
908  #define DRX_CFG_AUD_AUTOSOUND       (DRX_CFG_BASE +  8)	/* ASS & ASC         */
909  #define DRX_CFG_AUD_ASS_THRES       (DRX_CFG_BASE +  9)	/* ASS Thresholds    */
910  #define DRX_CFG_AUD_DEVIATION       (DRX_CFG_BASE + 10)	/* Deviation         */
911  #define DRX_CFG_AUD_PRESCALE        (DRX_CFG_BASE + 11)	/* Prescale          */
912  #define DRX_CFG_AUD_MIXER           (DRX_CFG_BASE + 12)	/* Mixer             */
913  #define DRX_CFG_AUD_AVSYNC          (DRX_CFG_BASE + 13)	/* AVSync            */
914  #define DRX_CFG_AUD_CARRIER         (DRX_CFG_BASE + 14)	/* Audio carriers    */
915  #define DRX_CFG_I2S_OUTPUT          (DRX_CFG_BASE + 15)	/* I2S output        */
916  #define DRX_CFG_ATV_STANDARD        (DRX_CFG_BASE + 16)	/* ATV standard      */
917  #define DRX_CFG_SQI_SPEED           (DRX_CFG_BASE + 17)	/* SQI speed         */
918  #define DRX_CTRL_CFG_MAX            (DRX_CFG_BASE + 18)	/* never to be used  */
919  
920  #define DRX_CFG_PINS_SAFE_MODE      DRX_CFG_PINSAFE
921  /*============================================================================*/
922  /*============================================================================*/
923  /*== CTRL related data structures ============================================*/
924  /*============================================================================*/
925  /*============================================================================*/
926  
927  /*
928   * struct drxu_code_info	Parameters for microcode upload and verfiy.
929   *
930   * @mc_file:	microcode file name
931   *
932   * Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE
933   */
934  struct drxu_code_info {
935  	char			*mc_file;
936  };
937  
938  /*
939  * \struct drx_mc_version_rec_t
940  * \brief Microcode version record
941  * Version numbers are stored in BCD format, as usual:
942  *   o major number = bits 31-20 (first three nibbles of MSW)
943  *   o minor number = bits 19-16 (fourth nibble of MSW)
944  *   o patch number = bits 15-0  (remaining nibbles in LSW)
945  *
946  * The device type indicates for which the device is meant. It is based on the
947  * JTAG ID, using everything except the bond ID and the metal fix.
948  *
949  * Special values:
950  * - mc_dev_type == 0         => any device allowed
951  * - mc_base_version == 0.0.0 => full microcode (mc_version is the version)
952  * - mc_base_version != 0.0.0 => patch microcode, the base microcode version
953  *                             (mc_version is the version)
954  */
955  #define AUX_VER_RECORD 0x8000
956  
957  struct drx_mc_version_rec {
958  	u16 aux_type;	/* type of aux data - 0x8000 for version record     */
959  	u32 mc_dev_type;	/* device type, based on JTAG ID                    */
960  	u32 mc_version;	/* version of microcode                             */
961  	u32 mc_base_version;	/* in case of patch: the original microcode version */
962  };
963  
964  /*========================================*/
965  
966  /*
967  * \struct drx_filter_info_t
968  * \brief Parameters for loading filter coefficients
969  *
970  * Used by DRX_CTRL_LOAD_FILTER
971  */
972  struct drx_filter_info {
973  	u8 *data_re;
974  	      /*< pointer to coefficients for RE */
975  	u8 *data_im;
976  	      /*< pointer to coefficients for IM */
977  	u16 size_re;
978  	      /*< size of coefficients for RE    */
979  	u16 size_im;
980  	      /*< size of coefficients for IM    */
981  };
982  
983  /*========================================*/
984  
985  /*
986  * \struct struct drx_channel * \brief The set of parameters describing a single channel.
987  *
988  * Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL.
989  * Only certain fields need to be used for a specific standard.
990  *
991  */
992  struct drx_channel {
993  	s32 frequency;
994  				/*< frequency in kHz                 */
995  	enum drx_bandwidth bandwidth;
996  				/*< bandwidth                        */
997  	enum drx_mirror mirror;	/*< mirrored or not on RF            */
998  	enum drx_modulation constellation;
999  				/*< constellation                    */
1000  	enum drx_hierarchy hierarchy;
1001  				/*< hierarchy                        */
1002  	enum drx_priority priority;	/*< priority                         */
1003  	enum drx_coderate coderate;	/*< coderate                         */
1004  	enum drx_guard guard;	/*< guard interval                   */
1005  	enum drx_fft_mode fftmode;	/*< fftmode                          */
1006  	enum drx_classification classification;
1007  				/*< classification                   */
1008  	u32 symbolrate;
1009  				/*< symbolrate in symbols/sec        */
1010  	enum drx_interleave_mode interleavemode;
1011  				/*< interleaveMode QAM               */
1012  	enum drx_ldpc ldpc;		/*< ldpc                             */
1013  	enum drx_carrier_mode carrier;	/*< carrier                          */
1014  	enum drx_frame_mode framemode;
1015  				/*< frame mode                       */
1016  	enum drx_pilot_mode pilot;	/*< pilot mode                       */
1017  };
1018  
1019  /*========================================*/
1020  
1021  enum drx_cfg_sqi_speed {
1022  	DRX_SQI_SPEED_FAST = 0,
1023  	DRX_SQI_SPEED_MEDIUM,
1024  	DRX_SQI_SPEED_SLOW,
1025  	DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
1026  };
1027  
1028  /*========================================*/
1029  
1030  /*
1031  * \struct struct drx_complex * A complex number.
1032  *
1033  * Used by DRX_CTRL_CONSTEL.
1034  */
1035  struct drx_complex {
1036  	s16 im;
1037       /*< Imaginary part. */
1038  	s16 re;
1039       /*< Real part.      */
1040  };
1041  
1042  /*========================================*/
1043  
1044  /*
1045  * \struct struct drx_frequency_plan * Array element of a frequency plan.
1046  *
1047  * Used by DRX_CTRL_SCAN_INIT.
1048  */
1049  struct drx_frequency_plan {
1050  	s32 first;
1051  		     /*< First centre frequency in this band        */
1052  	s32 last;
1053  		     /*< Last centre frequency in this band         */
1054  	s32 step;
1055  		     /*< Stepping frequency in this band            */
1056  	enum drx_bandwidth bandwidth;
1057  		     /*< Bandwidth within this frequency band       */
1058  	u16 ch_number;
1059  		     /*< First channel number in this band, or first
1060  			    index in ch_names                         */
1061  	char **ch_names;
1062  		     /*< Optional list of channel names in this
1063  			    band                                     */
1064  };
1065  
1066  /*========================================*/
1067  
1068  /*
1069  * \struct struct drx_scan_param * Parameters for channel scan.
1070  *
1071  * Used by DRX_CTRL_SCAN_INIT.
1072  */
1073  struct drx_scan_param {
1074  	struct drx_frequency_plan *frequency_plan;
1075  				  /*< Frequency plan (array)*/
1076  	u16 frequency_plan_size;  /*< Number of bands       */
1077  	u32 num_tries;		  /*< Max channels tried    */
1078  	s32 skip;	  /*< Minimum frequency step to take
1079  					after a channel is found */
1080  	void *ext_params;	  /*< Standard specific params */
1081  };
1082  
1083  /*========================================*/
1084  
1085  /*
1086  * \brief Scan commands.
1087  * Used by scanning algorithms.
1088  */
1089  enum drx_scan_command {
1090  		DRX_SCAN_COMMAND_INIT = 0,/*< Initialize scanning */
1091  		DRX_SCAN_COMMAND_NEXT,	  /*< Next scan           */
1092  		DRX_SCAN_COMMAND_STOP	  /*< Stop scanning       */
1093  };
1094  
1095  /*========================================*/
1096  
1097  /*
1098  * \brief Inner scan function prototype.
1099  */
1100  typedef int(*drx_scan_func_t) (void *scan_context,
1101  				     enum drx_scan_command scan_command,
1102  				     struct drx_channel *scan_channel,
1103  				     bool *get_next_channel);
1104  
1105  /*========================================*/
1106  
1107  /*
1108  * \struct struct drxtps_info * TPS information, DVB-T specific.
1109  *
1110  * Used by DRX_CTRL_TPS_INFO.
1111  */
1112  	struct drxtps_info {
1113  		enum drx_fft_mode fftmode;	/*< Fft mode       */
1114  		enum drx_guard guard;	/*< Guard interval */
1115  		enum drx_modulation constellation;
1116  					/*< Constellation  */
1117  		enum drx_hierarchy hierarchy;
1118  					/*< Hierarchy      */
1119  		enum drx_coderate high_coderate;
1120  					/*< High code rate */
1121  		enum drx_coderate low_coderate;
1122  					/*< Low cod rate   */
1123  		enum drx_tps_frame frame;	/*< Tps frame      */
1124  		u8 length;		/*< Length         */
1125  		u16 cell_id;		/*< Cell id        */
1126  	};
1127  
1128  /*========================================*/
1129  
1130  /*
1131  * \brief Power mode of device.
1132  *
1133  * Used by DRX_CTRL_SET_POWER_MODE.
1134  */
1135  	enum drx_power_mode {
1136  		DRX_POWER_UP = 0,
1137  			 /*< Generic         , Power Up Mode   */
1138  		DRX_POWER_MODE_1,
1139  			 /*< Device specific , Power Up Mode   */
1140  		DRX_POWER_MODE_2,
1141  			 /*< Device specific , Power Up Mode   */
1142  		DRX_POWER_MODE_3,
1143  			 /*< Device specific , Power Up Mode   */
1144  		DRX_POWER_MODE_4,
1145  			 /*< Device specific , Power Up Mode   */
1146  		DRX_POWER_MODE_5,
1147  			 /*< Device specific , Power Up Mode   */
1148  		DRX_POWER_MODE_6,
1149  			 /*< Device specific , Power Up Mode   */
1150  		DRX_POWER_MODE_7,
1151  			 /*< Device specific , Power Up Mode   */
1152  		DRX_POWER_MODE_8,
1153  			 /*< Device specific , Power Up Mode   */
1154  
1155  		DRX_POWER_MODE_9,
1156  			 /*< Device specific , Power Down Mode */
1157  		DRX_POWER_MODE_10,
1158  			 /*< Device specific , Power Down Mode */
1159  		DRX_POWER_MODE_11,
1160  			 /*< Device specific , Power Down Mode */
1161  		DRX_POWER_MODE_12,
1162  			 /*< Device specific , Power Down Mode */
1163  		DRX_POWER_MODE_13,
1164  			 /*< Device specific , Power Down Mode */
1165  		DRX_POWER_MODE_14,
1166  			 /*< Device specific , Power Down Mode */
1167  		DRX_POWER_MODE_15,
1168  			 /*< Device specific , Power Down Mode */
1169  		DRX_POWER_MODE_16,
1170  			 /*< Device specific , Power Down Mode */
1171  		DRX_POWER_DOWN = 255
1172  			 /*< Generic         , Power Down Mode */
1173  	};
1174  
1175  /*========================================*/
1176  
1177  /*
1178  * \enum enum drx_module * \brief Software module identification.
1179  *
1180  * Used by DRX_CTRL_VERSION.
1181  */
1182  	enum drx_module {
1183  		DRX_MODULE_DEVICE,
1184  		DRX_MODULE_MICROCODE,
1185  		DRX_MODULE_DRIVERCORE,
1186  		DRX_MODULE_DEVICEDRIVER,
1187  		DRX_MODULE_DAP,
1188  		DRX_MODULE_BSP_I2C,
1189  		DRX_MODULE_BSP_TUNER,
1190  		DRX_MODULE_BSP_HOST,
1191  		DRX_MODULE_UNKNOWN
1192  	};
1193  
1194  /*
1195  * \enum struct drx_version * \brief Version information of one software module.
1196  *
1197  * Used by DRX_CTRL_VERSION.
1198  */
1199  	struct drx_version {
1200  		enum drx_module module_type;
1201  			       /*< Type identifier of the module */
1202  		char *module_name;
1203  			       /*< Name or description of module */
1204  		u16 v_major;  /*< Major version number          */
1205  		u16 v_minor;  /*< Minor version number          */
1206  		u16 v_patch;  /*< Patch version number          */
1207  		char *v_string; /*< Version as text string        */
1208  	};
1209  
1210  /*
1211  * \enum struct drx_version_list * \brief List element of NULL terminated, linked list for version information.
1212  *
1213  * Used by DRX_CTRL_VERSION.
1214  */
1215  struct drx_version_list {
1216  	struct drx_version *version;/*< Version information */
1217  	struct drx_version_list *next;
1218  			      /*< Next list element   */
1219  };
1220  
1221  /*========================================*/
1222  
1223  /*
1224  * \brief Parameters needed to confiugure a UIO.
1225  *
1226  * Used by DRX_CTRL_UIO_CFG.
1227  */
1228  	struct drxuio_cfg {
1229  		enum drx_uio uio;
1230  		       /*< UIO identifier       */
1231  		enum drxuio_mode mode;
1232  		       /*< UIO operational mode */
1233  	};
1234  
1235  /*========================================*/
1236  
1237  /*
1238  * \brief Parameters needed to read from or write to a UIO.
1239  *
1240  * Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE.
1241  */
1242  	struct drxuio_data {
1243  		enum drx_uio uio;
1244  		   /*< UIO identifier              */
1245  		bool value;
1246  		   /*< UIO value (true=1, false=0) */
1247  	};
1248  
1249  /*========================================*/
1250  
1251  /*
1252  * \brief Parameters needed to configure OOB.
1253  *
1254  * Used by DRX_CTRL_SET_OOB.
1255  */
1256  	struct drxoob {
1257  		s32 frequency;	   /*< Frequency in kHz      */
1258  		enum drxoob_downstream_standard standard;
1259  						   /*< OOB standard          */
1260  		bool spectrum_inverted;	   /*< If true, then spectrum
1261  							 is inverted          */
1262  	};
1263  
1264  /*========================================*/
1265  
1266  /*
1267  * \brief Metrics from OOB.
1268  *
1269  * Used by DRX_CTRL_GET_OOB.
1270  */
1271  	struct drxoob_status {
1272  		s32 frequency; /*< Frequency in Khz         */
1273  		enum drx_lock_status lock;	  /*< Lock status              */
1274  		u32 mer;		  /*< MER                      */
1275  		s32 symbol_rate_offset;	  /*< Symbolrate offset in ppm */
1276  	};
1277  
1278  /*========================================*/
1279  
1280  /*
1281  * \brief Device dependent configuration data.
1282  *
1283  * Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG.
1284  * A sort of nested drx_ctrl() functionality for device specific controls.
1285  */
1286  	struct drx_cfg {
1287  		u32 cfg_type;
1288  			  /*< Function identifier */
1289  		void *cfg_data;
1290  			  /*< Function data */
1291  	};
1292  
1293  /*========================================*/
1294  
1295  /*
1296  * /struct DRXMpegStartWidth_t
1297  * MStart width [nr MCLK cycles] for serial MPEG output.
1298  */
1299  
1300  	enum drxmpeg_str_width {
1301  		DRX_MPEG_STR_WIDTH_1,
1302  		DRX_MPEG_STR_WIDTH_8
1303  	};
1304  
1305  /* CTRL CFG MPEG output */
1306  /*
1307  * \struct struct drx_cfg_mpeg_output * \brief Configuration parameters for MPEG output control.
1308  *
1309  * Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and
1310  * DRX_CTRL_GET_CFG.
1311  */
1312  
1313  	struct drx_cfg_mpeg_output {
1314  		bool enable_mpeg_output;/*< If true, enable MPEG output      */
1315  		bool insert_rs_byte;	/*< If true, insert RS byte          */
1316  		bool enable_parallel;	/*< If true, parallel out otherwise
1317  								     serial   */
1318  		bool invert_data;	/*< If true, invert DATA signals     */
1319  		bool invert_err;	/*< If true, invert ERR signal       */
1320  		bool invert_str;	/*< If true, invert STR signals      */
1321  		bool invert_val;	/*< If true, invert VAL signals      */
1322  		bool invert_clk;	/*< If true, invert CLK signals      */
1323  		bool static_clk;	/*< If true, static MPEG clockrate
1324  					     will be used, otherwise clockrate
1325  					     will adapt to the bitrate of the
1326  					     TS                               */
1327  		u32 bitrate;		/*< Maximum bitrate in b/s in case
1328  					     static clockrate is selected     */
1329  		enum drxmpeg_str_width width_str;
1330  					/*< MPEG start width                 */
1331  	};
1332  
1333  
1334  /*========================================*/
1335  
1336  /*
1337  * \struct struct drxi2c_data * \brief Data for I2C via 2nd or 3rd or etc I2C port.
1338  *
1339  * Used by DRX_CTRL_I2C_READWRITE.
1340  * If port_nr is equal to primairy port_nr BSPI2C will be used.
1341  *
1342  */
1343  	struct drxi2c_data {
1344  		u16 port_nr;	/*< I2C port number               */
1345  		struct i2c_device_addr *w_dev_addr;
1346  				/*< Write device address          */
1347  		u16 w_count;	/*< Size of write data in bytes   */
1348  		u8 *wData;	/*< Pointer to write data         */
1349  		struct i2c_device_addr *r_dev_addr;
1350  				/*< Read device address           */
1351  		u16 r_count;	/*< Size of data to read in bytes */
1352  		u8 *r_data;	/*< Pointer to read buffer        */
1353  	};
1354  
1355  /*========================================*/
1356  
1357  /*
1358  * \enum enum drx_aud_standard * \brief Audio standard identifier.
1359  *
1360  * Used by DRX_CTRL_SET_AUD.
1361  */
1362  	enum drx_aud_standard {
1363  		DRX_AUD_STANDARD_BTSC,	   /*< set BTSC standard (USA)       */
1364  		DRX_AUD_STANDARD_A2,	   /*< set A2-Korea FM Stereo        */
1365  		DRX_AUD_STANDARD_EIAJ,	   /*< set to Japanese FM Stereo     */
1366  		DRX_AUD_STANDARD_FM_STEREO,/*< set to FM-Stereo Radio        */
1367  		DRX_AUD_STANDARD_M_MONO,   /*< for 4.5 MHz mono detected     */
1368  		DRX_AUD_STANDARD_D_K_MONO, /*< for 6.5 MHz mono detected     */
1369  		DRX_AUD_STANDARD_BG_FM,	   /*< set BG_FM standard            */
1370  		DRX_AUD_STANDARD_D_K1,	   /*< set D_K1 standard             */
1371  		DRX_AUD_STANDARD_D_K2,	   /*< set D_K2 standard             */
1372  		DRX_AUD_STANDARD_D_K3,	   /*< set D_K3 standard             */
1373  		DRX_AUD_STANDARD_BG_NICAM_FM,
1374  					   /*< set BG_NICAM_FM standard      */
1375  		DRX_AUD_STANDARD_L_NICAM_AM,
1376  					   /*< set L_NICAM_AM standard       */
1377  		DRX_AUD_STANDARD_I_NICAM_FM,
1378  					   /*< set I_NICAM_FM standard       */
1379  		DRX_AUD_STANDARD_D_K_NICAM_FM,
1380  					   /*< set D_K_NICAM_FM standard     */
1381  		DRX_AUD_STANDARD_NOT_READY,/*< used to detect audio standard */
1382  		DRX_AUD_STANDARD_AUTO = DRX_AUTO,
1383  					   /*< Automatic Standard Detection  */
1384  		DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN
1385  					   /*< used as auto and for readback */
1386  	};
1387  
1388  /* CTRL_AUD_GET_STATUS    - struct drx_aud_status */
1389  /*
1390  * \enum enum drx_aud_nicam_status * \brief Status of NICAM carrier.
1391  */
1392  	enum drx_aud_nicam_status {
1393  		DRX_AUD_NICAM_DETECTED = 0,
1394  					  /*< NICAM carrier detected         */
1395  		DRX_AUD_NICAM_NOT_DETECTED,
1396  					  /*< NICAM carrier not detected     */
1397  		DRX_AUD_NICAM_BAD	  /*< NICAM carrier bad quality      */
1398  	};
1399  
1400  /*
1401  * \struct struct drx_aud_status * \brief Audio status characteristics.
1402  */
1403  	struct drx_aud_status {
1404  		bool stereo;		  /*< stereo detection               */
1405  		bool carrier_a;	  /*< carrier A detected             */
1406  		bool carrier_b;	  /*< carrier B detected             */
1407  		bool sap;		  /*< sap / bilingual detection      */
1408  		bool rds;		  /*< RDS data array present         */
1409  		enum drx_aud_nicam_status nicam_status;
1410  					  /*< status of NICAM carrier        */
1411  		s8 fm_ident;		  /*< FM Identification value        */
1412  	};
1413  
1414  /* CTRL_AUD_READ_RDS       - DRXRDSdata_t */
1415  
1416  /*
1417  * \struct DRXRDSdata_t
1418  * \brief Raw RDS data array.
1419  */
1420  	struct drx_cfg_aud_rds {
1421  		bool valid;		  /*< RDS data validation            */
1422  		u16 data[18];		  /*< data from one RDS data array   */
1423  	};
1424  
1425  /* DRX_CFG_AUD_VOLUME      - struct drx_cfg_aud_volume - set/get */
1426  /*
1427  * \enum DRXAudAVCDecayTime_t
1428  * \brief Automatic volume control configuration.
1429  */
1430  	enum drx_aud_avc_mode {
1431  		DRX_AUD_AVC_OFF,	  /*< Automatic volume control off   */
1432  		DRX_AUD_AVC_DECAYTIME_8S, /*< level volume in  8 seconds     */
1433  		DRX_AUD_AVC_DECAYTIME_4S, /*< level volume in  4 seconds     */
1434  		DRX_AUD_AVC_DECAYTIME_2S, /*< level volume in  2 seconds     */
1435  		DRX_AUD_AVC_DECAYTIME_20MS/*< level volume in 20 millisec    */
1436  	};
1437  
1438  /*
1439  * /enum DRXAudMaxAVCGain_t
1440  * /brief Automatic volume control max gain in audio baseband.
1441  */
1442  	enum drx_aud_avc_max_gain {
1443  		DRX_AUD_AVC_MAX_GAIN_0DB, /*< maximum AVC gain  0 dB         */
1444  		DRX_AUD_AVC_MAX_GAIN_6DB, /*< maximum AVC gain  6 dB         */
1445  		DRX_AUD_AVC_MAX_GAIN_12DB /*< maximum AVC gain 12 dB         */
1446  	};
1447  
1448  /*
1449  * /enum DRXAudMaxAVCAtten_t
1450  * /brief Automatic volume control max attenuation in audio baseband.
1451  */
1452  	enum drx_aud_avc_max_atten {
1453  		DRX_AUD_AVC_MAX_ATTEN_12DB,
1454  					  /*< maximum AVC attenuation 12 dB  */
1455  		DRX_AUD_AVC_MAX_ATTEN_18DB,
1456  					  /*< maximum AVC attenuation 18 dB  */
1457  		DRX_AUD_AVC_MAX_ATTEN_24DB/*< maximum AVC attenuation 24 dB  */
1458  	};
1459  /*
1460  * \struct struct drx_cfg_aud_volume * \brief Audio volume configuration.
1461  */
1462  	struct drx_cfg_aud_volume {
1463  		bool mute;		  /*< mute overrides volume setting  */
1464  		s16 volume;		  /*< volume, range -114 to 12 dB    */
1465  		enum drx_aud_avc_mode avc_mode;  /*< AVC auto volume control mode   */
1466  		u16 avc_ref_level;	  /*< AVC reference level            */
1467  		enum drx_aud_avc_max_gain avc_max_gain;
1468  					  /*< AVC max gain selection         */
1469  		enum drx_aud_avc_max_atten avc_max_atten;
1470  					  /*< AVC max attenuation selection  */
1471  		s16 strength_left;	  /*< quasi-peak, left speaker       */
1472  		s16 strength_right;	  /*< quasi-peak, right speaker      */
1473  	};
1474  
1475  /* DRX_CFG_I2S_OUTPUT      - struct drx_cfg_i2s_output - set/get */
1476  /*
1477  * \enum enum drxi2s_mode * \brief I2S output mode.
1478  */
1479  	enum drxi2s_mode {
1480  		DRX_I2S_MODE_MASTER,	  /*< I2S is in master mode          */
1481  		DRX_I2S_MODE_SLAVE	  /*< I2S is in slave mode           */
1482  	};
1483  
1484  /*
1485  * \enum enum drxi2s_word_length * \brief Width of I2S data.
1486  */
1487  	enum drxi2s_word_length {
1488  		DRX_I2S_WORDLENGTH_32 = 0,/*< I2S data is 32 bit wide        */
1489  		DRX_I2S_WORDLENGTH_16 = 1 /*< I2S data is 16 bit wide        */
1490  	};
1491  
1492  /*
1493  * \enum enum drxi2s_format * \brief Data wordstrobe alignment for I2S.
1494  */
1495  	enum drxi2s_format {
1496  		DRX_I2S_FORMAT_WS_WITH_DATA,
1497  				    /*< I2S data and wordstrobe are aligned  */
1498  		DRX_I2S_FORMAT_WS_ADVANCED
1499  				    /*< I2S data one cycle after wordstrobe  */
1500  	};
1501  
1502  /*
1503  * \enum enum drxi2s_polarity * \brief Polarity of I2S data.
1504  */
1505  	enum drxi2s_polarity {
1506  		DRX_I2S_POLARITY_RIGHT,/*< wordstrobe - right high, left low */
1507  		DRX_I2S_POLARITY_LEFT  /*< wordstrobe - right low, left high */
1508  	};
1509  
1510  /*
1511  * \struct struct drx_cfg_i2s_output * \brief I2S output configuration.
1512  */
1513  	struct drx_cfg_i2s_output {
1514  		bool output_enable;	  /*< I2S output enable              */
1515  		u32 frequency;	  /*< range from 8000-48000 Hz       */
1516  		enum drxi2s_mode mode;	  /*< I2S mode, master or slave      */
1517  		enum drxi2s_word_length word_length;
1518  					  /*< I2S wordlength, 16 or 32 bits  */
1519  		enum drxi2s_polarity polarity;/*< I2S wordstrobe polarity        */
1520  		enum drxi2s_format format;	  /*< I2S wordstrobe delay to data   */
1521  	};
1522  
1523  /* ------------------------------expert interface-----------------------------*/
1524  /*
1525  * /enum enum drx_aud_fm_deemphasis * setting for FM-Deemphasis in audio demodulator.
1526  *
1527  */
1528  	enum drx_aud_fm_deemphasis {
1529  		DRX_AUD_FM_DEEMPH_50US,
1530  		DRX_AUD_FM_DEEMPH_75US,
1531  		DRX_AUD_FM_DEEMPH_OFF
1532  	};
1533  
1534  /*
1535  * /enum DRXAudDeviation_t
1536  * setting for deviation mode in audio demodulator.
1537  *
1538  */
1539  	enum drx_cfg_aud_deviation {
1540  		DRX_AUD_DEVIATION_NORMAL,
1541  		DRX_AUD_DEVIATION_HIGH
1542  	};
1543  
1544  /*
1545  * /enum enum drx_no_carrier_option * setting for carrier, mute/noise.
1546  *
1547  */
1548  	enum drx_no_carrier_option {
1549  		DRX_NO_CARRIER_MUTE,
1550  		DRX_NO_CARRIER_NOISE
1551  	};
1552  
1553  /*
1554  * \enum DRXAudAutoSound_t
1555  * \brief Automatic Sound
1556  */
1557  	enum drx_cfg_aud_auto_sound {
1558  		DRX_AUD_AUTO_SOUND_OFF = 0,
1559  		DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON,
1560  		DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF
1561  	};
1562  
1563  /*
1564  * \enum DRXAudASSThres_t
1565  * \brief Automatic Sound Select Thresholds
1566  */
1567  	struct drx_cfg_aud_ass_thres {
1568  		u16 a2;	/* A2 Threshold for ASS configuration */
1569  		u16 btsc;	/* BTSC Threshold for ASS configuration */
1570  		u16 nicam;	/* Nicam Threshold for ASS configuration */
1571  	};
1572  
1573  /*
1574  * \struct struct drx_aud_carrier * \brief Carrier detection related parameters
1575  */
1576  	struct drx_aud_carrier {
1577  		u16 thres;	/* carrier detetcion threshold for primary carrier (A) */
1578  		enum drx_no_carrier_option opt;	/* Mute or noise at no carrier detection (A) */
1579  		s32 shift;	/* DC level of incoming signal (A) */
1580  		s32 dco;	/* frequency adjustment (A) */
1581  	};
1582  
1583  /*
1584  * \struct struct drx_cfg_aud_carriers * \brief combining carrier A & B to one struct
1585  */
1586  	struct drx_cfg_aud_carriers {
1587  		struct drx_aud_carrier a;
1588  		struct drx_aud_carrier b;
1589  	};
1590  
1591  /*
1592  * /enum enum drx_aud_i2s_src * Selection of audio source
1593  */
1594  	enum drx_aud_i2s_src {
1595  		DRX_AUD_SRC_MONO,
1596  		DRX_AUD_SRC_STEREO_OR_AB,
1597  		DRX_AUD_SRC_STEREO_OR_A,
1598  		DRX_AUD_SRC_STEREO_OR_B};
1599  
1600  /*
1601  * \enum enum drx_aud_i2s_matrix * \brief Used for selecting I2S output.
1602  */
1603  	enum drx_aud_i2s_matrix {
1604  		DRX_AUD_I2S_MATRIX_A_MONO,
1605  					/*< A sound only, stereo or mono     */
1606  		DRX_AUD_I2S_MATRIX_B_MONO,
1607  					/*< B sound only, stereo or mono     */
1608  		DRX_AUD_I2S_MATRIX_STEREO,
1609  					/*< A+B sound, transparent           */
1610  		DRX_AUD_I2S_MATRIX_MONO	/*< A+B mixed to mono sum, (L+R)/2   */};
1611  
1612  /*
1613  * /enum enum drx_aud_fm_matrix * setting for FM-Matrix in audio demodulator.
1614  *
1615  */
1616  	enum drx_aud_fm_matrix {
1617  		DRX_AUD_FM_MATRIX_NO_MATRIX,
1618  		DRX_AUD_FM_MATRIX_GERMAN,
1619  		DRX_AUD_FM_MATRIX_KOREAN,
1620  		DRX_AUD_FM_MATRIX_SOUND_A,
1621  		DRX_AUD_FM_MATRIX_SOUND_B};
1622  
1623  /*
1624  * \struct DRXAudMatrices_t
1625  * \brief Mixer settings
1626  */
1627  struct drx_cfg_aud_mixer {
1628  	enum drx_aud_i2s_src source_i2s;
1629  	enum drx_aud_i2s_matrix matrix_i2s;
1630  	enum drx_aud_fm_matrix matrix_fm;
1631  };
1632  
1633  /*
1634  * \enum DRXI2SVidSync_t
1635  * \brief Audio/video synchronization, interacts with I2S mode.
1636  * AUTO_1 and AUTO_2 are for automatic video standard detection with preference
1637  * for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz)
1638  */
1639  	enum drx_cfg_aud_av_sync {
1640  		DRX_AUD_AVSYNC_OFF,/*< audio/video synchronization is off   */
1641  		DRX_AUD_AVSYNC_NTSC,
1642  				   /*< it is an NTSC system                 */
1643  		DRX_AUD_AVSYNC_MONOCHROME,
1644  				   /*< it is a MONOCHROME system            */
1645  		DRX_AUD_AVSYNC_PAL_SECAM
1646  				   /*< it is a PAL/SECAM system             */};
1647  
1648  /*
1649  * \struct struct drx_cfg_aud_prescale * \brief Prescalers
1650  */
1651  struct drx_cfg_aud_prescale {
1652  	u16 fm_deviation;
1653  	s16 nicam_gain;
1654  };
1655  
1656  /*
1657  * \struct struct drx_aud_beep * \brief Beep
1658  */
1659  struct drx_aud_beep {
1660  	s16 volume;	/* dB */
1661  	u16 frequency;	/* Hz */
1662  	bool mute;
1663  };
1664  
1665  /*
1666  * \enum enum drx_aud_btsc_detect * \brief BTSC detetcion mode
1667  */
1668  	enum drx_aud_btsc_detect {
1669  		DRX_BTSC_STEREO,
1670  		DRX_BTSC_MONO_AND_SAP};
1671  
1672  /*
1673  * \struct struct drx_aud_data * \brief Audio data structure
1674  */
1675  struct drx_aud_data {
1676  	/* audio storage */
1677  	bool audio_is_active;
1678  	enum drx_aud_standard audio_standard;
1679  	struct drx_cfg_i2s_output i2sdata;
1680  	struct drx_cfg_aud_volume volume;
1681  	enum drx_cfg_aud_auto_sound auto_sound;
1682  	struct drx_cfg_aud_ass_thres ass_thresholds;
1683  	struct drx_cfg_aud_carriers carriers;
1684  	struct drx_cfg_aud_mixer mixer;
1685  	enum drx_cfg_aud_deviation deviation;
1686  	enum drx_cfg_aud_av_sync av_sync;
1687  	struct drx_cfg_aud_prescale prescale;
1688  	enum drx_aud_fm_deemphasis deemph;
1689  	enum drx_aud_btsc_detect btsc_detect;
1690  	/* rds */
1691  	u16 rds_data_counter;
1692  	bool rds_data_present;
1693  };
1694  
1695  /*
1696  * \enum enum drx_qam_lock_range * \brief QAM lock range mode
1697  */
1698  	enum drx_qam_lock_range {
1699  		DRX_QAM_LOCKRANGE_NORMAL,
1700  		DRX_QAM_LOCKRANGE_EXTENDED};
1701  
1702  /*============================================================================*/
1703  /*============================================================================*/
1704  /*== Data access structures ==================================================*/
1705  /*============================================================================*/
1706  /*============================================================================*/
1707  
1708  /* Address on device */
1709  	typedef u32 dr_xaddr_t, *pdr_xaddr_t;
1710  
1711  /* Protocol specific flags */
1712  	typedef u32 dr_xflags_t, *pdr_xflags_t;
1713  
1714  /* Write block of data to device */
1715  	typedef int(*drx_write_block_func_t) (struct i2c_device_addr *dev_addr,	/* address of I2C device        */
1716  						   u32 addr,	/* address of register/memory   */
1717  						   u16 datasize,	/* size of data in bytes        */
1718  						   u8 *data,	/* data to send                 */
1719  						   u32 flags);
1720  
1721  /* Read block of data from device */
1722  	typedef int(*drx_read_block_func_t) (struct i2c_device_addr *dev_addr,	/* address of I2C device        */
1723  						  u32 addr,	/* address of register/memory   */
1724  						  u16 datasize,	/* size of data in bytes        */
1725  						  u8 *data,	/* receive buffer               */
1726  						  u32 flags);
1727  
1728  /* Write 8-bits value to device */
1729  	typedef int(*drx_write_reg8func_t) (struct i2c_device_addr *dev_addr,	/* address of I2C device        */
1730  						  u32 addr,	/* address of register/memory   */
1731  						  u8 data,	/* data to send                 */
1732  						  u32 flags);
1733  
1734  /* Read 8-bits value to device */
1735  	typedef int(*drx_read_reg8func_t) (struct i2c_device_addr *dev_addr,	/* address of I2C device        */
1736  						 u32 addr,	/* address of register/memory   */
1737  						 u8 *data,	/* receive buffer               */
1738  						 u32 flags);
1739  
1740  /* Read modify write 8-bits value to device */
1741  	typedef int(*drx_read_modify_write_reg8func_t) (struct i2c_device_addr *dev_addr,	/* address of I2C device       */
1742  							    u32 waddr,	/* write address of register   */
1743  							    u32 raddr,	/* read  address of register   */
1744  							    u8 wdata,	/* data to write               */
1745  							    u8 *rdata);	/* data to read                */
1746  
1747  /* Write 16-bits value to device */
1748  	typedef int(*drx_write_reg16func_t) (struct i2c_device_addr *dev_addr,	/* address of I2C device        */
1749  						   u32 addr,	/* address of register/memory   */
1750  						   u16 data,	/* data to send                 */
1751  						   u32 flags);
1752  
1753  /* Read 16-bits value to device */
1754  	typedef int(*drx_read_reg16func_t) (struct i2c_device_addr *dev_addr,	/* address of I2C device        */
1755  						  u32 addr,	/* address of register/memory   */
1756  						  u16 *data,	/* receive buffer               */
1757  						  u32 flags);
1758  
1759  /* Read modify write 16-bits value to device */
1760  	typedef int(*drx_read_modify_write_reg16func_t) (struct i2c_device_addr *dev_addr,	/* address of I2C device       */
1761  							     u32 waddr,	/* write address of register   */
1762  							     u32 raddr,	/* read  address of register   */
1763  							     u16 wdata,	/* data to write               */
1764  							     u16 *rdata);	/* data to read                */
1765  
1766  /* Write 32-bits value to device */
1767  	typedef int(*drx_write_reg32func_t) (struct i2c_device_addr *dev_addr,	/* address of I2C device        */
1768  						   u32 addr,	/* address of register/memory   */
1769  						   u32 data,	/* data to send                 */
1770  						   u32 flags);
1771  
1772  /* Read 32-bits value to device */
1773  	typedef int(*drx_read_reg32func_t) (struct i2c_device_addr *dev_addr,	/* address of I2C device        */
1774  						  u32 addr,	/* address of register/memory   */
1775  						  u32 *data,	/* receive buffer               */
1776  						  u32 flags);
1777  
1778  /* Read modify write 32-bits value to device */
1779  	typedef int(*drx_read_modify_write_reg32func_t) (struct i2c_device_addr *dev_addr,	/* address of I2C device       */
1780  							     u32 waddr,	/* write address of register   */
1781  							     u32 raddr,	/* read  address of register   */
1782  							     u32 wdata,	/* data to write               */
1783  							     u32 *rdata);	/* data to read                */
1784  
1785  /*
1786  * \struct struct drx_access_func * \brief Interface to an access protocol.
1787  */
1788  struct drx_access_func {
1789  	drx_write_block_func_t write_block_func;
1790  	drx_read_block_func_t read_block_func;
1791  	drx_write_reg8func_t write_reg8func;
1792  	drx_read_reg8func_t read_reg8func;
1793  	drx_read_modify_write_reg8func_t read_modify_write_reg8func;
1794  	drx_write_reg16func_t write_reg16func;
1795  	drx_read_reg16func_t read_reg16func;
1796  	drx_read_modify_write_reg16func_t read_modify_write_reg16func;
1797  	drx_write_reg32func_t write_reg32func;
1798  	drx_read_reg32func_t read_reg32func;
1799  	drx_read_modify_write_reg32func_t read_modify_write_reg32func;
1800  };
1801  
1802  /* Register address and data for register dump function */
1803  struct drx_reg_dump {
1804  	u32 address;
1805  	u32 data;
1806  };
1807  
1808  /*============================================================================*/
1809  /*============================================================================*/
1810  /*== Demod instance data structures ==========================================*/
1811  /*============================================================================*/
1812  /*============================================================================*/
1813  
1814  /*
1815  * \struct struct drx_common_attr * \brief Set of common attributes, shared by all DRX devices.
1816  */
1817  	struct drx_common_attr {
1818  		/* Microcode (firmware) attributes */
1819  		char *microcode_file;   /*<  microcode filename           */
1820  		bool verify_microcode;
1821  				   /*< Use microcode verify or not.          */
1822  		struct drx_mc_version_rec mcversion;
1823  				   /*< Version record of microcode from file */
1824  
1825  		/* Clocks and tuner attributes */
1826  		s32 intermediate_freq;
1827  				     /*< IF,if tuner instance not used. (kHz)*/
1828  		s32 sys_clock_freq;
1829  				     /*< Systemclock frequency.  (kHz)       */
1830  		s32 osc_clock_freq;
1831  				     /*< Oscillator clock frequency.  (kHz)  */
1832  		s16 osc_clock_deviation;
1833  				     /*< Oscillator clock deviation.  (ppm)  */
1834  		bool mirror_freq_spect;
1835  				     /*< Mirror IF frequency spectrum or not.*/
1836  
1837  		/* Initial MPEG output attributes */
1838  		struct drx_cfg_mpeg_output mpeg_cfg;
1839  				     /*< MPEG configuration                  */
1840  
1841  		bool is_opened;     /*< if true instance is already opened. */
1842  
1843  		/* Channel scan */
1844  		struct drx_scan_param *scan_param;
1845  				      /*< scan parameters                    */
1846  		u16 scan_freq_plan_index;
1847  				      /*< next index in freq plan            */
1848  		s32 scan_next_frequency;
1849  				      /*< next freq to scan                  */
1850  		bool scan_ready;     /*< scan ready flag                    */
1851  		u32 scan_max_channels;/*< number of channels in freqplan     */
1852  		u32 scan_channels_scanned;
1853  					/*< number of channels scanned       */
1854  		/* Channel scan - inner loop: demod related */
1855  		drx_scan_func_t scan_function;
1856  				      /*< function to check channel          */
1857  		/* Channel scan - inner loop: SYSObj related */
1858  		void *scan_context;    /*< Context Pointer of SYSObj          */
1859  		/* Channel scan - parameters for default DTV scan function in core driver  */
1860  		u16 scan_demod_lock_timeout;
1861  					 /*< millisecs to wait for lock      */
1862  		enum drx_lock_status scan_desired_lock;
1863  				      /*< lock requirement for channel found */
1864  		/* scan_active can be used by SetChannel to decide how to program the tuner,
1865  		   fast or slow (but stable). Usually fast during scan. */
1866  		bool scan_active;    /*< true when scan routines are active */
1867  
1868  		/* Power management */
1869  		enum drx_power_mode current_power_mode;
1870  				      /*< current power management mode      */
1871  
1872  		/* Tuner */
1873  		u8 tuner_port_nr;     /*< nr of I2C port to which tuner is    */
1874  		s32 tuner_min_freq_rf;
1875  				      /*< minimum RF input frequency, in kHz */
1876  		s32 tuner_max_freq_rf;
1877  				      /*< maximum RF input frequency, in kHz */
1878  		bool tuner_rf_agc_pol; /*< if true invert RF AGC polarity     */
1879  		bool tuner_if_agc_pol; /*< if true invert IF AGC polarity     */
1880  		bool tuner_slow_mode; /*< if true invert IF AGC polarity     */
1881  
1882  		struct drx_channel current_channel;
1883  				      /*< current channel parameters         */
1884  		enum drx_standard current_standard;
1885  				      /*< current standard selection         */
1886  		enum drx_standard prev_standard;
1887  				      /*< previous standard selection        */
1888  		enum drx_standard di_cache_standard;
1889  				      /*< standard in DI cache if available  */
1890  		bool use_bootloader; /*< use bootloader in open             */
1891  		u32 capabilities;   /*< capabilities flags                 */
1892  		u32 product_id;      /*< product ID inc. metal fix number   */};
1893  
1894  /*
1895  * Generic functions for DRX devices.
1896  */
1897  
1898  struct drx_demod_instance;
1899  
1900  /*
1901  * \struct struct drx_demod_instance * \brief Top structure of demodulator instance.
1902  */
1903  struct drx_demod_instance {
1904  				/*< data access protocol functions       */
1905  	struct i2c_device_addr *my_i2c_dev_addr;
1906  				/*< i2c address and device identifier    */
1907  	struct drx_common_attr *my_common_attr;
1908  				/*< common DRX attributes                */
1909  	void *my_ext_attr;    /*< device specific attributes           */
1910  	/* generic demodulator data */
1911  
1912  	struct i2c_adapter	*i2c;
1913  	const struct firmware	*firmware;
1914  };
1915  
1916  /*-------------------------------------------------------------------------
1917  MACROS
1918  Conversion from enum values to human readable form.
1919  -------------------------------------------------------------------------*/
1920  
1921  /* standard */
1922  
1923  #define DRX_STR_STANDARD(x) ( \
1924  	(x == DRX_STANDARD_DVBT)  ? "DVB-T"            : \
1925  	(x == DRX_STANDARD_8VSB)  ? "8VSB"             : \
1926  	(x == DRX_STANDARD_NTSC)  ? "NTSC"             : \
1927  	(x == DRX_STANDARD_PAL_SECAM_BG)  ? "PAL/SECAM B/G"    : \
1928  	(x == DRX_STANDARD_PAL_SECAM_DK)  ? "PAL/SECAM D/K"    : \
1929  	(x == DRX_STANDARD_PAL_SECAM_I)  ? "PAL/SECAM I"      : \
1930  	(x == DRX_STANDARD_PAL_SECAM_L)  ? "PAL/SECAM L"      : \
1931  	(x == DRX_STANDARD_PAL_SECAM_LP)  ? "PAL/SECAM LP"     : \
1932  	(x == DRX_STANDARD_ITU_A)  ? "ITU-A"            : \
1933  	(x == DRX_STANDARD_ITU_B)  ? "ITU-B"            : \
1934  	(x == DRX_STANDARD_ITU_C)  ? "ITU-C"            : \
1935  	(x == DRX_STANDARD_ITU_D)  ? "ITU-D"            : \
1936  	(x == DRX_STANDARD_FM)  ? "FM"               : \
1937  	(x == DRX_STANDARD_DTMB)  ? "DTMB"             : \
1938  	(x == DRX_STANDARD_AUTO)  ? "Auto"             : \
1939  	(x == DRX_STANDARD_UNKNOWN)  ? "Unknown"          : \
1940  	"(Invalid)")
1941  
1942  /* channel */
1943  
1944  #define DRX_STR_BANDWIDTH(x) ( \
1945  	(x == DRX_BANDWIDTH_8MHZ)  ?  "8 MHz"            : \
1946  	(x == DRX_BANDWIDTH_7MHZ)  ?  "7 MHz"            : \
1947  	(x == DRX_BANDWIDTH_6MHZ)  ?  "6 MHz"            : \
1948  	(x == DRX_BANDWIDTH_AUTO)  ?  "Auto"             : \
1949  	(x == DRX_BANDWIDTH_UNKNOWN)  ?  "Unknown"          : \
1950  	"(Invalid)")
1951  #define DRX_STR_FFTMODE(x) ( \
1952  	(x == DRX_FFTMODE_2K)  ?  "2k"               : \
1953  	(x == DRX_FFTMODE_4K)  ?  "4k"               : \
1954  	(x == DRX_FFTMODE_8K)  ?  "8k"               : \
1955  	(x == DRX_FFTMODE_AUTO)  ?  "Auto"             : \
1956  	(x == DRX_FFTMODE_UNKNOWN)  ?  "Unknown"          : \
1957  	"(Invalid)")
1958  #define DRX_STR_GUARD(x) ( \
1959  	(x == DRX_GUARD_1DIV32)  ?  "1/32nd"           : \
1960  	(x == DRX_GUARD_1DIV16)  ?  "1/16th"           : \
1961  	(x == DRX_GUARD_1DIV8)  ?  "1/8th"            : \
1962  	(x == DRX_GUARD_1DIV4)  ?  "1/4th"            : \
1963  	(x == DRX_GUARD_AUTO)  ?  "Auto"             : \
1964  	(x == DRX_GUARD_UNKNOWN)  ?  "Unknown"          : \
1965  	"(Invalid)")
1966  #define DRX_STR_CONSTELLATION(x) ( \
1967  	(x == DRX_CONSTELLATION_BPSK)  ?  "BPSK"            : \
1968  	(x == DRX_CONSTELLATION_QPSK)  ?  "QPSK"            : \
1969  	(x == DRX_CONSTELLATION_PSK8)  ?  "PSK8"            : \
1970  	(x == DRX_CONSTELLATION_QAM16)  ?  "QAM16"           : \
1971  	(x == DRX_CONSTELLATION_QAM32)  ?  "QAM32"           : \
1972  	(x == DRX_CONSTELLATION_QAM64)  ?  "QAM64"           : \
1973  	(x == DRX_CONSTELLATION_QAM128)  ?  "QAM128"          : \
1974  	(x == DRX_CONSTELLATION_QAM256)  ?  "QAM256"          : \
1975  	(x == DRX_CONSTELLATION_QAM512)  ?  "QAM512"          : \
1976  	(x == DRX_CONSTELLATION_QAM1024)  ?  "QAM1024"         : \
1977  	(x == DRX_CONSTELLATION_QPSK_NR)  ?  "QPSK_NR"            : \
1978  	(x == DRX_CONSTELLATION_AUTO)  ?  "Auto"            : \
1979  	(x == DRX_CONSTELLATION_UNKNOWN)  ?  "Unknown"         : \
1980  	"(Invalid)")
1981  #define DRX_STR_CODERATE(x) ( \
1982  	(x == DRX_CODERATE_1DIV2)  ?  "1/2nd"           : \
1983  	(x == DRX_CODERATE_2DIV3)  ?  "2/3rd"           : \
1984  	(x == DRX_CODERATE_3DIV4)  ?  "3/4th"           : \
1985  	(x == DRX_CODERATE_5DIV6)  ?  "5/6th"           : \
1986  	(x == DRX_CODERATE_7DIV8)  ?  "7/8th"           : \
1987  	(x == DRX_CODERATE_AUTO)  ?  "Auto"            : \
1988  	(x == DRX_CODERATE_UNKNOWN)  ?  "Unknown"         : \
1989  	"(Invalid)")
1990  #define DRX_STR_HIERARCHY(x) ( \
1991  	(x == DRX_HIERARCHY_NONE)  ?  "None"            : \
1992  	(x == DRX_HIERARCHY_ALPHA1)  ?  "Alpha=1"         : \
1993  	(x == DRX_HIERARCHY_ALPHA2)  ?  "Alpha=2"         : \
1994  	(x == DRX_HIERARCHY_ALPHA4)  ?  "Alpha=4"         : \
1995  	(x == DRX_HIERARCHY_AUTO)  ?  "Auto"            : \
1996  	(x == DRX_HIERARCHY_UNKNOWN)  ?  "Unknown"         : \
1997  	"(Invalid)")
1998  #define DRX_STR_PRIORITY(x) ( \
1999  	(x == DRX_PRIORITY_LOW)  ?  "Low"             : \
2000  	(x == DRX_PRIORITY_HIGH)  ?  "High"            : \
2001  	(x == DRX_PRIORITY_UNKNOWN)  ?  "Unknown"         : \
2002  	"(Invalid)")
2003  #define DRX_STR_MIRROR(x) ( \
2004  	(x == DRX_MIRROR_NO)  ?  "Normal"          : \
2005  	(x == DRX_MIRROR_YES)  ?  "Mirrored"        : \
2006  	(x == DRX_MIRROR_AUTO)  ?  "Auto"            : \
2007  	(x == DRX_MIRROR_UNKNOWN)  ?  "Unknown"         : \
2008  	"(Invalid)")
2009  #define DRX_STR_CLASSIFICATION(x) ( \
2010  	(x == DRX_CLASSIFICATION_GAUSS)  ?  "Gaussion"        : \
2011  	(x == DRX_CLASSIFICATION_HVY_GAUSS)  ?  "Heavy Gaussion"  : \
2012  	(x == DRX_CLASSIFICATION_COCHANNEL)  ?  "Co-channel"      : \
2013  	(x == DRX_CLASSIFICATION_STATIC)  ?  "Static echo"     : \
2014  	(x == DRX_CLASSIFICATION_MOVING)  ?  "Moving echo"     : \
2015  	(x == DRX_CLASSIFICATION_ZERODB)  ?  "Zero dB echo"    : \
2016  	(x == DRX_CLASSIFICATION_UNKNOWN)  ?  "Unknown"         : \
2017  	(x == DRX_CLASSIFICATION_AUTO)  ?  "Auto"            : \
2018  	"(Invalid)")
2019  
2020  #define DRX_STR_INTERLEAVEMODE(x) ( \
2021  	(x == DRX_INTERLEAVEMODE_I128_J1) ? "I128_J1"         : \
2022  	(x == DRX_INTERLEAVEMODE_I128_J1_V2) ? "I128_J1_V2"      : \
2023  	(x == DRX_INTERLEAVEMODE_I128_J2) ? "I128_J2"         : \
2024  	(x == DRX_INTERLEAVEMODE_I64_J2) ? "I64_J2"          : \
2025  	(x == DRX_INTERLEAVEMODE_I128_J3) ? "I128_J3"         : \
2026  	(x == DRX_INTERLEAVEMODE_I32_J4) ? "I32_J4"          : \
2027  	(x == DRX_INTERLEAVEMODE_I128_J4) ? "I128_J4"         : \
2028  	(x == DRX_INTERLEAVEMODE_I16_J8) ? "I16_J8"          : \
2029  	(x == DRX_INTERLEAVEMODE_I128_J5) ? "I128_J5"         : \
2030  	(x == DRX_INTERLEAVEMODE_I8_J16) ? "I8_J16"          : \
2031  	(x == DRX_INTERLEAVEMODE_I128_J6) ? "I128_J6"         : \
2032  	(x == DRX_INTERLEAVEMODE_RESERVED_11) ? "Reserved 11"     : \
2033  	(x == DRX_INTERLEAVEMODE_I128_J7) ? "I128_J7"         : \
2034  	(x == DRX_INTERLEAVEMODE_RESERVED_13) ? "Reserved 13"     : \
2035  	(x == DRX_INTERLEAVEMODE_I128_J8) ? "I128_J8"         : \
2036  	(x == DRX_INTERLEAVEMODE_RESERVED_15) ? "Reserved 15"     : \
2037  	(x == DRX_INTERLEAVEMODE_I12_J17) ? "I12_J17"         : \
2038  	(x == DRX_INTERLEAVEMODE_I5_J4) ? "I5_J4"           : \
2039  	(x == DRX_INTERLEAVEMODE_B52_M240) ? "B52_M240"        : \
2040  	(x == DRX_INTERLEAVEMODE_B52_M720) ? "B52_M720"        : \
2041  	(x == DRX_INTERLEAVEMODE_B52_M48) ? "B52_M48"         : \
2042  	(x == DRX_INTERLEAVEMODE_B52_M0) ? "B52_M0"          : \
2043  	(x == DRX_INTERLEAVEMODE_UNKNOWN) ? "Unknown"         : \
2044  	(x == DRX_INTERLEAVEMODE_AUTO) ? "Auto"            : \
2045  	"(Invalid)")
2046  
2047  #define DRX_STR_LDPC(x) ( \
2048  	(x == DRX_LDPC_0_4) ? "0.4"             : \
2049  	(x == DRX_LDPC_0_6) ? "0.6"             : \
2050  	(x == DRX_LDPC_0_8) ? "0.8"             : \
2051  	(x == DRX_LDPC_AUTO) ? "Auto"            : \
2052  	(x == DRX_LDPC_UNKNOWN) ? "Unknown"         : \
2053  	"(Invalid)")
2054  
2055  #define DRX_STR_CARRIER(x) ( \
2056  	(x == DRX_CARRIER_MULTI) ? "Multi"           : \
2057  	(x == DRX_CARRIER_SINGLE) ? "Single"          : \
2058  	(x == DRX_CARRIER_AUTO) ? "Auto"            : \
2059  	(x == DRX_CARRIER_UNKNOWN) ? "Unknown"         : \
2060  	"(Invalid)")
2061  
2062  #define DRX_STR_FRAMEMODE(x) ( \
2063  	(x == DRX_FRAMEMODE_420)  ? "420"                : \
2064  	(x == DRX_FRAMEMODE_595)  ? "595"                : \
2065  	(x == DRX_FRAMEMODE_945)  ? "945"                : \
2066  	(x == DRX_FRAMEMODE_420_FIXED_PN)  ? "420 with fixed PN"  : \
2067  	(x == DRX_FRAMEMODE_945_FIXED_PN)  ? "945 with fixed PN"  : \
2068  	(x == DRX_FRAMEMODE_AUTO)  ? "Auto"               : \
2069  	(x == DRX_FRAMEMODE_UNKNOWN)  ? "Unknown"            : \
2070  	"(Invalid)")
2071  
2072  #define DRX_STR_PILOT(x) ( \
2073  	(x == DRX_PILOT_ON) ?   "On"              : \
2074  	(x == DRX_PILOT_OFF) ?   "Off"             : \
2075  	(x == DRX_PILOT_AUTO) ?   "Auto"            : \
2076  	(x == DRX_PILOT_UNKNOWN) ?   "Unknown"         : \
2077  	"(Invalid)")
2078  /* TPS */
2079  
2080  #define DRX_STR_TPS_FRAME(x)  ( \
2081  	(x == DRX_TPS_FRAME1)  ?  "Frame1"          : \
2082  	(x == DRX_TPS_FRAME2)  ?  "Frame2"          : \
2083  	(x == DRX_TPS_FRAME3)  ?  "Frame3"          : \
2084  	(x == DRX_TPS_FRAME4)  ?  "Frame4"          : \
2085  	(x == DRX_TPS_FRAME_UNKNOWN)  ?  "Unknown"         : \
2086  	"(Invalid)")
2087  
2088  /* lock status */
2089  
2090  #define DRX_STR_LOCKSTATUS(x) ( \
2091  	(x == DRX_NEVER_LOCK)  ?  "Never"           : \
2092  	(x == DRX_NOT_LOCKED)  ?  "No"              : \
2093  	(x == DRX_LOCKED)  ?  "Locked"          : \
2094  	(x == DRX_LOCK_STATE_1)  ?  "Lock state 1"    : \
2095  	(x == DRX_LOCK_STATE_2)  ?  "Lock state 2"    : \
2096  	(x == DRX_LOCK_STATE_3)  ?  "Lock state 3"    : \
2097  	(x == DRX_LOCK_STATE_4)  ?  "Lock state 4"    : \
2098  	(x == DRX_LOCK_STATE_5)  ?  "Lock state 5"    : \
2099  	(x == DRX_LOCK_STATE_6)  ?  "Lock state 6"    : \
2100  	(x == DRX_LOCK_STATE_7)  ?  "Lock state 7"    : \
2101  	(x == DRX_LOCK_STATE_8)  ?  "Lock state 8"    : \
2102  	(x == DRX_LOCK_STATE_9)  ?  "Lock state 9"    : \
2103  	"(Invalid)")
2104  
2105  /* version information , modules */
2106  #define DRX_STR_MODULE(x) ( \
2107  	(x == DRX_MODULE_DEVICE)  ?  "Device"                : \
2108  	(x == DRX_MODULE_MICROCODE)  ?  "Microcode"             : \
2109  	(x == DRX_MODULE_DRIVERCORE)  ?  "CoreDriver"            : \
2110  	(x == DRX_MODULE_DEVICEDRIVER)  ?  "DeviceDriver"          : \
2111  	(x == DRX_MODULE_BSP_I2C)  ?  "BSP I2C"               : \
2112  	(x == DRX_MODULE_BSP_TUNER)  ?  "BSP Tuner"             : \
2113  	(x == DRX_MODULE_BSP_HOST)  ?  "BSP Host"              : \
2114  	(x == DRX_MODULE_DAP)  ?  "Data Access Protocol"  : \
2115  	(x == DRX_MODULE_UNKNOWN)  ?  "Unknown"               : \
2116  	"(Invalid)")
2117  
2118  #define DRX_STR_POWER_MODE(x) ( \
2119  	(x == DRX_POWER_UP)  ?  "DRX_POWER_UP    "  : \
2120  	(x == DRX_POWER_MODE_1)  ?  "DRX_POWER_MODE_1"  : \
2121  	(x == DRX_POWER_MODE_2)  ?  "DRX_POWER_MODE_2"  : \
2122  	(x == DRX_POWER_MODE_3)  ?  "DRX_POWER_MODE_3"  : \
2123  	(x == DRX_POWER_MODE_4)  ?  "DRX_POWER_MODE_4"  : \
2124  	(x == DRX_POWER_MODE_5)  ?  "DRX_POWER_MODE_5"  : \
2125  	(x == DRX_POWER_MODE_6)  ?  "DRX_POWER_MODE_6"  : \
2126  	(x == DRX_POWER_MODE_7)  ?  "DRX_POWER_MODE_7"  : \
2127  	(x == DRX_POWER_MODE_8)  ?  "DRX_POWER_MODE_8"  : \
2128  	(x == DRX_POWER_MODE_9)  ?  "DRX_POWER_MODE_9"  : \
2129  	(x == DRX_POWER_MODE_10)  ?  "DRX_POWER_MODE_10" : \
2130  	(x == DRX_POWER_MODE_11)  ?  "DRX_POWER_MODE_11" : \
2131  	(x == DRX_POWER_MODE_12)  ?  "DRX_POWER_MODE_12" : \
2132  	(x == DRX_POWER_MODE_13)  ?  "DRX_POWER_MODE_13" : \
2133  	(x == DRX_POWER_MODE_14)  ?  "DRX_POWER_MODE_14" : \
2134  	(x == DRX_POWER_MODE_15)  ?  "DRX_POWER_MODE_15" : \
2135  	(x == DRX_POWER_MODE_16)  ?  "DRX_POWER_MODE_16" : \
2136  	(x == DRX_POWER_DOWN)  ?  "DRX_POWER_DOWN  " : \
2137  	"(Invalid)")
2138  
2139  #define DRX_STR_OOB_STANDARD(x) ( \
2140  	(x == DRX_OOB_MODE_A)  ?  "ANSI 55-1  " : \
2141  	(x == DRX_OOB_MODE_B_GRADE_A)  ?  "ANSI 55-2 A" : \
2142  	(x == DRX_OOB_MODE_B_GRADE_B)  ?  "ANSI 55-2 B" : \
2143  	"(Invalid)")
2144  
2145  #define DRX_STR_AUD_STANDARD(x) ( \
2146  	(x == DRX_AUD_STANDARD_BTSC)  ? "BTSC"                     : \
2147  	(x == DRX_AUD_STANDARD_A2)  ? "A2"                       : \
2148  	(x == DRX_AUD_STANDARD_EIAJ)  ? "EIAJ"                     : \
2149  	(x == DRX_AUD_STANDARD_FM_STEREO)  ? "FM Stereo"                : \
2150  	(x == DRX_AUD_STANDARD_AUTO)  ? "Auto"                     : \
2151  	(x == DRX_AUD_STANDARD_M_MONO)  ? "M-Standard Mono"          : \
2152  	(x == DRX_AUD_STANDARD_D_K_MONO)  ? "D/K Mono FM"              : \
2153  	(x == DRX_AUD_STANDARD_BG_FM)  ? "B/G-Dual Carrier FM (A2)" : \
2154  	(x == DRX_AUD_STANDARD_D_K1)  ? "D/K1-Dual Carrier FM"     : \
2155  	(x == DRX_AUD_STANDARD_D_K2)  ? "D/K2-Dual Carrier FM"     : \
2156  	(x == DRX_AUD_STANDARD_D_K3)  ? "D/K3-Dual Carrier FM"     : \
2157  	(x == DRX_AUD_STANDARD_BG_NICAM_FM)  ? "B/G-NICAM-FM"             : \
2158  	(x == DRX_AUD_STANDARD_L_NICAM_AM)  ? "L-NICAM-AM"               : \
2159  	(x == DRX_AUD_STANDARD_I_NICAM_FM)  ? "I-NICAM-FM"               : \
2160  	(x == DRX_AUD_STANDARD_D_K_NICAM_FM)  ? "D/K-NICAM-FM"             : \
2161  	(x == DRX_AUD_STANDARD_UNKNOWN)  ? "Unknown"                  : \
2162  	"(Invalid)")
2163  #define DRX_STR_AUD_STEREO(x) ( \
2164  	(x == true)  ? "Stereo"           : \
2165  	(x == false)  ? "Mono"             : \
2166  	"(Invalid)")
2167  
2168  #define DRX_STR_AUD_SAP(x) ( \
2169  	(x == true)  ? "Present"          : \
2170  	(x == false)  ? "Not present"      : \
2171  	"(Invalid)")
2172  
2173  #define DRX_STR_AUD_CARRIER(x) ( \
2174  	(x == true)  ? "Present"          : \
2175  	(x == false)  ? "Not present"      : \
2176  	"(Invalid)")
2177  
2178  #define DRX_STR_AUD_RDS(x) ( \
2179  	(x == true)  ? "Available"        : \
2180  	(x == false)  ? "Not Available"    : \
2181  	"(Invalid)")
2182  
2183  #define DRX_STR_AUD_NICAM_STATUS(x) ( \
2184  	(x == DRX_AUD_NICAM_DETECTED)  ? "Detected"         : \
2185  	(x == DRX_AUD_NICAM_NOT_DETECTED)  ? "Not detected"     : \
2186  	(x == DRX_AUD_NICAM_BAD)  ? "Bad"              : \
2187  	"(Invalid)")
2188  
2189  #define DRX_STR_RDS_VALID(x) ( \
2190  	(x == true)  ? "Valid"            : \
2191  	(x == false)  ? "Not Valid"        : \
2192  	"(Invalid)")
2193  
2194  /*-------------------------------------------------------------------------
2195  Access macros
2196  -------------------------------------------------------------------------*/
2197  
2198  /*
2199  * \brief Create a compilable reference to the microcode attribute
2200  * \param d pointer to demod instance
2201  *
2202  * Used as main reference to an attribute field.
2203  * Used by both macro implementation and function implementation.
2204  * These macros are defined to avoid duplication of code in macro and function
2205  * definitions that handle access of demod common or extended attributes.
2206  *
2207  */
2208  
2209  #define DRX_ATTR_MCRECORD(d)        ((d)->my_common_attr->mcversion)
2210  #define DRX_ATTR_MIRRORFREQSPECT(d) ((d)->my_common_attr->mirror_freq_spect)
2211  #define DRX_ATTR_CURRENTPOWERMODE(d)((d)->my_common_attr->current_power_mode)
2212  #define DRX_ATTR_ISOPENED(d)        ((d)->my_common_attr->is_opened)
2213  #define DRX_ATTR_USEBOOTLOADER(d)   ((d)->my_common_attr->use_bootloader)
2214  #define DRX_ATTR_CURRENTSTANDARD(d) ((d)->my_common_attr->current_standard)
2215  #define DRX_ATTR_PREVSTANDARD(d)    ((d)->my_common_attr->prev_standard)
2216  #define DRX_ATTR_CACHESTANDARD(d)   ((d)->my_common_attr->di_cache_standard)
2217  #define DRX_ATTR_CURRENTCHANNEL(d)  ((d)->my_common_attr->current_channel)
2218  #define DRX_ATTR_MICROCODE(d)       ((d)->my_common_attr->microcode)
2219  #define DRX_ATTR_VERIFYMICROCODE(d) ((d)->my_common_attr->verify_microcode)
2220  #define DRX_ATTR_CAPABILITIES(d)    ((d)->my_common_attr->capabilities)
2221  #define DRX_ATTR_PRODUCTID(d)       ((d)->my_common_attr->product_id)
2222  #define DRX_ATTR_INTERMEDIATEFREQ(d) ((d)->my_common_attr->intermediate_freq)
2223  #define DRX_ATTR_SYSCLOCKFREQ(d)     ((d)->my_common_attr->sys_clock_freq)
2224  #define DRX_ATTR_TUNERRFAGCPOL(d)   ((d)->my_common_attr->tuner_rf_agc_pol)
2225  #define DRX_ATTR_TUNERIFAGCPOL(d)    ((d)->my_common_attr->tuner_if_agc_pol)
2226  #define DRX_ATTR_TUNERSLOWMODE(d)    ((d)->my_common_attr->tuner_slow_mode)
2227  #define DRX_ATTR_TUNERSPORTNR(d)     ((d)->my_common_attr->tuner_port_nr)
2228  #define DRX_ATTR_I2CADDR(d)         ((d)->my_i2c_dev_addr->i2c_addr)
2229  #define DRX_ATTR_I2CDEVID(d)        ((d)->my_i2c_dev_addr->i2c_dev_id)
2230  #define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD)
2231  
2232  /*************************/
2233  
2234  /* Macros with device-specific handling are converted to CFG functions */
2235  
2236  #define DRX_ACCESSMACRO_SET(demod, value, cfg_name, data_type)             \
2237  	do {                                                               \
2238  		struct drx_cfg config;                                     \
2239  		data_type cfg_data;                                        \
2240  		config.cfg_type = cfg_name;                                \
2241  		config.cfg_data = &cfg_data;                               \
2242  		cfg_data = value;                                          \
2243  		drx_ctrl(demod, DRX_CTRL_SET_CFG, &config);                \
2244  	} while (0)
2245  
2246  #define DRX_ACCESSMACRO_GET(demod, value, cfg_name, data_type, error_value) \
2247  	do {                                                                \
2248  		int cfg_status;                                             \
2249  		struct drx_cfg config;                                      \
2250  		data_type    cfg_data;                                      \
2251  		config.cfg_type = cfg_name;                                 \
2252  		config.cfg_data = &cfg_data;                                \
2253  		cfg_status = drx_ctrl(demod, DRX_CTRL_GET_CFG, &config);    \
2254  		if (cfg_status == 0) {                                      \
2255  			value = cfg_data;                                   \
2256  		} else {                                                    \
2257  			value = (data_type)error_value;                     \
2258  		}                                                           \
2259  	} while (0)
2260  
2261  /* Configuration functions for usage by Access (XS) Macros */
2262  
2263  #ifndef DRX_XS_CFG_BASE
2264  #define DRX_XS_CFG_BASE (500)
2265  #endif
2266  
2267  #define DRX_XS_CFG_PRESET          (DRX_XS_CFG_BASE + 0)
2268  #define DRX_XS_CFG_AUD_BTSC_DETECT (DRX_XS_CFG_BASE + 1)
2269  #define DRX_XS_CFG_QAM_LOCKRANGE   (DRX_XS_CFG_BASE + 2)
2270  
2271  /* Access Macros with device-specific handling */
2272  
2273  #define DRX_SET_PRESET(d, x) \
2274  	DRX_ACCESSMACRO_SET((d), (x), DRX_XS_CFG_PRESET, char*)
2275  #define DRX_GET_PRESET(d, x) \
2276  	DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR")
2277  
2278  #define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET((d), (x), \
2279  	 DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect)
2280  #define DRX_GET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_GET((d), (x), \
2281  	 DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect, DRX_UNKNOWN)
2282  
2283  #define DRX_SET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_SET((d), (x), \
2284  	 DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range)
2285  #define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET((d), (x), \
2286  	 DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range, DRX_UNKNOWN)
2287  
2288  /*
2289  * \brief Macro to check if std is an ATV standard
2290  * \retval true std is an ATV standard
2291  * \retval false std is an ATV standard
2292  */
2293  #define DRX_ISATVSTD(std) (((std) == DRX_STANDARD_PAL_SECAM_BG) || \
2294  			      ((std) == DRX_STANDARD_PAL_SECAM_DK) || \
2295  			      ((std) == DRX_STANDARD_PAL_SECAM_I) || \
2296  			      ((std) == DRX_STANDARD_PAL_SECAM_L) || \
2297  			      ((std) == DRX_STANDARD_PAL_SECAM_LP) || \
2298  			      ((std) == DRX_STANDARD_NTSC) || \
2299  			      ((std) == DRX_STANDARD_FM))
2300  
2301  /*
2302  * \brief Macro to check if std is an QAM standard
2303  * \retval true std is an QAM standards
2304  * \retval false std is an QAM standards
2305  */
2306  #define DRX_ISQAMSTD(std) (((std) == DRX_STANDARD_ITU_A) || \
2307  			      ((std) == DRX_STANDARD_ITU_B) || \
2308  			      ((std) == DRX_STANDARD_ITU_C) || \
2309  			      ((std) == DRX_STANDARD_ITU_D))
2310  
2311  /*
2312  * \brief Macro to check if std is VSB standard
2313  * \retval true std is VSB standard
2314  * \retval false std is not VSB standard
2315  */
2316  #define DRX_ISVSBSTD(std) ((std) == DRX_STANDARD_8VSB)
2317  
2318  /*
2319  * \brief Macro to check if std is DVBT standard
2320  * \retval true std is DVBT standard
2321  * \retval false std is not DVBT standard
2322  */
2323  #define DRX_ISDVBTSTD(std) ((std) == DRX_STANDARD_DVBT)
2324  
2325  /*-------------------------------------------------------------------------
2326  THE END
2327  -------------------------------------------------------------------------*/
2328  #endif				/* __DRXDRIVER_H__ */
2329