1 /*
2 *
3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27 #include <drm/i915_drm.h>
28
29 #include "display/intel_fbc.h"
30 #include "display/intel_gmbus.h"
31
32 #include "i915_drv.h"
33 #include "i915_reg.h"
34 #include "i915_suspend.h"
35
i915_save_display(struct drm_i915_private * dev_priv)36 static void i915_save_display(struct drm_i915_private *dev_priv)
37 {
38 /* Display arbitration control */
39 if (INTEL_GEN(dev_priv) <= 4)
40 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
41
42 /* save FBC interval */
43 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
44 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
45 }
46
i915_restore_display(struct drm_i915_private * dev_priv)47 static void i915_restore_display(struct drm_i915_private *dev_priv)
48 {
49 /* Display arbitration */
50 if (INTEL_GEN(dev_priv) <= 4)
51 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
52
53 /* only restore FBC info on the platform that supports FBC*/
54 intel_fbc_global_disable(dev_priv);
55
56 /* restore FBC interval */
57 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
58 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
59
60 i915_redisable_vga(dev_priv);
61 }
62
i915_save_state(struct drm_i915_private * dev_priv)63 int i915_save_state(struct drm_i915_private *dev_priv)
64 {
65 struct pci_dev *pdev = dev_priv->drm.pdev;
66 int i;
67
68 mutex_lock(&dev_priv->drm.struct_mutex);
69
70 i915_save_display(dev_priv);
71
72 if (IS_GEN(dev_priv, 4))
73 pci_read_config_word(pdev, GCDGMBUS,
74 &dev_priv->regfile.saveGCDGMBUS);
75
76 /* Cache mode state */
77 if (INTEL_GEN(dev_priv) < 7)
78 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
79
80 /* Memory Arbitration state */
81 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
82
83 /* Scratch space */
84 if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
85 for (i = 0; i < 7; i++) {
86 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
87 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
88 }
89 for (i = 0; i < 3; i++)
90 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
91 } else if (IS_GEN(dev_priv, 2)) {
92 for (i = 0; i < 7; i++)
93 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
94 } else if (HAS_GMCH(dev_priv)) {
95 for (i = 0; i < 16; i++) {
96 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
97 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
98 }
99 for (i = 0; i < 3; i++)
100 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
101 }
102
103 mutex_unlock(&dev_priv->drm.struct_mutex);
104
105 return 0;
106 }
107
i915_restore_state(struct drm_i915_private * dev_priv)108 int i915_restore_state(struct drm_i915_private *dev_priv)
109 {
110 struct pci_dev *pdev = dev_priv->drm.pdev;
111 int i;
112
113 mutex_lock(&dev_priv->drm.struct_mutex);
114
115 if (IS_GEN(dev_priv, 4))
116 pci_write_config_word(pdev, GCDGMBUS,
117 dev_priv->regfile.saveGCDGMBUS);
118 i915_restore_display(dev_priv);
119
120 /* Cache mode state */
121 if (INTEL_GEN(dev_priv) < 7)
122 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
123 0xffff0000);
124
125 /* Memory arbitration state */
126 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
127
128 /* Scratch space */
129 if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
130 for (i = 0; i < 7; i++) {
131 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
132 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
133 }
134 for (i = 0; i < 3; i++)
135 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
136 } else if (IS_GEN(dev_priv, 2)) {
137 for (i = 0; i < 7; i++)
138 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
139 } else if (HAS_GMCH(dev_priv)) {
140 for (i = 0; i < 16; i++) {
141 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
142 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
143 }
144 for (i = 0; i < 3; i++)
145 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
146 }
147
148 mutex_unlock(&dev_priv->drm.struct_mutex);
149
150 intel_gmbus_reset(dev_priv);
151
152 return 0;
153 }
154
