1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25 #include <linux/delay.h>
26
27 #include "dm_services.h"
28 #include "dm_helpers.h"
29 #include "core_types.h"
30 #include "resource.h"
31 #include "dcn20/dcn20_resource.h"
32 #include "dce110/dce110_hw_sequencer.h"
33 #include "dcn10/dcn10_hw_sequencer.h"
34 #include "dcn20_hwseq.h"
35 #include "dce/dce_hwseq.h"
36 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
37 #include "dcn20/dcn20_dsc.h"
38 #endif
39 #include "abm.h"
40 #include "clk_mgr.h"
41 #include "dmcu.h"
42 #include "hubp.h"
43 #include "timing_generator.h"
44 #include "opp.h"
45 #include "ipp.h"
46 #include "mpc.h"
47 #include "mcif_wb.h"
48 #include "reg_helper.h"
49 #include "dcn10/dcn10_cm_common.h"
50 #include "dcn10/dcn10_hubbub.h"
51 #include "dcn10/dcn10_optc.h"
52 #include "dc_link_dp.h"
53 #include "vm_helper.h"
54 #include "dccg.h"
55
56 #define DC_LOGGER_INIT(logger)
57
58 #define CTX \
59 hws->ctx
60 #define REG(reg)\
61 hws->regs->reg
62
63 #undef FN
64 #define FN(reg_name, field_name) \
65 hws->shifts->field_name, hws->masks->field_name
66
dcn20_enable_power_gating_plane(struct dce_hwseq * hws,bool enable)67 static void dcn20_enable_power_gating_plane(
68 struct dce_hwseq *hws,
69 bool enable)
70 {
71 bool force_on = 1; /* disable power gating */
72
73 if (enable)
74 force_on = 0;
75
76 /* DCHUBP0/1/2/3/4/5 */
77 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
78 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
79 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
80 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
81 if (REG(DOMAIN8_PG_CONFIG))
82 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
83 if (REG(DOMAIN10_PG_CONFIG))
84 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
85
86 /* DPP0/1/2/3/4/5 */
87 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
88 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
89 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
90 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
91 if (REG(DOMAIN9_PG_CONFIG))
92 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
93 if (REG(DOMAIN11_PG_CONFIG))
94 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
95
96 /* DCS0/1/2/3/4/5 */
97 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
98 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
99 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
100 if (REG(DOMAIN19_PG_CONFIG))
101 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
102 if (REG(DOMAIN20_PG_CONFIG))
103 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
104 if (REG(DOMAIN21_PG_CONFIG))
105 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
106 }
107
dcn20_dccg_init(struct dce_hwseq * hws)108 void dcn20_dccg_init(struct dce_hwseq *hws)
109 {
110 /*
111 * set MICROSECOND_TIME_BASE_DIV
112 * 100Mhz refclk -> 0x120264
113 * 27Mhz refclk -> 0x12021b
114 * 48Mhz refclk -> 0x120230
115 *
116 */
117 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
118
119 /*
120 * set MILLISECOND_TIME_BASE_DIV
121 * 100Mhz refclk -> 0x1186a0
122 * 27Mhz refclk -> 0x106978
123 * 48Mhz refclk -> 0x10bb80
124 *
125 */
126 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
127
128 /* This value is dependent on the hardware pipeline delay so set once per SOC */
129 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
130 }
dcn20_display_init(struct dc * dc)131 void dcn20_display_init(struct dc *dc)
132 {
133 struct dce_hwseq *hws = dc->hwseq;
134
135 /* RBBMIF
136 * disable RBBMIF timeout detection for all clients
137 * Ensure RBBMIF does not drop register accesses due to the per-client timeout
138 */
139 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
140 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
141
142 /* DCCG */
143 dcn20_dccg_init(hws);
144
145 REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 0);
146
147 /* DCHUB/MMHUBBUB
148 * set global timer refclk divider
149 * 100Mhz refclk -> 2
150 * 27Mhz refclk -> 1
151 * 48Mhz refclk -> 1
152 */
153 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
154 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
155 REG_WRITE(REFCLK_CNTL, 0);
156
157 /* OPTC
158 * OTG_CONTROL.OTG_DISABLE_POINT_CNTL = 0x3; will be set during optc2_enable_crtc
159 */
160
161 /* AZ
162 * default value is 0x64 for 100Mhz ref clock, if the ref clock is 100Mhz, no need to program this regiser,
163 * if not, it should be programmed according to the ref clock
164 */
165 REG_UPDATE(AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, 0x64);
166 /* Enable controller clock gating */
167 REG_WRITE(AZALIA_CONTROLLER_CLOCK_GATING, 0x1);
168 }
169
dcn20_disable_vga(struct dce_hwseq * hws)170 void dcn20_disable_vga(
171 struct dce_hwseq *hws)
172 {
173 REG_WRITE(D1VGA_CONTROL, 0);
174 REG_WRITE(D2VGA_CONTROL, 0);
175 REG_WRITE(D3VGA_CONTROL, 0);
176 REG_WRITE(D4VGA_CONTROL, 0);
177 REG_WRITE(D5VGA_CONTROL, 0);
178 REG_WRITE(D6VGA_CONTROL, 0);
179 }
180
dcn20_program_tripleBuffer(const struct dc * dc,struct pipe_ctx * pipe_ctx,bool enableTripleBuffer)181 void dcn20_program_tripleBuffer(
182 const struct dc *dc,
183 struct pipe_ctx *pipe_ctx,
184 bool enableTripleBuffer)
185 {
186 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
187 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
188 pipe_ctx->plane_res.hubp,
189 enableTripleBuffer);
190 }
191 }
192
193 /* Blank pixel data during initialization */
dcn20_init_blank(struct dc * dc,struct timing_generator * tg)194 void dcn20_init_blank(
195 struct dc *dc,
196 struct timing_generator *tg)
197 {
198 enum dc_color_space color_space;
199 struct tg_color black_color = {0};
200 struct output_pixel_processor *opp = NULL;
201 struct output_pixel_processor *bottom_opp = NULL;
202 uint32_t num_opps, opp_id_src0, opp_id_src1;
203 uint32_t otg_active_width, otg_active_height;
204
205 /* program opp dpg blank color */
206 color_space = COLOR_SPACE_SRGB;
207 color_space_to_black_color(dc, color_space, &black_color);
208
209 /* get the OTG active size */
210 tg->funcs->get_otg_active_size(tg,
211 &otg_active_width,
212 &otg_active_height);
213
214 /* get the OPTC source */
215 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
216 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
217 opp = dc->res_pool->opps[opp_id_src0];
218
219 if (num_opps == 2) {
220 otg_active_width = otg_active_width / 2;
221 ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp);
222 bottom_opp = dc->res_pool->opps[opp_id_src1];
223 }
224
225 opp->funcs->opp_set_disp_pattern_generator(
226 opp,
227 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
228 COLOR_DEPTH_UNDEFINED,
229 &black_color,
230 otg_active_width,
231 otg_active_height);
232
233 if (num_opps == 2) {
234 bottom_opp->funcs->opp_set_disp_pattern_generator(
235 bottom_opp,
236 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
237 COLOR_DEPTH_UNDEFINED,
238 &black_color,
239 otg_active_width,
240 otg_active_height);
241 }
242
243 dcn20_hwss_wait_for_blank_complete(opp);
244 }
245
246 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
dcn20_dsc_pg_control(struct dce_hwseq * hws,unsigned int dsc_inst,bool power_on)247 static void dcn20_dsc_pg_control(
248 struct dce_hwseq *hws,
249 unsigned int dsc_inst,
250 bool power_on)
251 {
252 uint32_t power_gate = power_on ? 0 : 1;
253 uint32_t pwr_status = power_on ? 0 : 2;
254 uint32_t org_ip_request_cntl = 0;
255
256 if (hws->ctx->dc->debug.disable_dsc_power_gate)
257 return;
258
259 if (REG(DOMAIN16_PG_CONFIG) == 0)
260 return;
261
262 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
263 if (org_ip_request_cntl == 0)
264 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
265
266 switch (dsc_inst) {
267 case 0: /* DSC0 */
268 REG_UPDATE(DOMAIN16_PG_CONFIG,
269 DOMAIN16_POWER_GATE, power_gate);
270
271 REG_WAIT(DOMAIN16_PG_STATUS,
272 DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
273 1, 1000);
274 break;
275 case 1: /* DSC1 */
276 REG_UPDATE(DOMAIN17_PG_CONFIG,
277 DOMAIN17_POWER_GATE, power_gate);
278
279 REG_WAIT(DOMAIN17_PG_STATUS,
280 DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
281 1, 1000);
282 break;
283 case 2: /* DSC2 */
284 REG_UPDATE(DOMAIN18_PG_CONFIG,
285 DOMAIN18_POWER_GATE, power_gate);
286
287 REG_WAIT(DOMAIN18_PG_STATUS,
288 DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
289 1, 1000);
290 break;
291 case 3: /* DSC3 */
292 REG_UPDATE(DOMAIN19_PG_CONFIG,
293 DOMAIN19_POWER_GATE, power_gate);
294
295 REG_WAIT(DOMAIN19_PG_STATUS,
296 DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
297 1, 1000);
298 break;
299 case 4: /* DSC4 */
300 REG_UPDATE(DOMAIN20_PG_CONFIG,
301 DOMAIN20_POWER_GATE, power_gate);
302
303 REG_WAIT(DOMAIN20_PG_STATUS,
304 DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
305 1, 1000);
306 break;
307 case 5: /* DSC5 */
308 REG_UPDATE(DOMAIN21_PG_CONFIG,
309 DOMAIN21_POWER_GATE, power_gate);
310
311 REG_WAIT(DOMAIN21_PG_STATUS,
312 DOMAIN21_PGFSM_PWR_STATUS, pwr_status,
313 1, 1000);
314 break;
315 default:
316 BREAK_TO_DEBUGGER();
317 break;
318 }
319
320 if (org_ip_request_cntl == 0)
321 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
322 }
323 #endif
324
dcn20_dpp_pg_control(struct dce_hwseq * hws,unsigned int dpp_inst,bool power_on)325 static void dcn20_dpp_pg_control(
326 struct dce_hwseq *hws,
327 unsigned int dpp_inst,
328 bool power_on)
329 {
330 uint32_t power_gate = power_on ? 0 : 1;
331 uint32_t pwr_status = power_on ? 0 : 2;
332
333 if (hws->ctx->dc->debug.disable_dpp_power_gate)
334 return;
335 if (REG(DOMAIN1_PG_CONFIG) == 0)
336 return;
337
338 switch (dpp_inst) {
339 case 0: /* DPP0 */
340 REG_UPDATE(DOMAIN1_PG_CONFIG,
341 DOMAIN1_POWER_GATE, power_gate);
342
343 REG_WAIT(DOMAIN1_PG_STATUS,
344 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
345 1, 1000);
346 break;
347 case 1: /* DPP1 */
348 REG_UPDATE(DOMAIN3_PG_CONFIG,
349 DOMAIN3_POWER_GATE, power_gate);
350
351 REG_WAIT(DOMAIN3_PG_STATUS,
352 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
353 1, 1000);
354 break;
355 case 2: /* DPP2 */
356 REG_UPDATE(DOMAIN5_PG_CONFIG,
357 DOMAIN5_POWER_GATE, power_gate);
358
359 REG_WAIT(DOMAIN5_PG_STATUS,
360 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
361 1, 1000);
362 break;
363 case 3: /* DPP3 */
364 REG_UPDATE(DOMAIN7_PG_CONFIG,
365 DOMAIN7_POWER_GATE, power_gate);
366
367 REG_WAIT(DOMAIN7_PG_STATUS,
368 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
369 1, 1000);
370 break;
371 case 4: /* DPP4 */
372 REG_UPDATE(DOMAIN9_PG_CONFIG,
373 DOMAIN9_POWER_GATE, power_gate);
374
375 REG_WAIT(DOMAIN9_PG_STATUS,
376 DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
377 1, 1000);
378 break;
379 case 5: /* DPP5 */
380 /*
381 * Do not power gate DPP5, should be left at HW default, power on permanently.
382 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
383 * reset.
384 * REG_UPDATE(DOMAIN11_PG_CONFIG,
385 * DOMAIN11_POWER_GATE, power_gate);
386 *
387 * REG_WAIT(DOMAIN11_PG_STATUS,
388 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status,
389 * 1, 1000);
390 */
391 break;
392 default:
393 BREAK_TO_DEBUGGER();
394 break;
395 }
396 }
397
398
dcn20_hubp_pg_control(struct dce_hwseq * hws,unsigned int hubp_inst,bool power_on)399 static void dcn20_hubp_pg_control(
400 struct dce_hwseq *hws,
401 unsigned int hubp_inst,
402 bool power_on)
403 {
404 uint32_t power_gate = power_on ? 0 : 1;
405 uint32_t pwr_status = power_on ? 0 : 2;
406
407 if (hws->ctx->dc->debug.disable_hubp_power_gate)
408 return;
409 if (REG(DOMAIN0_PG_CONFIG) == 0)
410 return;
411
412 switch (hubp_inst) {
413 case 0: /* DCHUBP0 */
414 REG_UPDATE(DOMAIN0_PG_CONFIG,
415 DOMAIN0_POWER_GATE, power_gate);
416
417 REG_WAIT(DOMAIN0_PG_STATUS,
418 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
419 1, 1000);
420 break;
421 case 1: /* DCHUBP1 */
422 REG_UPDATE(DOMAIN2_PG_CONFIG,
423 DOMAIN2_POWER_GATE, power_gate);
424
425 REG_WAIT(DOMAIN2_PG_STATUS,
426 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
427 1, 1000);
428 break;
429 case 2: /* DCHUBP2 */
430 REG_UPDATE(DOMAIN4_PG_CONFIG,
431 DOMAIN4_POWER_GATE, power_gate);
432
433 REG_WAIT(DOMAIN4_PG_STATUS,
434 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
435 1, 1000);
436 break;
437 case 3: /* DCHUBP3 */
438 REG_UPDATE(DOMAIN6_PG_CONFIG,
439 DOMAIN6_POWER_GATE, power_gate);
440
441 REG_WAIT(DOMAIN6_PG_STATUS,
442 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
443 1, 1000);
444 break;
445 case 4: /* DCHUBP4 */
446 REG_UPDATE(DOMAIN8_PG_CONFIG,
447 DOMAIN8_POWER_GATE, power_gate);
448
449 REG_WAIT(DOMAIN8_PG_STATUS,
450 DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
451 1, 1000);
452 break;
453 case 5: /* DCHUBP5 */
454 /*
455 * Do not power gate DCHUB5, should be left at HW default, power on permanently.
456 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
457 * reset.
458 * REG_UPDATE(DOMAIN10_PG_CONFIG,
459 * DOMAIN10_POWER_GATE, power_gate);
460 *
461 * REG_WAIT(DOMAIN10_PG_STATUS,
462 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status,
463 * 1, 1000);
464 */
465 break;
466 default:
467 BREAK_TO_DEBUGGER();
468 break;
469 }
470 }
471
472
473 /* disable HW used by plane.
474 * note: cannot disable until disconnect is complete
475 */
dcn20_plane_atomic_disable(struct dc * dc,struct pipe_ctx * pipe_ctx)476 static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
477 {
478 struct hubp *hubp = pipe_ctx->plane_res.hubp;
479 struct dpp *dpp = pipe_ctx->plane_res.dpp;
480
481 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
482
483 /* In flip immediate with pipe splitting case GSL is used for
484 * synchronization so we must disable it when the plane is disabled.
485 */
486 if (pipe_ctx->stream_res.gsl_group != 0)
487 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
488
489 dc->hwss.set_flip_control_gsl(pipe_ctx, false);
490
491 hubp->funcs->hubp_clk_cntl(hubp, false);
492
493 dpp->funcs->dpp_dppclk_control(dpp, false, false);
494
495 hubp->power_gated = true;
496 dc->optimized_required = false; /* We're powering off, no need to optimize */
497
498 dc->hwss.plane_atomic_power_down(dc,
499 pipe_ctx->plane_res.dpp,
500 pipe_ctx->plane_res.hubp);
501
502 pipe_ctx->stream = NULL;
503 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
504 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
505 pipe_ctx->top_pipe = NULL;
506 pipe_ctx->bottom_pipe = NULL;
507 pipe_ctx->plane_state = NULL;
508 }
509
510
dcn20_disable_plane(struct dc * dc,struct pipe_ctx * pipe_ctx)511 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
512 {
513 DC_LOGGER_INIT(dc->ctx->logger);
514
515 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
516 return;
517
518 dcn20_plane_atomic_disable(dc, pipe_ctx);
519
520 DC_LOG_DC("Power down front end %d\n",
521 pipe_ctx->pipe_idx);
522 }
523
dcn20_enable_stream_timing(struct pipe_ctx * pipe_ctx,struct dc_state * context,struct dc * dc)524 enum dc_status dcn20_enable_stream_timing(
525 struct pipe_ctx *pipe_ctx,
526 struct dc_state *context,
527 struct dc *dc)
528 {
529 struct dc_stream_state *stream = pipe_ctx->stream;
530 struct drr_params params = {0};
531 unsigned int event_triggers = 0;
532 struct pipe_ctx *odm_pipe;
533 int opp_cnt = 1;
534 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
535
536 /* by upper caller loop, pipe0 is parent pipe and be called first.
537 * back end is set up by for pipe0. Other children pipe share back end
538 * with pipe 0. No program is needed.
539 */
540 if (pipe_ctx->top_pipe != NULL)
541 return DC_OK;
542
543 /* TODO check if timing_changed, disable stream if timing changed */
544
545 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
546 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
547 opp_cnt++;
548 }
549
550 if (opp_cnt > 1)
551 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
552 pipe_ctx->stream_res.tg,
553 opp_inst, opp_cnt,
554 &pipe_ctx->stream->timing);
555
556 /* HW program guide assume display already disable
557 * by unplug sequence. OTG assume stop.
558 */
559 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
560
561 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
562 pipe_ctx->clock_source,
563 &pipe_ctx->stream_res.pix_clk_params,
564 &pipe_ctx->pll_settings)) {
565 BREAK_TO_DEBUGGER();
566 return DC_ERROR_UNEXPECTED;
567 }
568
569 pipe_ctx->stream_res.tg->funcs->program_timing(
570 pipe_ctx->stream_res.tg,
571 &stream->timing,
572 pipe_ctx->pipe_dlg_param.vready_offset,
573 pipe_ctx->pipe_dlg_param.vstartup_start,
574 pipe_ctx->pipe_dlg_param.vupdate_offset,
575 pipe_ctx->pipe_dlg_param.vupdate_width,
576 pipe_ctx->stream->signal,
577 true);
578
579 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
580 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
581 odm_pipe->stream_res.opp,
582 true);
583
584 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
585 pipe_ctx->stream_res.opp,
586 true);
587
588 dc->hwss.blank_pixel_data(dc, pipe_ctx, true);
589
590 /* VTG is within DCHUB command block. DCFCLK is always on */
591 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
592 BREAK_TO_DEBUGGER();
593 return DC_ERROR_UNEXPECTED;
594 }
595
596 dcn20_hwss_wait_for_blank_complete(pipe_ctx->stream_res.opp);
597
598 params.vertical_total_min = stream->adjust.v_total_min;
599 params.vertical_total_max = stream->adjust.v_total_max;
600 params.vertical_total_mid = stream->adjust.v_total_mid;
601 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
602 if (pipe_ctx->stream_res.tg->funcs->set_drr)
603 pipe_ctx->stream_res.tg->funcs->set_drr(
604 pipe_ctx->stream_res.tg, ¶ms);
605
606 // DRR should set trigger event to monitor surface update event
607 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
608 event_triggers = 0x80;
609 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
610 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
611 pipe_ctx->stream_res.tg, event_triggers);
612
613 /* TODO program crtc source select for non-virtual signal*/
614 /* TODO program FMT */
615 /* TODO setup link_enc */
616 /* TODO set stream attributes */
617 /* TODO program audio */
618 /* TODO enable stream if timing changed */
619 /* TODO unblank stream if DP */
620
621 return DC_OK;
622 }
623
dcn20_program_output_csc(struct dc * dc,struct pipe_ctx * pipe_ctx,enum dc_color_space colorspace,uint16_t * matrix,int opp_id)624 void dcn20_program_output_csc(struct dc *dc,
625 struct pipe_ctx *pipe_ctx,
626 enum dc_color_space colorspace,
627 uint16_t *matrix,
628 int opp_id)
629 {
630 struct mpc *mpc = dc->res_pool->mpc;
631 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
632 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
633
634 if (mpc->funcs->power_on_mpc_mem_pwr)
635 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
636
637 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
638 if (mpc->funcs->set_output_csc != NULL)
639 mpc->funcs->set_output_csc(mpc,
640 opp_id,
641 matrix,
642 ocsc_mode);
643 } else {
644 if (mpc->funcs->set_ocsc_default != NULL)
645 mpc->funcs->set_ocsc_default(mpc,
646 opp_id,
647 colorspace,
648 ocsc_mode);
649 }
650 }
651
dcn20_set_output_transfer_func(struct pipe_ctx * pipe_ctx,const struct dc_stream_state * stream)652 bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
653 const struct dc_stream_state *stream)
654 {
655 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
656 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
657 struct pwl_params *params = NULL;
658 /*
659 * program OGAM only for the top pipe
660 * if there is a pipe split then fix diagnostic is required:
661 * how to pass OGAM parameter for stream.
662 * if programming for all pipes is required then remove condition
663 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
664 */
665 if (mpc->funcs->power_on_mpc_mem_pwr)
666 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
667 if (pipe_ctx->top_pipe == NULL
668 && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
669 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
670 params = &stream->out_transfer_func->pwl;
671 else if (pipe_ctx->stream->out_transfer_func->type ==
672 TF_TYPE_DISTRIBUTED_POINTS &&
673 cm_helper_translate_curve_to_hw_format(
674 stream->out_transfer_func,
675 &mpc->blender_params, false))
676 params = &mpc->blender_params;
677 /*
678 * there is no ROM
679 */
680 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
681 BREAK_TO_DEBUGGER();
682 }
683 /*
684 * if above if is not executed then 'params' equal to 0 and set in bypass
685 */
686 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
687
688 return true;
689 }
690
dcn20_set_blend_lut(struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)691 static bool dcn20_set_blend_lut(
692 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
693 {
694 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
695 bool result = true;
696 struct pwl_params *blend_lut = NULL;
697
698 if (plane_state->blend_tf) {
699 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
700 blend_lut = &plane_state->blend_tf->pwl;
701 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
702 cm_helper_translate_curve_to_hw_format(
703 plane_state->blend_tf,
704 &dpp_base->regamma_params, false);
705 blend_lut = &dpp_base->regamma_params;
706 }
707 }
708 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
709
710 return result;
711 }
712
dcn20_set_shaper_3dlut(struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)713 static bool dcn20_set_shaper_3dlut(
714 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
715 {
716 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
717 bool result = true;
718 struct pwl_params *shaper_lut = NULL;
719
720 if (plane_state->in_shaper_func) {
721 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
722 shaper_lut = &plane_state->in_shaper_func->pwl;
723 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
724 cm_helper_translate_curve_to_hw_format(
725 plane_state->in_shaper_func,
726 &dpp_base->shaper_params, true);
727 shaper_lut = &dpp_base->shaper_params;
728 }
729 }
730
731 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
732 if (plane_state->lut3d_func &&
733 plane_state->lut3d_func->state.bits.initialized == 1)
734 result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
735 &plane_state->lut3d_func->lut_3d);
736 else
737 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
738
739 if (plane_state->lut3d_func &&
740 plane_state->lut3d_func->state.bits.initialized == 1 &&
741 plane_state->lut3d_func->hdr_multiplier != 0)
742 dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base,
743 plane_state->lut3d_func->hdr_multiplier);
744 else
745 dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base, 0x1f000);
746
747 return result;
748 }
749
dcn20_set_input_transfer_func(struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)750 bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
751 const struct dc_plane_state *plane_state)
752 {
753 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
754 const struct dc_transfer_func *tf = NULL;
755 bool result = true;
756 bool use_degamma_ram = false;
757
758 if (dpp_base == NULL || plane_state == NULL)
759 return false;
760
761 dcn20_set_shaper_3dlut(pipe_ctx, plane_state);
762 dcn20_set_blend_lut(pipe_ctx, plane_state);
763
764 if (plane_state->in_transfer_func)
765 tf = plane_state->in_transfer_func;
766
767
768 if (tf == NULL) {
769 dpp_base->funcs->dpp_set_degamma(dpp_base,
770 IPP_DEGAMMA_MODE_BYPASS);
771 return true;
772 }
773
774 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS)
775 use_degamma_ram = true;
776
777 if (use_degamma_ram == true) {
778 if (tf->type == TF_TYPE_HWPWL)
779 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
780 &tf->pwl);
781 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
782 cm_helper_translate_curve_to_degamma_hw_format(tf,
783 &dpp_base->degamma_params);
784 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
785 &dpp_base->degamma_params);
786 }
787 return true;
788 }
789 /* handle here the optimized cases when de-gamma ROM could be used.
790 *
791 */
792 if (tf->type == TF_TYPE_PREDEFINED) {
793 switch (tf->tf) {
794 case TRANSFER_FUNCTION_SRGB:
795 dpp_base->funcs->dpp_set_degamma(dpp_base,
796 IPP_DEGAMMA_MODE_HW_sRGB);
797 break;
798 case TRANSFER_FUNCTION_BT709:
799 dpp_base->funcs->dpp_set_degamma(dpp_base,
800 IPP_DEGAMMA_MODE_HW_xvYCC);
801 break;
802 case TRANSFER_FUNCTION_LINEAR:
803 dpp_base->funcs->dpp_set_degamma(dpp_base,
804 IPP_DEGAMMA_MODE_BYPASS);
805 break;
806 case TRANSFER_FUNCTION_PQ:
807 default:
808 result = false;
809 break;
810 }
811 } else if (tf->type == TF_TYPE_BYPASS)
812 dpp_base->funcs->dpp_set_degamma(dpp_base,
813 IPP_DEGAMMA_MODE_BYPASS);
814 else {
815 /*
816 * if we are here, we did not handle correctly.
817 * fix is required for this use case
818 */
819 BREAK_TO_DEBUGGER();
820 dpp_base->funcs->dpp_set_degamma(dpp_base,
821 IPP_DEGAMMA_MODE_BYPASS);
822 }
823
824 return result;
825 }
826
dcn20_update_odm(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx)827 static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
828 {
829 struct pipe_ctx *odm_pipe;
830 int opp_cnt = 1;
831 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
832
833 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
834 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
835 opp_cnt++;
836 }
837
838 if (opp_cnt > 1)
839 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
840 pipe_ctx->stream_res.tg,
841 opp_inst, opp_cnt,
842 &pipe_ctx->stream->timing);
843 else
844 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
845 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
846 }
847
dcn20_blank_pixel_data(struct dc * dc,struct pipe_ctx * pipe_ctx,bool blank)848 void dcn20_blank_pixel_data(
849 struct dc *dc,
850 struct pipe_ctx *pipe_ctx,
851 bool blank)
852 {
853 struct tg_color black_color = {0};
854 struct stream_resource *stream_res = &pipe_ctx->stream_res;
855 struct dc_stream_state *stream = pipe_ctx->stream;
856 enum dc_color_space color_space = stream->output_color_space;
857 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
858 struct pipe_ctx *odm_pipe;
859 int odm_cnt = 1;
860
861 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
862 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
863
864 /* get opp dpg blank color */
865 color_space_to_black_color(dc, color_space, &black_color);
866
867 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
868 odm_cnt++;
869
870 width = width / odm_cnt;
871
872 if (blank) {
873 if (stream_res->abm)
874 stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
875
876 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
877 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
878 } else {
879 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
880 }
881
882 stream_res->opp->funcs->opp_set_disp_pattern_generator(
883 stream_res->opp,
884 test_pattern,
885 stream->timing.display_color_depth,
886 &black_color,
887 width,
888 height);
889
890 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
891 odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
892 odm_pipe->stream_res.opp,
893 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
894 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
895 stream->timing.display_color_depth,
896 &black_color,
897 width,
898 height);
899 }
900
901 if (!blank)
902 if (stream_res->abm) {
903 stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1);
904 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
905 }
906 }
907
908
dcn20_power_on_plane(struct dce_hwseq * hws,struct pipe_ctx * pipe_ctx)909 static void dcn20_power_on_plane(
910 struct dce_hwseq *hws,
911 struct pipe_ctx *pipe_ctx)
912 {
913 DC_LOGGER_INIT(hws->ctx->logger);
914 if (REG(DC_IP_REQUEST_CNTL)) {
915 REG_SET(DC_IP_REQUEST_CNTL, 0,
916 IP_REQUEST_EN, 1);
917 dcn20_dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
918 dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
919 REG_SET(DC_IP_REQUEST_CNTL, 0,
920 IP_REQUEST_EN, 0);
921 DC_LOG_DEBUG(
922 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
923 }
924 }
925
dcn20_enable_plane(struct dc * dc,struct pipe_ctx * pipe_ctx,struct dc_state * context)926 void dcn20_enable_plane(
927 struct dc *dc,
928 struct pipe_ctx *pipe_ctx,
929 struct dc_state *context)
930 {
931 //if (dc->debug.sanity_checks) {
932 // dcn10_verify_allow_pstate_change_high(dc);
933 //}
934 dcn20_power_on_plane(dc->hwseq, pipe_ctx);
935
936 /* enable DCFCLK current DCHUB */
937 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
938
939 /* initialize HUBP on power up */
940 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
941
942 /* make sure OPP_PIPE_CLOCK_EN = 1 */
943 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
944 pipe_ctx->stream_res.opp,
945 true);
946
947 /* TODO: enable/disable in dm as per update type.
948 if (plane_state) {
949 DC_LOG_DC(dc->ctx->logger,
950 "Pipe:%d 0x%x: addr hi:0x%x, "
951 "addr low:0x%x, "
952 "src: %d, %d, %d,"
953 " %d; dst: %d, %d, %d, %d;\n",
954 pipe_ctx->pipe_idx,
955 plane_state,
956 plane_state->address.grph.addr.high_part,
957 plane_state->address.grph.addr.low_part,
958 plane_state->src_rect.x,
959 plane_state->src_rect.y,
960 plane_state->src_rect.width,
961 plane_state->src_rect.height,
962 plane_state->dst_rect.x,
963 plane_state->dst_rect.y,
964 plane_state->dst_rect.width,
965 plane_state->dst_rect.height);
966
967 DC_LOG_DC(dc->ctx->logger,
968 "Pipe %d: width, height, x, y format:%d\n"
969 "viewport:%d, %d, %d, %d\n"
970 "recout: %d, %d, %d, %d\n",
971 pipe_ctx->pipe_idx,
972 plane_state->format,
973 pipe_ctx->plane_res.scl_data.viewport.width,
974 pipe_ctx->plane_res.scl_data.viewport.height,
975 pipe_ctx->plane_res.scl_data.viewport.x,
976 pipe_ctx->plane_res.scl_data.viewport.y,
977 pipe_ctx->plane_res.scl_data.recout.width,
978 pipe_ctx->plane_res.scl_data.recout.height,
979 pipe_ctx->plane_res.scl_data.recout.x,
980 pipe_ctx->plane_res.scl_data.recout.y);
981 print_rq_dlg_ttu(dc, pipe_ctx);
982 }
983 */
984 if (dc->vm_pa_config.valid) {
985 struct vm_system_aperture_param apt;
986
987 apt.sys_default.quad_part = 0;
988
989 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
990 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
991
992 // Program system aperture settings
993 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
994 }
995
996 // if (dc->debug.sanity_checks) {
997 // dcn10_verify_allow_pstate_change_high(dc);
998 // }
999 }
1000
1001
dcn20_program_pipe(struct dc * dc,struct pipe_ctx * pipe_ctx,struct dc_state * context)1002 static void dcn20_program_pipe(
1003 struct dc *dc,
1004 struct pipe_ctx *pipe_ctx,
1005 struct dc_state *context)
1006 {
1007 pipe_ctx->plane_state->update_flags.bits.full_update =
1008 context->commit_hints.full_update_needed ? 1 : pipe_ctx->plane_state->update_flags.bits.full_update;
1009
1010 if (pipe_ctx->plane_state->update_flags.bits.full_update)
1011 dcn20_enable_plane(dc, pipe_ctx, context);
1012
1013 update_dchubp_dpp(dc, pipe_ctx, context);
1014
1015 set_hdr_multiplier(pipe_ctx);
1016
1017 if (pipe_ctx->plane_state->update_flags.bits.full_update ||
1018 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1019 pipe_ctx->plane_state->update_flags.bits.gamma_change)
1020 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
1021
1022 /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1023 * only do gamma programming for full update.
1024 * TODO: This can be further optimized/cleaned up
1025 * Always call this for now since it does memcmp inside before
1026 * doing heavy calculation and programming
1027 */
1028 if (pipe_ctx->plane_state->update_flags.bits.full_update)
1029 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
1030 }
1031
dcn20_program_all_pipe_in_tree(struct dc * dc,struct pipe_ctx * pipe_ctx,struct dc_state * context)1032 static void dcn20_program_all_pipe_in_tree(
1033 struct dc *dc,
1034 struct pipe_ctx *pipe_ctx,
1035 struct dc_state *context)
1036 {
1037 if (pipe_ctx->top_pipe == NULL && !pipe_ctx->prev_odm_pipe) {
1038 bool blank = !is_pipe_tree_visible(pipe_ctx);
1039
1040 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1041 pipe_ctx->stream_res.tg,
1042 pipe_ctx->pipe_dlg_param.vready_offset,
1043 pipe_ctx->pipe_dlg_param.vstartup_start,
1044 pipe_ctx->pipe_dlg_param.vupdate_offset,
1045 pipe_ctx->pipe_dlg_param.vupdate_width);
1046
1047 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1048 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1049
1050 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
1051
1052 if (dc->hwss.update_odm)
1053 dc->hwss.update_odm(dc, context, pipe_ctx);
1054 }
1055
1056 if (pipe_ctx->plane_state != NULL)
1057 dcn20_program_pipe(dc, pipe_ctx, context);
1058
1059 if (pipe_ctx->bottom_pipe != NULL) {
1060 ASSERT(pipe_ctx->bottom_pipe != pipe_ctx);
1061 dcn20_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
1062 } else if (pipe_ctx->next_odm_pipe != NULL) {
1063 ASSERT(pipe_ctx->next_odm_pipe != pipe_ctx);
1064 dcn20_program_all_pipe_in_tree(dc, pipe_ctx->next_odm_pipe, context);
1065 }
1066 }
1067
dcn20_pipe_control_lock_global(struct dc * dc,struct pipe_ctx * pipe,bool lock)1068 void dcn20_pipe_control_lock_global(
1069 struct dc *dc,
1070 struct pipe_ctx *pipe,
1071 bool lock)
1072 {
1073 if (lock) {
1074 pipe->stream_res.tg->funcs->lock_doublebuffer_enable(
1075 pipe->stream_res.tg);
1076 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1077 } else {
1078 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1079 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
1080 CRTC_STATE_VACTIVE);
1081 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
1082 CRTC_STATE_VBLANK);
1083 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
1084 CRTC_STATE_VACTIVE);
1085 pipe->stream_res.tg->funcs->lock_doublebuffer_disable(
1086 pipe->stream_res.tg);
1087 }
1088 }
1089
dcn20_pipe_control_lock(struct dc * dc,struct pipe_ctx * pipe,bool lock)1090 void dcn20_pipe_control_lock(
1091 struct dc *dc,
1092 struct pipe_ctx *pipe,
1093 bool lock)
1094 {
1095 bool flip_immediate = false;
1096
1097 /* use TG master update lock to lock everything on the TG
1098 * therefore only top pipe need to lock
1099 */
1100 if (pipe->top_pipe)
1101 return;
1102
1103 if (pipe->plane_state != NULL)
1104 flip_immediate = pipe->plane_state->flip_immediate;
1105
1106 /* In flip immediate and pipe splitting case, we need to use GSL
1107 * for synchronization. Only do setup on locking and on flip type change.
1108 */
1109 if (lock && pipe->bottom_pipe != NULL)
1110 if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
1111 (!flip_immediate && pipe->stream_res.gsl_group > 0))
1112 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
1113
1114 if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
1115 if (lock)
1116 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
1117 else
1118 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);
1119 } else {
1120 if (lock)
1121 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1122 else
1123 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1124 }
1125 }
1126
dcn20_apply_ctx_for_surface(struct dc * dc,const struct dc_stream_state * stream,int num_planes,struct dc_state * context)1127 static void dcn20_apply_ctx_for_surface(
1128 struct dc *dc,
1129 const struct dc_stream_state *stream,
1130 int num_planes,
1131 struct dc_state *context)
1132 {
1133 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
1134 int i;
1135 struct timing_generator *tg;
1136 bool removed_pipe[6] = { false };
1137 bool interdependent_update = false;
1138 struct pipe_ctx *top_pipe_to_program =
1139 find_top_pipe_for_stream(dc, context, stream);
1140 struct pipe_ctx *prev_top_pipe_to_program =
1141 find_top_pipe_for_stream(dc, dc->current_state, stream);
1142 DC_LOGGER_INIT(dc->ctx->logger);
1143
1144 if (!top_pipe_to_program)
1145 return;
1146
1147 /* Carry over GSL groups in case the context is changing. */
1148 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1149 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1150 struct pipe_ctx *old_pipe_ctx =
1151 &dc->current_state->res_ctx.pipe_ctx[i];
1152
1153 if (pipe_ctx->stream == stream &&
1154 pipe_ctx->stream == old_pipe_ctx->stream)
1155 pipe_ctx->stream_res.gsl_group =
1156 old_pipe_ctx->stream_res.gsl_group;
1157 }
1158
1159 tg = top_pipe_to_program->stream_res.tg;
1160
1161 interdependent_update = top_pipe_to_program->plane_state &&
1162 top_pipe_to_program->plane_state->update_flags.bits.full_update;
1163
1164 if (interdependent_update)
1165 lock_all_pipes(dc, context, true);
1166 else
1167 dcn20_pipe_control_lock(dc, top_pipe_to_program, true);
1168
1169 if (num_planes == 0) {
1170 /* OTG blank before remove all front end */
1171 dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
1172 }
1173
1174 /* Disconnect unused mpcc */
1175 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1176 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1177 struct pipe_ctx *old_pipe_ctx =
1178 &dc->current_state->res_ctx.pipe_ctx[i];
1179 /*
1180 * Powergate reused pipes that are not powergated
1181 * fairly hacky right now, using opp_id as indicator
1182 * TODO: After move dc_post to dc_update, this will
1183 * be removed.
1184 */
1185 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
1186 if (old_pipe_ctx->stream_res.tg == tg &&
1187 old_pipe_ctx->plane_res.hubp &&
1188 old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID)
1189 dc->hwss.disable_plane(dc, old_pipe_ctx);
1190 }
1191
1192 if ((!pipe_ctx->plane_state ||
1193 pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) &&
1194 old_pipe_ctx->plane_state &&
1195 old_pipe_ctx->stream_res.tg == tg) {
1196
1197 dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx);
1198 removed_pipe[i] = true;
1199
1200 DC_LOG_DC("Reset mpcc for pipe %d\n",
1201 old_pipe_ctx->pipe_idx);
1202 }
1203 }
1204
1205 if (num_planes > 0)
1206 dcn20_program_all_pipe_in_tree(dc, top_pipe_to_program, context);
1207
1208 /* Program secondary blending tree and writeback pipes */
1209 if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree))
1210 dc->hwss.program_all_writeback_pipes_in_tree(dc, stream, context);
1211
1212 if (interdependent_update)
1213 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1214 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1215
1216 /* Skip inactive pipes and ones already updated */
1217 if (!pipe_ctx->stream || pipe_ctx->stream == stream ||
1218 !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg))
1219 continue;
1220
1221 pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent(
1222 pipe_ctx->plane_res.hubp,
1223 &pipe_ctx->dlg_regs,
1224 &pipe_ctx->ttu_regs);
1225 }
1226
1227 if (interdependent_update)
1228 lock_all_pipes(dc, context, false);
1229 else
1230 dcn20_pipe_control_lock(dc, top_pipe_to_program, false);
1231
1232 for (i = 0; i < dc->res_pool->pipe_count; i++)
1233 if (removed_pipe[i])
1234 dcn20_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1235
1236 /*
1237 * If we are enabling a pipe, we need to wait for pending clear as this is a critical
1238 * part of the enable operation otherwise, DM may request an immediate flip which
1239 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
1240 * is unsupported on DCN.
1241 */
1242 i = 0;
1243 if (num_planes > 0 && top_pipe_to_program &&
1244 (prev_top_pipe_to_program == NULL || prev_top_pipe_to_program->plane_state == NULL)) {
1245 while (i < TIMEOUT_FOR_PIPE_ENABLE_MS &&
1246 top_pipe_to_program->plane_res.hubp->funcs->hubp_is_flip_pending(top_pipe_to_program->plane_res.hubp)) {
1247 i += 1;
1248 msleep(1);
1249 }
1250 }
1251 }
1252
1253
dcn20_prepare_bandwidth(struct dc * dc,struct dc_state * context)1254 void dcn20_prepare_bandwidth(
1255 struct dc *dc,
1256 struct dc_state *context)
1257 {
1258 struct hubbub *hubbub = dc->res_pool->hubbub;
1259
1260 dc->clk_mgr->funcs->update_clocks(
1261 dc->clk_mgr,
1262 context,
1263 false);
1264
1265 /* program dchubbub watermarks */
1266 hubbub->funcs->program_watermarks(hubbub,
1267 &context->bw_ctx.bw.dcn.watermarks,
1268 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1269 false);
1270 }
1271
dcn20_optimize_bandwidth(struct dc * dc,struct dc_state * context)1272 void dcn20_optimize_bandwidth(
1273 struct dc *dc,
1274 struct dc_state *context)
1275 {
1276 struct hubbub *hubbub = dc->res_pool->hubbub;
1277
1278 /* program dchubbub watermarks */
1279 hubbub->funcs->program_watermarks(hubbub,
1280 &context->bw_ctx.bw.dcn.watermarks,
1281 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1282 true);
1283
1284 dc->clk_mgr->funcs->update_clocks(
1285 dc->clk_mgr,
1286 context,
1287 true);
1288 }
1289
dcn20_update_bandwidth(struct dc * dc,struct dc_state * context)1290 bool dcn20_update_bandwidth(
1291 struct dc *dc,
1292 struct dc_state *context)
1293 {
1294 int i;
1295
1296 /* recalculate DML parameters */
1297 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
1298 return false;
1299
1300 /* apply updated bandwidth parameters */
1301 dc->hwss.prepare_bandwidth(dc, context);
1302
1303 /* update hubp configs for all pipes */
1304 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1305 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1306
1307 if (pipe_ctx->plane_state == NULL)
1308 continue;
1309
1310 if (pipe_ctx->top_pipe == NULL) {
1311 bool blank = !is_pipe_tree_visible(pipe_ctx);
1312
1313 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1314 pipe_ctx->stream_res.tg,
1315 pipe_ctx->pipe_dlg_param.vready_offset,
1316 pipe_ctx->pipe_dlg_param.vstartup_start,
1317 pipe_ctx->pipe_dlg_param.vupdate_offset,
1318 pipe_ctx->pipe_dlg_param.vupdate_width);
1319
1320 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1321 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1322 if (pipe_ctx->prev_odm_pipe == NULL)
1323 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
1324 }
1325
1326 pipe_ctx->plane_res.hubp->funcs->hubp_setup(
1327 pipe_ctx->plane_res.hubp,
1328 &pipe_ctx->dlg_regs,
1329 &pipe_ctx->ttu_regs,
1330 &pipe_ctx->rq_regs,
1331 &pipe_ctx->pipe_dlg_param);
1332 }
1333
1334 return true;
1335 }
1336
dcn20_enable_writeback(struct dc * dc,const struct dc_stream_status * stream_status,struct dc_writeback_info * wb_info)1337 static void dcn20_enable_writeback(
1338 struct dc *dc,
1339 const struct dc_stream_status *stream_status,
1340 struct dc_writeback_info *wb_info)
1341 {
1342 struct dwbc *dwb;
1343 struct mcif_wb *mcif_wb;
1344 struct timing_generator *optc;
1345
1346 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
1347 ASSERT(wb_info->wb_enabled);
1348 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
1349 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
1350
1351 /* set the OPTC source mux */
1352 ASSERT(stream_status->primary_otg_inst < MAX_PIPES);
1353 optc = dc->res_pool->timing_generators[stream_status->primary_otg_inst];
1354 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
1355 /* set MCIF_WB buffer and arbitration configuration */
1356 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
1357 mcif_wb->funcs->config_mcif_arb(mcif_wb, &dc->current_state->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
1358 /* Enable MCIF_WB */
1359 mcif_wb->funcs->enable_mcif(mcif_wb);
1360 /* Enable DWB */
1361 dwb->funcs->enable(dwb, &wb_info->dwb_params);
1362 /* TODO: add sequence to enable/disable warmup */
1363 }
1364
dcn20_disable_writeback(struct dc * dc,unsigned int dwb_pipe_inst)1365 void dcn20_disable_writeback(
1366 struct dc *dc,
1367 unsigned int dwb_pipe_inst)
1368 {
1369 struct dwbc *dwb;
1370 struct mcif_wb *mcif_wb;
1371
1372 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
1373 dwb = dc->res_pool->dwbc[dwb_pipe_inst];
1374 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
1375
1376 dwb->funcs->disable(dwb);
1377 mcif_wb->funcs->disable_mcif(mcif_wb);
1378 }
1379
dcn20_hwss_wait_for_blank_complete(struct output_pixel_processor * opp)1380 bool dcn20_hwss_wait_for_blank_complete(
1381 struct output_pixel_processor *opp)
1382 {
1383 int counter;
1384
1385 for (counter = 0; counter < 1000; counter++) {
1386 if (opp->funcs->dpg_is_blanked(opp))
1387 break;
1388
1389 udelay(100);
1390 }
1391
1392 if (counter == 1000) {
1393 dm_error("DC: failed to blank crtc!\n");
1394 return false;
1395 }
1396
1397 return true;
1398 }
1399
dcn20_dmdata_status_done(struct pipe_ctx * pipe_ctx)1400 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
1401 {
1402 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1403
1404 if (!hubp)
1405 return false;
1406 return hubp->funcs->dmdata_status_done(hubp);
1407 }
1408
dcn20_disable_stream_gating(struct dc * dc,struct pipe_ctx * pipe_ctx)1409 static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
1410 {
1411 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1412 struct dce_hwseq *hws = dc->hwseq;
1413
1414 if (pipe_ctx->stream_res.dsc) {
1415 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1416
1417 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
1418 while (odm_pipe) {
1419 dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
1420 odm_pipe = odm_pipe->next_odm_pipe;
1421 }
1422 }
1423 #endif
1424 }
1425
dcn20_enable_stream_gating(struct dc * dc,struct pipe_ctx * pipe_ctx)1426 static void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
1427 {
1428 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1429 struct dce_hwseq *hws = dc->hwseq;
1430
1431 if (pipe_ctx->stream_res.dsc) {
1432 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1433
1434 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
1435 while (odm_pipe) {
1436 dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
1437 odm_pipe = odm_pipe->next_odm_pipe;
1438 }
1439 }
1440 #endif
1441 }
1442
dcn20_set_dmdata_attributes(struct pipe_ctx * pipe_ctx)1443 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
1444 {
1445 struct dc_dmdata_attributes attr = { 0 };
1446 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1447
1448 attr.dmdata_mode = DMDATA_HW_MODE;
1449 attr.dmdata_size =
1450 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
1451 attr.address.quad_part =
1452 pipe_ctx->stream->dmdata_address.quad_part;
1453 attr.dmdata_dl_delta = 0;
1454 attr.dmdata_qos_mode = 0;
1455 attr.dmdata_qos_level = 0;
1456 attr.dmdata_repeat = 1; /* always repeat */
1457 attr.dmdata_updated = 1;
1458 attr.dmdata_sw_data = NULL;
1459
1460 hubp->funcs->dmdata_set_attributes(hubp, &attr);
1461 }
1462
dcn20_disable_stream(struct pipe_ctx * pipe_ctx)1463 void dcn20_disable_stream(struct pipe_ctx *pipe_ctx)
1464 {
1465 dce110_disable_stream(pipe_ctx);
1466 }
1467
dcn20_init_vm_ctx(struct dce_hwseq * hws,struct dc * dc,struct dc_virtual_addr_space_config * va_config,int vmid)1468 static void dcn20_init_vm_ctx(
1469 struct dce_hwseq *hws,
1470 struct dc *dc,
1471 struct dc_virtual_addr_space_config *va_config,
1472 int vmid)
1473 {
1474 struct dcn_hubbub_virt_addr_config config;
1475
1476 if (vmid == 0) {
1477 ASSERT(0); /* VMID cannot be 0 for vm context */
1478 return;
1479 }
1480
1481 config.page_table_start_addr = va_config->page_table_start_addr;
1482 config.page_table_end_addr = va_config->page_table_end_addr;
1483 config.page_table_block_size = va_config->page_table_block_size_in_bytes;
1484 config.page_table_depth = va_config->page_table_depth;
1485 config.page_table_base_addr = va_config->page_table_base_addr;
1486
1487 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
1488 }
1489
dcn20_init_sys_ctx(struct dce_hwseq * hws,struct dc * dc,struct dc_phy_addr_space_config * pa_config)1490 static int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
1491 {
1492 struct dcn_hubbub_phys_addr_config config;
1493
1494 config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
1495 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
1496 config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
1497 config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
1498 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
1499 config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
1500 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
1501 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
1502 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
1503 config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
1504
1505 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
1506 }
1507
patch_address_for_sbs_tb_stereo(struct pipe_ctx * pipe_ctx,PHYSICAL_ADDRESS_LOC * addr)1508 static bool patch_address_for_sbs_tb_stereo(
1509 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
1510 {
1511 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1512 bool sec_split = pipe_ctx->top_pipe &&
1513 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1514 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
1515 (pipe_ctx->stream->timing.timing_3d_format ==
1516 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1517 pipe_ctx->stream->timing.timing_3d_format ==
1518 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
1519 *addr = plane_state->address.grph_stereo.left_addr;
1520 plane_state->address.grph_stereo.left_addr =
1521 plane_state->address.grph_stereo.right_addr;
1522 return true;
1523 }
1524
1525 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
1526 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1527 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1528 plane_state->address.grph_stereo.right_addr =
1529 plane_state->address.grph_stereo.left_addr;
1530 }
1531 return false;
1532 }
1533
1534
dcn20_update_plane_addr(const struct dc * dc,struct pipe_ctx * pipe_ctx)1535 static void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1536 {
1537 bool addr_patched = false;
1538 PHYSICAL_ADDRESS_LOC addr;
1539 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1540
1541 if (plane_state == NULL)
1542 return;
1543
1544 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1545
1546 // Call Helper to track VMID use
1547 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
1548
1549 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1550 pipe_ctx->plane_res.hubp,
1551 &plane_state->address,
1552 plane_state->flip_immediate);
1553
1554 plane_state->status.requested_address = plane_state->address;
1555
1556 if (plane_state->flip_immediate)
1557 plane_state->status.current_address = plane_state->address;
1558
1559 if (addr_patched)
1560 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
1561 }
1562
dcn20_unblank_stream(struct pipe_ctx * pipe_ctx,struct dc_link_settings * link_settings)1563 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
1564 struct dc_link_settings *link_settings)
1565 {
1566 struct encoder_unblank_param params = { { 0 } };
1567 struct dc_stream_state *stream = pipe_ctx->stream;
1568 struct dc_link *link = stream->link;
1569 struct pipe_ctx *odm_pipe;
1570
1571 params.opp_cnt = 1;
1572 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1573 params.opp_cnt++;
1574 }
1575 /* only 3 items below are used by unblank */
1576 params.timing = pipe_ctx->stream->timing;
1577
1578 params.link_settings.link_rate = link_settings->link_rate;
1579
1580 if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1581 if (optc1_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
1582 params.timing.pix_clk_100hz /= 2;
1583 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1584 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
1585 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms);
1586 }
1587
1588 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1589 link->dc->hwss.edp_backlight_control(link, true);
1590 }
1591 }
1592
dcn20_setup_vupdate_interrupt(struct pipe_ctx * pipe_ctx)1593 void dcn20_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx)
1594 {
1595 struct timing_generator *tg = pipe_ctx->stream_res.tg;
1596 int start_line = get_vupdate_offset_from_vsync(pipe_ctx);
1597
1598 if (start_line < 0)
1599 start_line = 0;
1600
1601 if (tg->funcs->setup_vertical_interrupt2)
1602 tg->funcs->setup_vertical_interrupt2(tg, start_line);
1603 }
1604
dcn20_reset_back_end_for_pipe(struct dc * dc,struct pipe_ctx * pipe_ctx,struct dc_state * context)1605 static void dcn20_reset_back_end_for_pipe(
1606 struct dc *dc,
1607 struct pipe_ctx *pipe_ctx,
1608 struct dc_state *context)
1609 {
1610 int i;
1611 DC_LOGGER_INIT(dc->ctx->logger);
1612 if (pipe_ctx->stream_res.stream_enc == NULL) {
1613 pipe_ctx->stream = NULL;
1614 return;
1615 }
1616
1617 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1618 /* DPMS may already disable */
1619 if (!pipe_ctx->stream->dpms_off)
1620 core_link_disable_stream(pipe_ctx);
1621 else if (pipe_ctx->stream_res.audio)
1622 dc->hwss.disable_audio_stream(pipe_ctx);
1623
1624 /* free acquired resources */
1625 if (pipe_ctx->stream_res.audio) {
1626 /*disable az_endpoint*/
1627 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
1628
1629 /*free audio*/
1630 if (dc->caps.dynamic_audio == true) {
1631 /*we have to dynamic arbitrate the audio endpoints*/
1632 /*we free the resource, need reset is_audio_acquired*/
1633 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
1634 pipe_ctx->stream_res.audio, false);
1635 pipe_ctx->stream_res.audio = NULL;
1636 }
1637 }
1638 }
1639 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1640 else if (pipe_ctx->stream_res.dsc) {
1641 dp_set_dsc_enable(pipe_ctx, false);
1642 }
1643 #endif
1644
1645 /* by upper caller loop, parent pipe: pipe0, will be reset last.
1646 * back end share by all pipes and will be disable only when disable
1647 * parent pipe.
1648 */
1649 if (pipe_ctx->top_pipe == NULL) {
1650 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
1651
1652 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
1653 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
1654 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1655 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1656
1657 if (pipe_ctx->stream_res.tg->funcs->set_drr)
1658 pipe_ctx->stream_res.tg->funcs->set_drr(
1659 pipe_ctx->stream_res.tg, NULL);
1660 }
1661
1662 for (i = 0; i < dc->res_pool->pipe_count; i++)
1663 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
1664 break;
1665
1666 if (i == dc->res_pool->pipe_count)
1667 return;
1668
1669 pipe_ctx->stream = NULL;
1670 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
1671 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
1672 }
1673
dcn20_reset_hw_ctx_wrap(struct dc * dc,struct dc_state * context)1674 static void dcn20_reset_hw_ctx_wrap(
1675 struct dc *dc,
1676 struct dc_state *context)
1677 {
1678 int i;
1679
1680 /* Reset Back End*/
1681 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1682 struct pipe_ctx *pipe_ctx_old =
1683 &dc->current_state->res_ctx.pipe_ctx[i];
1684 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1685
1686 if (!pipe_ctx_old->stream)
1687 continue;
1688
1689 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
1690 continue;
1691
1692 if (!pipe_ctx->stream ||
1693 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1694 struct clock_source *old_clk = pipe_ctx_old->clock_source;
1695
1696 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
1697 if (dc->hwss.enable_stream_gating)
1698 dc->hwss.enable_stream_gating(dc, pipe_ctx);
1699 if (old_clk)
1700 old_clk->funcs->cs_power_down(old_clk);
1701 }
1702 }
1703 }
1704
dcn20_update_mpcc(struct dc * dc,struct pipe_ctx * pipe_ctx)1705 static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
1706 {
1707 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1708 struct mpcc_blnd_cfg blnd_cfg = { {0} };
1709 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
1710 int mpcc_id;
1711 struct mpcc *new_mpcc;
1712 struct mpc *mpc = dc->res_pool->mpc;
1713 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
1714
1715 // input to MPCC is always RGB, by default leave black_color at 0
1716 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
1717 dcn10_get_hdr_visual_confirm_color(
1718 pipe_ctx, &blnd_cfg.black_color);
1719 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
1720 dcn10_get_surface_visual_confirm_color(
1721 pipe_ctx, &blnd_cfg.black_color);
1722 }
1723
1724 if (per_pixel_alpha)
1725 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
1726 else
1727 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
1728
1729 blnd_cfg.overlap_only = false;
1730 blnd_cfg.global_gain = 0xff;
1731
1732 if (pipe_ctx->plane_state->global_alpha)
1733 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
1734 else
1735 blnd_cfg.global_alpha = 0xff;
1736
1737 blnd_cfg.background_color_bpc = 4;
1738 blnd_cfg.bottom_gain_mode = 0;
1739 blnd_cfg.top_gain = 0x1f000;
1740 blnd_cfg.bottom_inside_gain = 0x1f000;
1741 blnd_cfg.bottom_outside_gain = 0x1f000;
1742 blnd_cfg.pre_multiplied_alpha = per_pixel_alpha;
1743
1744 /*
1745 * TODO: remove hack
1746 * Note: currently there is a bug in init_hw such that
1747 * on resume from hibernate, BIOS sets up MPCC0, and
1748 * we do mpcc_remove but the mpcc cannot go to idle
1749 * after remove. This cause us to pick mpcc1 here,
1750 * which causes a pstate hang for yet unknown reason.
1751 */
1752 mpcc_id = hubp->inst;
1753
1754 /* If there is no full update, don't need to touch MPC tree*/
1755 if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
1756 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
1757 return;
1758 }
1759
1760 /* check if this MPCC is already being used */
1761 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
1762 /* remove MPCC if being used */
1763 if (new_mpcc != NULL)
1764 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
1765 else
1766 if (dc->debug.sanity_checks)
1767 mpc->funcs->assert_mpcc_idle_before_connect(
1768 dc->res_pool->mpc, mpcc_id);
1769
1770 /* Call MPC to insert new plane */
1771 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
1772 mpc_tree_params,
1773 &blnd_cfg,
1774 NULL,
1775 NULL,
1776 hubp->inst,
1777 mpcc_id);
1778
1779 ASSERT(new_mpcc != NULL);
1780 hubp->opp_id = pipe_ctx->stream_res.opp->inst;
1781 hubp->mpcc_id = mpcc_id;
1782 }
1783
find_free_gsl_group(const struct dc * dc)1784 static int find_free_gsl_group(const struct dc *dc)
1785 {
1786 if (dc->res_pool->gsl_groups.gsl_0 == 0)
1787 return 1;
1788 if (dc->res_pool->gsl_groups.gsl_1 == 0)
1789 return 2;
1790 if (dc->res_pool->gsl_groups.gsl_2 == 0)
1791 return 3;
1792
1793 return 0;
1794 }
1795
1796 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
1797 * This is only used to lock pipes in pipe splitting case with immediate flip
1798 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
1799 * so we get tearing with freesync since we cannot flip multiple pipes
1800 * atomically.
1801 * We use GSL for this:
1802 * - immediate flip: find first available GSL group if not already assigned
1803 * program gsl with that group, set current OTG as master
1804 * and always us 0x4 = AND of flip_ready from all pipes
1805 * - vsync flip: disable GSL if used
1806 *
1807 * Groups in stream_res are stored as +1 from HW registers, i.e.
1808 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
1809 * Using a magic value like -1 would require tracking all inits/resets
1810 */
dcn20_setup_gsl_group_as_lock(const struct dc * dc,struct pipe_ctx * pipe_ctx,bool enable)1811 void dcn20_setup_gsl_group_as_lock(
1812 const struct dc *dc,
1813 struct pipe_ctx *pipe_ctx,
1814 bool enable)
1815 {
1816 struct gsl_params gsl;
1817 int group_idx;
1818
1819 memset(&gsl, 0, sizeof(struct gsl_params));
1820
1821 if (enable) {
1822 /* return if group already assigned since GSL was set up
1823 * for vsync flip, we would unassign so it can't be "left over"
1824 */
1825 if (pipe_ctx->stream_res.gsl_group > 0)
1826 return;
1827
1828 group_idx = find_free_gsl_group(dc);
1829 ASSERT(group_idx != 0);
1830 pipe_ctx->stream_res.gsl_group = group_idx;
1831
1832 /* set gsl group reg field and mark resource used */
1833 switch (group_idx) {
1834 case 1:
1835 gsl.gsl0_en = 1;
1836 dc->res_pool->gsl_groups.gsl_0 = 1;
1837 break;
1838 case 2:
1839 gsl.gsl1_en = 1;
1840 dc->res_pool->gsl_groups.gsl_1 = 1;
1841 break;
1842 case 3:
1843 gsl.gsl2_en = 1;
1844 dc->res_pool->gsl_groups.gsl_2 = 1;
1845 break;
1846 default:
1847 BREAK_TO_DEBUGGER();
1848 return; // invalid case
1849 }
1850 gsl.gsl_master_en = 1;
1851 } else {
1852 group_idx = pipe_ctx->stream_res.gsl_group;
1853 if (group_idx == 0)
1854 return; // if not in use, just return
1855
1856 pipe_ctx->stream_res.gsl_group = 0;
1857
1858 /* unset gsl group reg field and mark resource free */
1859 switch (group_idx) {
1860 case 1:
1861 gsl.gsl0_en = 0;
1862 dc->res_pool->gsl_groups.gsl_0 = 0;
1863 break;
1864 case 2:
1865 gsl.gsl1_en = 0;
1866 dc->res_pool->gsl_groups.gsl_1 = 0;
1867 break;
1868 case 3:
1869 gsl.gsl2_en = 0;
1870 dc->res_pool->gsl_groups.gsl_2 = 0;
1871 break;
1872 default:
1873 BREAK_TO_DEBUGGER();
1874 return;
1875 }
1876 gsl.gsl_master_en = 0;
1877 }
1878
1879 /* at this point we want to program whether it's to enable or disable */
1880 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
1881 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
1882 pipe_ctx->stream_res.tg->funcs->set_gsl(
1883 pipe_ctx->stream_res.tg,
1884 &gsl);
1885
1886 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
1887 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);
1888 } else
1889 BREAK_TO_DEBUGGER();
1890 }
1891
dcn20_set_flip_control_gsl(struct pipe_ctx * pipe_ctx,bool flip_immediate)1892 static void dcn20_set_flip_control_gsl(
1893 struct pipe_ctx *pipe_ctx,
1894 bool flip_immediate)
1895 {
1896 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
1897 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
1898 pipe_ctx->plane_res.hubp, flip_immediate);
1899
1900 }
1901
dcn20_enable_stream(struct pipe_ctx * pipe_ctx)1902 static void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
1903 {
1904 enum dc_lane_count lane_count =
1905 pipe_ctx->stream->link->cur_link_settings.lane_count;
1906
1907 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
1908 struct dc_link *link = pipe_ctx->stream->link;
1909
1910 uint32_t active_total_with_borders;
1911 uint32_t early_control = 0;
1912 struct timing_generator *tg = pipe_ctx->stream_res.tg;
1913
1914 /* For MST, there are multiply stream go to only one link.
1915 * connect DIG back_end to front_end while enable_stream and
1916 * disconnect them during disable_stream
1917 * BY this, it is logic clean to separate stream and link
1918 */
1919 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
1920 pipe_ctx->stream_res.stream_enc->id, true);
1921
1922 if (link->dc->hwss.program_dmdata_engine)
1923 link->dc->hwss.program_dmdata_engine(pipe_ctx);
1924
1925 link->dc->hwss.update_info_frame(pipe_ctx);
1926
1927 /* enable early control to avoid corruption on DP monitor*/
1928 active_total_with_borders =
1929 timing->h_addressable
1930 + timing->h_border_left
1931 + timing->h_border_right;
1932
1933 if (lane_count != 0)
1934 early_control = active_total_with_borders % lane_count;
1935
1936 if (early_control == 0)
1937 early_control = lane_count;
1938
1939 tg->funcs->set_early_control(tg, early_control);
1940
1941 /* enable audio only within mode set */
1942 if (pipe_ctx->stream_res.audio != NULL) {
1943 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1944 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
1945 }
1946 }
1947
dcn20_program_dmdata_engine(struct pipe_ctx * pipe_ctx)1948 static void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
1949 {
1950 struct dc_stream_state *stream = pipe_ctx->stream;
1951 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1952 bool enable = false;
1953 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
1954 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal)
1955 ? dmdata_dp
1956 : dmdata_hdmi;
1957
1958 /* if using dynamic meta, don't set up generic infopackets */
1959 if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
1960 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
1961 enable = true;
1962 }
1963
1964 if (!hubp)
1965 return;
1966
1967 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
1968 return;
1969
1970 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
1971 hubp->inst, mode);
1972 }
1973
dcn20_fpga_init_hw(struct dc * dc)1974 static void dcn20_fpga_init_hw(struct dc *dc)
1975 {
1976 int i, j;
1977 struct dce_hwseq *hws = dc->hwseq;
1978 struct resource_pool *res_pool = dc->res_pool;
1979 struct dc_state *context = dc->current_state;
1980
1981 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
1982 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
1983
1984 // Initialize the dccg
1985 if (res_pool->dccg->funcs->dccg_init)
1986 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
1987
1988 //Enable ability to power gate / don't force power on permanently
1989 dc->hwss.enable_power_gating_plane(hws, true);
1990
1991 // Specific to FPGA dccg and registers
1992 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
1993 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
1994
1995 dcn20_dccg_init(hws);
1996
1997 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
1998 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
1999 REG_WRITE(REFCLK_CNTL, 0);
2000 //
2001
2002
2003 /* Blank pixel data with OPP DPG */
2004 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2005 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2006
2007 if (tg->funcs->is_tg_enabled(tg))
2008 dcn20_init_blank(dc, tg);
2009 }
2010
2011 for (i = 0; i < res_pool->timing_generator_count; i++) {
2012 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2013
2014 if (tg->funcs->is_tg_enabled(tg))
2015 tg->funcs->lock(tg);
2016 }
2017
2018 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2019 struct dpp *dpp = res_pool->dpps[i];
2020
2021 dpp->funcs->dpp_reset(dpp);
2022 }
2023
2024 /* Reset all MPCC muxes */
2025 res_pool->mpc->funcs->mpc_init(res_pool->mpc);
2026
2027 /* initialize OPP mpc_tree parameter */
2028 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
2029 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
2030 res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2031 for (j = 0; j < MAX_PIPES; j++)
2032 res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
2033 }
2034
2035 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2036 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2037 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2038 struct hubp *hubp = dc->res_pool->hubps[i];
2039 struct dpp *dpp = dc->res_pool->dpps[i];
2040
2041 pipe_ctx->stream_res.tg = tg;
2042 pipe_ctx->pipe_idx = i;
2043
2044 pipe_ctx->plane_res.hubp = hubp;
2045 pipe_ctx->plane_res.dpp = dpp;
2046 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
2047 hubp->mpcc_id = dpp->inst;
2048 hubp->opp_id = OPP_ID_INVALID;
2049 hubp->power_gated = false;
2050 pipe_ctx->stream_res.opp = NULL;
2051
2052 hubp->funcs->hubp_init(hubp);
2053
2054 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
2055 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2056 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
2057 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
2058 /*to do*/
2059 hwss1_plane_atomic_disconnect(dc, pipe_ctx);
2060 }
2061
2062 /* initialize DWB pointer to MCIF_WB */
2063 for (i = 0; i < res_pool->res_cap->num_dwb; i++)
2064 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
2065
2066 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2067 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2068
2069 if (tg->funcs->is_tg_enabled(tg))
2070 tg->funcs->unlock(tg);
2071 }
2072
2073 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2074 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2075
2076 dc->hwss.disable_plane(dc, pipe_ctx);
2077
2078 pipe_ctx->stream_res.tg = NULL;
2079 pipe_ctx->plane_res.hubp = NULL;
2080 }
2081
2082 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2083 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2084
2085 tg->funcs->tg_init(tg);
2086 }
2087 }
2088
dcn20_hw_sequencer_construct(struct dc * dc)2089 void dcn20_hw_sequencer_construct(struct dc *dc)
2090 {
2091 dcn10_hw_sequencer_construct(dc);
2092 dc->hwss.unblank_stream = dcn20_unblank_stream;
2093 dc->hwss.update_plane_addr = dcn20_update_plane_addr;
2094 dc->hwss.enable_stream_timing = dcn20_enable_stream_timing;
2095 dc->hwss.program_triplebuffer = dcn20_program_tripleBuffer;
2096 dc->hwss.set_input_transfer_func = dcn20_set_input_transfer_func;
2097 dc->hwss.set_output_transfer_func = dcn20_set_output_transfer_func;
2098 dc->hwss.apply_ctx_for_surface = dcn20_apply_ctx_for_surface;
2099 dc->hwss.pipe_control_lock = dcn20_pipe_control_lock;
2100 dc->hwss.pipe_control_lock_global = dcn20_pipe_control_lock_global;
2101 dc->hwss.optimize_bandwidth = dcn20_optimize_bandwidth;
2102 dc->hwss.prepare_bandwidth = dcn20_prepare_bandwidth;
2103 dc->hwss.update_bandwidth = dcn20_update_bandwidth;
2104 dc->hwss.enable_writeback = dcn20_enable_writeback;
2105 dc->hwss.disable_writeback = dcn20_disable_writeback;
2106 dc->hwss.program_output_csc = dcn20_program_output_csc;
2107 dc->hwss.update_odm = dcn20_update_odm;
2108 dc->hwss.blank_pixel_data = dcn20_blank_pixel_data;
2109 dc->hwss.dmdata_status_done = dcn20_dmdata_status_done;
2110 dc->hwss.program_dmdata_engine = dcn20_program_dmdata_engine;
2111 dc->hwss.enable_stream = dcn20_enable_stream;
2112 dc->hwss.disable_stream = dcn20_disable_stream;
2113 dc->hwss.init_sys_ctx = dcn20_init_sys_ctx;
2114 dc->hwss.init_vm_ctx = dcn20_init_vm_ctx;
2115 dc->hwss.disable_stream_gating = dcn20_disable_stream_gating;
2116 dc->hwss.enable_stream_gating = dcn20_enable_stream_gating;
2117 dc->hwss.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt;
2118 dc->hwss.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap;
2119 dc->hwss.update_mpcc = dcn20_update_mpcc;
2120 dc->hwss.set_flip_control_gsl = dcn20_set_flip_control_gsl;
2121 dc->hwss.init_blank = dcn20_init_blank;
2122 dc->hwss.disable_plane = dcn20_disable_plane;
2123 dc->hwss.plane_atomic_disable = dcn20_plane_atomic_disable;
2124 dc->hwss.enable_power_gating_plane = dcn20_enable_power_gating_plane;
2125 dc->hwss.dpp_pg_control = dcn20_dpp_pg_control;
2126 dc->hwss.hubp_pg_control = dcn20_hubp_pg_control;
2127 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2128 dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
2129 #else
2130 dc->hwss.dsc_pg_control = NULL;
2131 #endif
2132 dc->hwss.disable_vga = dcn20_disable_vga;
2133
2134 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2135 dc->hwss.init_hw = dcn20_fpga_init_hw;
2136 dc->hwss.init_pipes = NULL;
2137 }
2138
2139
2140 }
2141
