1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/component.h>
9 #include <linux/delay.h>
10 #include <linux/iopoll.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/overflow.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/reset.h>
19
20 #include <drm/drm.h>
21 #include <drm/drm_atomic.h>
22 #include <drm/drm_atomic_uapi.h>
23 #include <drm/drm_crtc.h>
24 #include <drm/drm_flip_work.h>
25 #include <drm/drm_fourcc.h>
26 #include <drm/drm_gem_atomic_helper.h>
27 #include <drm/drm_gem_framebuffer_helper.h>
28 #include <drm/drm_plane_helper.h>
29 #include <drm/drm_probe_helper.h>
30 #include <drm/drm_self_refresh_helper.h>
31 #include <drm/drm_vblank.h>
32
33 #ifdef CONFIG_DRM_ANALOGIX_DP
34 #include <drm/bridge/analogix_dp.h>
35 #endif
36
37 #include "rockchip_drm_drv.h"
38 #include "rockchip_drm_gem.h"
39 #include "rockchip_drm_fb.h"
40 #include "rockchip_drm_vop.h"
41 #include "rockchip_rgb.h"
42
43 #define VOP_WIN_SET(vop, win, name, v) \
44 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
45 #define VOP_SCL_SET(vop, win, name, v) \
46 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
47 #define VOP_SCL_SET_EXT(vop, win, name, v) \
48 vop_reg_set(vop, &win->phy->scl->ext->name, \
49 win->base, ~0, v, #name)
50
51 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \
52 do { \
53 if (win_yuv2yuv && win_yuv2yuv->name.mask) \
54 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
55 } while (0)
56
57 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \
58 do { \
59 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \
60 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
61 } while (0)
62
63 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
64 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
65
66 #define VOP_REG_SET(vop, group, name, v) \
67 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
68
69 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
70 do { \
71 int i, reg = 0, mask = 0; \
72 for (i = 0; i < vop->data->intr->nintrs; i++) { \
73 if (vop->data->intr->intrs[i] & type) { \
74 reg |= (v) << i; \
75 mask |= 1 << i; \
76 } \
77 } \
78 VOP_INTR_SET_MASK(vop, name, mask, reg); \
79 } while (0)
80 #define VOP_INTR_GET_TYPE(vop, name, type) \
81 vop_get_intr_type(vop, &vop->data->intr->name, type)
82
83 #define VOP_WIN_GET(vop, win, name) \
84 vop_read_reg(vop, win->base, &win->phy->name)
85
86 #define VOP_WIN_HAS_REG(win, name) \
87 (!!(win->phy->name.mask))
88
89 #define VOP_WIN_GET_YRGBADDR(vop, win) \
90 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
91
92 #define VOP_WIN_TO_INDEX(vop_win) \
93 ((vop_win) - (vop_win)->vop->win)
94
95 #define VOP_AFBC_SET(vop, name, v) \
96 do { \
97 if ((vop)->data->afbc) \
98 vop_reg_set((vop), &(vop)->data->afbc->name, \
99 0, ~0, v, #name); \
100 } while (0)
101
102 #define to_vop(x) container_of(x, struct vop, crtc)
103 #define to_vop_win(x) container_of(x, struct vop_win, base)
104
105 #define AFBC_FMT_RGB565 0x0
106 #define AFBC_FMT_U8U8U8U8 0x5
107 #define AFBC_FMT_U8U8U8 0x4
108
109 #define AFBC_TILE_16x16 BIT(4)
110
111 /*
112 * The coefficients of the following matrix are all fixed points.
113 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets.
114 * They are all represented in two's complement.
115 */
116 static const uint32_t bt601_yuv2rgb[] = {
117 0x4A8, 0x0, 0x662,
118 0x4A8, 0x1E6F, 0x1CBF,
119 0x4A8, 0x812, 0x0,
120 0x321168, 0x0877CF, 0x2EB127
121 };
122
123 enum vop_pending {
124 VOP_PENDING_FB_UNREF,
125 };
126
127 struct vop_win {
128 struct drm_plane base;
129 const struct vop_win_data *data;
130 const struct vop_win_yuv2yuv_data *yuv2yuv_data;
131 struct vop *vop;
132 };
133
134 struct rockchip_rgb;
135 struct vop {
136 struct drm_crtc crtc;
137 struct device *dev;
138 struct drm_device *drm_dev;
139 bool is_enabled;
140
141 struct completion dsp_hold_completion;
142 unsigned int win_enabled;
143
144 /* protected by dev->event_lock */
145 struct drm_pending_vblank_event *event;
146
147 struct drm_flip_work fb_unref_work;
148 unsigned long pending;
149
150 struct completion line_flag_completion;
151
152 const struct vop_data *data;
153
154 uint32_t *regsbak;
155 void __iomem *regs;
156 void __iomem *lut_regs;
157
158 /* physical map length of vop register */
159 uint32_t len;
160
161 /* one time only one process allowed to config the register */
162 spinlock_t reg_lock;
163 /* lock vop irq reg */
164 spinlock_t irq_lock;
165 /* protects crtc enable/disable */
166 struct mutex vop_lock;
167
168 unsigned int irq;
169
170 /* vop AHP clk */
171 struct clk *hclk;
172 /* vop dclk */
173 struct clk *dclk;
174 /* vop share memory frequency */
175 struct clk *aclk;
176
177 /* vop dclk reset */
178 struct reset_control *dclk_rst;
179
180 /* optional internal rgb encoder */
181 struct rockchip_rgb *rgb;
182
183 struct vop_win win[];
184 };
185
vop_writel(struct vop * vop,uint32_t offset,uint32_t v)186 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
187 {
188 writel(v, vop->regs + offset);
189 vop->regsbak[offset >> 2] = v;
190 }
191
vop_readl(struct vop * vop,uint32_t offset)192 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
193 {
194 return readl(vop->regs + offset);
195 }
196
vop_read_reg(struct vop * vop,uint32_t base,const struct vop_reg * reg)197 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
198 const struct vop_reg *reg)
199 {
200 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
201 }
202
vop_reg_set(struct vop * vop,const struct vop_reg * reg,uint32_t _offset,uint32_t _mask,uint32_t v,const char * reg_name)203 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
204 uint32_t _offset, uint32_t _mask, uint32_t v,
205 const char *reg_name)
206 {
207 int offset, mask, shift;
208
209 if (!reg || !reg->mask) {
210 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
211 return;
212 }
213
214 offset = reg->offset + _offset;
215 mask = reg->mask & _mask;
216 shift = reg->shift;
217
218 if (reg->write_mask) {
219 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
220 } else {
221 uint32_t cached_val = vop->regsbak[offset >> 2];
222
223 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
224 vop->regsbak[offset >> 2] = v;
225 }
226
227 if (reg->relaxed)
228 writel_relaxed(v, vop->regs + offset);
229 else
230 writel(v, vop->regs + offset);
231 }
232
vop_get_intr_type(struct vop * vop,const struct vop_reg * reg,int type)233 static inline uint32_t vop_get_intr_type(struct vop *vop,
234 const struct vop_reg *reg, int type)
235 {
236 uint32_t i, ret = 0;
237 uint32_t regs = vop_read_reg(vop, 0, reg);
238
239 for (i = 0; i < vop->data->intr->nintrs; i++) {
240 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
241 ret |= vop->data->intr->intrs[i];
242 }
243
244 return ret;
245 }
246
vop_cfg_done(struct vop * vop)247 static inline void vop_cfg_done(struct vop *vop)
248 {
249 VOP_REG_SET(vop, common, cfg_done, 1);
250 }
251
has_rb_swapped(uint32_t format)252 static bool has_rb_swapped(uint32_t format)
253 {
254 switch (format) {
255 case DRM_FORMAT_XBGR8888:
256 case DRM_FORMAT_ABGR8888:
257 case DRM_FORMAT_BGR888:
258 case DRM_FORMAT_BGR565:
259 return true;
260 default:
261 return false;
262 }
263 }
264
vop_convert_format(uint32_t format)265 static enum vop_data_format vop_convert_format(uint32_t format)
266 {
267 switch (format) {
268 case DRM_FORMAT_XRGB8888:
269 case DRM_FORMAT_ARGB8888:
270 case DRM_FORMAT_XBGR8888:
271 case DRM_FORMAT_ABGR8888:
272 return VOP_FMT_ARGB8888;
273 case DRM_FORMAT_RGB888:
274 case DRM_FORMAT_BGR888:
275 return VOP_FMT_RGB888;
276 case DRM_FORMAT_RGB565:
277 case DRM_FORMAT_BGR565:
278 return VOP_FMT_RGB565;
279 case DRM_FORMAT_NV12:
280 return VOP_FMT_YUV420SP;
281 case DRM_FORMAT_NV16:
282 return VOP_FMT_YUV422SP;
283 case DRM_FORMAT_NV24:
284 return VOP_FMT_YUV444SP;
285 default:
286 DRM_ERROR("unsupported format[%08x]\n", format);
287 return -EINVAL;
288 }
289 }
290
vop_convert_afbc_format(uint32_t format)291 static int vop_convert_afbc_format(uint32_t format)
292 {
293 switch (format) {
294 case DRM_FORMAT_XRGB8888:
295 case DRM_FORMAT_ARGB8888:
296 case DRM_FORMAT_XBGR8888:
297 case DRM_FORMAT_ABGR8888:
298 return AFBC_FMT_U8U8U8U8;
299 case DRM_FORMAT_RGB888:
300 case DRM_FORMAT_BGR888:
301 return AFBC_FMT_U8U8U8;
302 case DRM_FORMAT_RGB565:
303 case DRM_FORMAT_BGR565:
304 return AFBC_FMT_RGB565;
305 /* either of the below should not be reachable */
306 default:
307 DRM_WARN_ONCE("unsupported AFBC format[%08x]\n", format);
308 return -EINVAL;
309 }
310
311 return -EINVAL;
312 }
313
scl_vop_cal_scale(enum scale_mode mode,uint32_t src,uint32_t dst,bool is_horizontal,int vsu_mode,int * vskiplines)314 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
315 uint32_t dst, bool is_horizontal,
316 int vsu_mode, int *vskiplines)
317 {
318 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
319
320 if (vskiplines)
321 *vskiplines = 0;
322
323 if (is_horizontal) {
324 if (mode == SCALE_UP)
325 val = GET_SCL_FT_BIC(src, dst);
326 else if (mode == SCALE_DOWN)
327 val = GET_SCL_FT_BILI_DN(src, dst);
328 } else {
329 if (mode == SCALE_UP) {
330 if (vsu_mode == SCALE_UP_BIL)
331 val = GET_SCL_FT_BILI_UP(src, dst);
332 else
333 val = GET_SCL_FT_BIC(src, dst);
334 } else if (mode == SCALE_DOWN) {
335 if (vskiplines) {
336 *vskiplines = scl_get_vskiplines(src, dst);
337 val = scl_get_bili_dn_vskip(src, dst,
338 *vskiplines);
339 } else {
340 val = GET_SCL_FT_BILI_DN(src, dst);
341 }
342 }
343 }
344
345 return val;
346 }
347
scl_vop_cal_scl_fac(struct vop * vop,const struct vop_win_data * win,uint32_t src_w,uint32_t src_h,uint32_t dst_w,uint32_t dst_h,const struct drm_format_info * info)348 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
349 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
350 uint32_t dst_h, const struct drm_format_info *info)
351 {
352 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
353 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
354 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
355 bool is_yuv = false;
356 uint16_t cbcr_src_w = src_w / info->hsub;
357 uint16_t cbcr_src_h = src_h / info->vsub;
358 uint16_t vsu_mode;
359 uint16_t lb_mode;
360 uint32_t val;
361 int vskiplines;
362
363 if (info->is_yuv)
364 is_yuv = true;
365
366 if (dst_w > 3840) {
367 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
368 return;
369 }
370
371 if (!win->phy->scl->ext) {
372 VOP_SCL_SET(vop, win, scale_yrgb_x,
373 scl_cal_scale2(src_w, dst_w));
374 VOP_SCL_SET(vop, win, scale_yrgb_y,
375 scl_cal_scale2(src_h, dst_h));
376 if (is_yuv) {
377 VOP_SCL_SET(vop, win, scale_cbcr_x,
378 scl_cal_scale2(cbcr_src_w, dst_w));
379 VOP_SCL_SET(vop, win, scale_cbcr_y,
380 scl_cal_scale2(cbcr_src_h, dst_h));
381 }
382 return;
383 }
384
385 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
386 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
387
388 if (is_yuv) {
389 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
390 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
391 if (cbcr_hor_scl_mode == SCALE_DOWN)
392 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
393 else
394 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
395 } else {
396 if (yrgb_hor_scl_mode == SCALE_DOWN)
397 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
398 else
399 lb_mode = scl_vop_cal_lb_mode(src_w, false);
400 }
401
402 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
403 if (lb_mode == LB_RGB_3840X2) {
404 if (yrgb_ver_scl_mode != SCALE_NONE) {
405 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
406 return;
407 }
408 if (cbcr_ver_scl_mode != SCALE_NONE) {
409 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
410 return;
411 }
412 vsu_mode = SCALE_UP_BIL;
413 } else if (lb_mode == LB_RGB_2560X4) {
414 vsu_mode = SCALE_UP_BIL;
415 } else {
416 vsu_mode = SCALE_UP_BIC;
417 }
418
419 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
420 true, 0, NULL);
421 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
422 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
423 false, vsu_mode, &vskiplines);
424 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
425
426 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
427 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
428
429 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
430 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
431 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
432 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
433 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
434 if (is_yuv) {
435 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
436 dst_w, true, 0, NULL);
437 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
438 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
439 dst_h, false, vsu_mode, &vskiplines);
440 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
441
442 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
443 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
444 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
445 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
446 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
447 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
448 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
449 }
450 }
451
vop_dsp_hold_valid_irq_enable(struct vop * vop)452 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
453 {
454 unsigned long flags;
455
456 if (WARN_ON(!vop->is_enabled))
457 return;
458
459 spin_lock_irqsave(&vop->irq_lock, flags);
460
461 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
462 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
463
464 spin_unlock_irqrestore(&vop->irq_lock, flags);
465 }
466
vop_dsp_hold_valid_irq_disable(struct vop * vop)467 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
468 {
469 unsigned long flags;
470
471 if (WARN_ON(!vop->is_enabled))
472 return;
473
474 spin_lock_irqsave(&vop->irq_lock, flags);
475
476 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
477
478 spin_unlock_irqrestore(&vop->irq_lock, flags);
479 }
480
481 /*
482 * (1) each frame starts at the start of the Vsync pulse which is signaled by
483 * the "FRAME_SYNC" interrupt.
484 * (2) the active data region of each frame ends at dsp_vact_end
485 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
486 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
487 *
488 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
489 * Interrupts
490 * LINE_FLAG -------------------------------+
491 * FRAME_SYNC ----+ |
492 * | |
493 * v v
494 * | Vsync | Vbp | Vactive | Vfp |
495 * ^ ^ ^ ^
496 * | | | |
497 * | | | |
498 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
499 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
500 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
501 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
502 */
vop_line_flag_irq_is_enabled(struct vop * vop)503 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
504 {
505 uint32_t line_flag_irq;
506 unsigned long flags;
507
508 spin_lock_irqsave(&vop->irq_lock, flags);
509
510 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
511
512 spin_unlock_irqrestore(&vop->irq_lock, flags);
513
514 return !!line_flag_irq;
515 }
516
vop_line_flag_irq_enable(struct vop * vop)517 static void vop_line_flag_irq_enable(struct vop *vop)
518 {
519 unsigned long flags;
520
521 if (WARN_ON(!vop->is_enabled))
522 return;
523
524 spin_lock_irqsave(&vop->irq_lock, flags);
525
526 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
527 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
528
529 spin_unlock_irqrestore(&vop->irq_lock, flags);
530 }
531
vop_line_flag_irq_disable(struct vop * vop)532 static void vop_line_flag_irq_disable(struct vop *vop)
533 {
534 unsigned long flags;
535
536 if (WARN_ON(!vop->is_enabled))
537 return;
538
539 spin_lock_irqsave(&vop->irq_lock, flags);
540
541 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
542
543 spin_unlock_irqrestore(&vop->irq_lock, flags);
544 }
545
vop_core_clks_enable(struct vop * vop)546 static int vop_core_clks_enable(struct vop *vop)
547 {
548 int ret;
549
550 ret = clk_enable(vop->hclk);
551 if (ret < 0)
552 return ret;
553
554 ret = clk_enable(vop->aclk);
555 if (ret < 0)
556 goto err_disable_hclk;
557
558 return 0;
559
560 err_disable_hclk:
561 clk_disable(vop->hclk);
562 return ret;
563 }
564
vop_core_clks_disable(struct vop * vop)565 static void vop_core_clks_disable(struct vop *vop)
566 {
567 clk_disable(vop->aclk);
568 clk_disable(vop->hclk);
569 }
570
vop_win_disable(struct vop * vop,const struct vop_win * vop_win)571 static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win)
572 {
573 const struct vop_win_data *win = vop_win->data;
574
575 if (win->phy->scl && win->phy->scl->ext) {
576 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
577 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
578 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
579 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
580 }
581
582 VOP_WIN_SET(vop, win, enable, 0);
583 vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win));
584 }
585
vop_enable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)586 static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
587 {
588 struct vop *vop = to_vop(crtc);
589 int ret, i;
590
591 ret = pm_runtime_get_sync(vop->dev);
592 if (ret < 0) {
593 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
594 return ret;
595 }
596
597 ret = vop_core_clks_enable(vop);
598 if (WARN_ON(ret < 0))
599 goto err_put_pm_runtime;
600
601 ret = clk_enable(vop->dclk);
602 if (WARN_ON(ret < 0))
603 goto err_disable_core;
604
605 /*
606 * Slave iommu shares power, irq and clock with vop. It was associated
607 * automatically with this master device via common driver code.
608 * Now that we have enabled the clock we attach it to the shared drm
609 * mapping.
610 */
611 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
612 if (ret) {
613 DRM_DEV_ERROR(vop->dev,
614 "failed to attach dma mapping, %d\n", ret);
615 goto err_disable_dclk;
616 }
617
618 spin_lock(&vop->reg_lock);
619 for (i = 0; i < vop->len; i += 4)
620 writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
621
622 /*
623 * We need to make sure that all windows are disabled before we
624 * enable the crtc. Otherwise we might try to scan from a destroyed
625 * buffer later.
626 *
627 * In the case of enable-after-PSR, we don't need to worry about this
628 * case since the buffer is guaranteed to be valid and disabling the
629 * window will result in screen glitches on PSR exit.
630 */
631 if (!old_state || !old_state->self_refresh_active) {
632 for (i = 0; i < vop->data->win_size; i++) {
633 struct vop_win *vop_win = &vop->win[i];
634
635 vop_win_disable(vop, vop_win);
636 }
637 }
638
639 if (vop->data->afbc) {
640 struct rockchip_crtc_state *s;
641 /*
642 * Disable AFBC and forget there was a vop window with AFBC
643 */
644 VOP_AFBC_SET(vop, enable, 0);
645 s = to_rockchip_crtc_state(crtc->state);
646 s->enable_afbc = false;
647 }
648
649 vop_cfg_done(vop);
650
651 spin_unlock(&vop->reg_lock);
652
653 /*
654 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
655 */
656 vop->is_enabled = true;
657
658 spin_lock(&vop->reg_lock);
659
660 VOP_REG_SET(vop, common, standby, 1);
661
662 spin_unlock(&vop->reg_lock);
663
664 drm_crtc_vblank_on(crtc);
665
666 return 0;
667
668 err_disable_dclk:
669 clk_disable(vop->dclk);
670 err_disable_core:
671 vop_core_clks_disable(vop);
672 err_put_pm_runtime:
673 pm_runtime_put_sync(vop->dev);
674 return ret;
675 }
676
rockchip_drm_set_win_enabled(struct drm_crtc * crtc,bool enabled)677 static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled)
678 {
679 struct vop *vop = to_vop(crtc);
680 int i;
681
682 spin_lock(&vop->reg_lock);
683
684 for (i = 0; i < vop->data->win_size; i++) {
685 struct vop_win *vop_win = &vop->win[i];
686 const struct vop_win_data *win = vop_win->data;
687
688 VOP_WIN_SET(vop, win, enable,
689 enabled && (vop->win_enabled & BIT(i)));
690 }
691 vop_cfg_done(vop);
692
693 spin_unlock(&vop->reg_lock);
694 }
695
vop_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)696 static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
697 struct drm_atomic_state *state)
698 {
699 struct vop *vop = to_vop(crtc);
700
701 WARN_ON(vop->event);
702
703 if (crtc->state->self_refresh_active)
704 rockchip_drm_set_win_enabled(crtc, false);
705
706 mutex_lock(&vop->vop_lock);
707
708 drm_crtc_vblank_off(crtc);
709
710 if (crtc->state->self_refresh_active)
711 goto out;
712
713 /*
714 * Vop standby will take effect at end of current frame,
715 * if dsp hold valid irq happen, it means standby complete.
716 *
717 * we must wait standby complete when we want to disable aclk,
718 * if not, memory bus maybe dead.
719 */
720 reinit_completion(&vop->dsp_hold_completion);
721 vop_dsp_hold_valid_irq_enable(vop);
722
723 spin_lock(&vop->reg_lock);
724
725 VOP_REG_SET(vop, common, standby, 1);
726
727 spin_unlock(&vop->reg_lock);
728
729 wait_for_completion(&vop->dsp_hold_completion);
730
731 vop_dsp_hold_valid_irq_disable(vop);
732
733 vop->is_enabled = false;
734
735 /*
736 * vop standby complete, so iommu detach is safe.
737 */
738 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
739
740 clk_disable(vop->dclk);
741 vop_core_clks_disable(vop);
742 pm_runtime_put(vop->dev);
743
744 out:
745 mutex_unlock(&vop->vop_lock);
746
747 if (crtc->state->event && !crtc->state->active) {
748 spin_lock_irq(&crtc->dev->event_lock);
749 drm_crtc_send_vblank_event(crtc, crtc->state->event);
750 spin_unlock_irq(&crtc->dev->event_lock);
751
752 crtc->state->event = NULL;
753 }
754 }
755
vop_plane_destroy(struct drm_plane * plane)756 static void vop_plane_destroy(struct drm_plane *plane)
757 {
758 drm_plane_cleanup(plane);
759 }
760
rockchip_afbc(u64 modifier)761 static inline bool rockchip_afbc(u64 modifier)
762 {
763 return modifier == ROCKCHIP_AFBC_MOD;
764 }
765
rockchip_mod_supported(struct drm_plane * plane,u32 format,u64 modifier)766 static bool rockchip_mod_supported(struct drm_plane *plane,
767 u32 format, u64 modifier)
768 {
769 if (modifier == DRM_FORMAT_MOD_LINEAR)
770 return true;
771
772 if (!rockchip_afbc(modifier)) {
773 DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier);
774
775 return false;
776 }
777
778 return vop_convert_afbc_format(format) >= 0;
779 }
780
vop_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)781 static int vop_plane_atomic_check(struct drm_plane *plane,
782 struct drm_atomic_state *state)
783 {
784 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
785 plane);
786 struct drm_crtc *crtc = new_plane_state->crtc;
787 struct drm_crtc_state *crtc_state;
788 struct drm_framebuffer *fb = new_plane_state->fb;
789 struct vop_win *vop_win = to_vop_win(plane);
790 const struct vop_win_data *win = vop_win->data;
791 int ret;
792 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
793 DRM_PLANE_HELPER_NO_SCALING;
794 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
795 DRM_PLANE_HELPER_NO_SCALING;
796
797 if (!crtc || WARN_ON(!fb))
798 return 0;
799
800 crtc_state = drm_atomic_get_existing_crtc_state(state,
801 crtc);
802 if (WARN_ON(!crtc_state))
803 return -EINVAL;
804
805 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
806 min_scale, max_scale,
807 true, true);
808 if (ret)
809 return ret;
810
811 if (!new_plane_state->visible)
812 return 0;
813
814 ret = vop_convert_format(fb->format->format);
815 if (ret < 0)
816 return ret;
817
818 /*
819 * Src.x1 can be odd when do clip, but yuv plane start point
820 * need align with 2 pixel.
821 */
822 if (fb->format->is_yuv && ((new_plane_state->src.x1 >> 16) % 2)) {
823 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
824 return -EINVAL;
825 }
826
827 if (fb->format->is_yuv && new_plane_state->rotation & DRM_MODE_REFLECT_Y) {
828 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n");
829 return -EINVAL;
830 }
831
832 if (rockchip_afbc(fb->modifier)) {
833 struct vop *vop = to_vop(crtc);
834
835 if (!vop->data->afbc) {
836 DRM_ERROR("vop does not support AFBC\n");
837 return -EINVAL;
838 }
839
840 ret = vop_convert_afbc_format(fb->format->format);
841 if (ret < 0)
842 return ret;
843
844 if (new_plane_state->src.x1 || new_plane_state->src.y1) {
845 DRM_ERROR("AFBC does not support offset display, xpos=%d, ypos=%d, offset=%d\n",
846 new_plane_state->src.x1,
847 new_plane_state->src.y1, fb->offsets[0]);
848 return -EINVAL;
849 }
850
851 if (new_plane_state->rotation && new_plane_state->rotation != DRM_MODE_ROTATE_0) {
852 DRM_ERROR("No rotation support in AFBC, rotation=%d\n",
853 new_plane_state->rotation);
854 return -EINVAL;
855 }
856 }
857
858 return 0;
859 }
860
vop_plane_atomic_disable(struct drm_plane * plane,struct drm_atomic_state * state)861 static void vop_plane_atomic_disable(struct drm_plane *plane,
862 struct drm_atomic_state *state)
863 {
864 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
865 plane);
866 struct vop_win *vop_win = to_vop_win(plane);
867 struct vop *vop = to_vop(old_state->crtc);
868
869 if (!old_state->crtc)
870 return;
871
872 spin_lock(&vop->reg_lock);
873
874 vop_win_disable(vop, vop_win);
875
876 spin_unlock(&vop->reg_lock);
877 }
878
vop_plane_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)879 static void vop_plane_atomic_update(struct drm_plane *plane,
880 struct drm_atomic_state *state)
881 {
882 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
883 plane);
884 struct drm_crtc *crtc = new_state->crtc;
885 struct vop_win *vop_win = to_vop_win(plane);
886 const struct vop_win_data *win = vop_win->data;
887 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data;
888 struct vop *vop = to_vop(new_state->crtc);
889 struct drm_framebuffer *fb = new_state->fb;
890 unsigned int actual_w, actual_h;
891 unsigned int dsp_stx, dsp_sty;
892 uint32_t act_info, dsp_info, dsp_st;
893 struct drm_rect *src = &new_state->src;
894 struct drm_rect *dest = &new_state->dst;
895 struct drm_gem_object *obj, *uv_obj;
896 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
897 unsigned long offset;
898 dma_addr_t dma_addr;
899 uint32_t val;
900 bool rb_swap;
901 int win_index = VOP_WIN_TO_INDEX(vop_win);
902 int format;
903 int is_yuv = fb->format->is_yuv;
904 int i;
905
906 /*
907 * can't update plane when vop is disabled.
908 */
909 if (WARN_ON(!crtc))
910 return;
911
912 if (WARN_ON(!vop->is_enabled))
913 return;
914
915 if (!new_state->visible) {
916 vop_plane_atomic_disable(plane, state);
917 return;
918 }
919
920 obj = fb->obj[0];
921 rk_obj = to_rockchip_obj(obj);
922
923 actual_w = drm_rect_width(src) >> 16;
924 actual_h = drm_rect_height(src) >> 16;
925 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
926
927 dsp_info = (drm_rect_height(dest) - 1) << 16;
928 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
929
930 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
931 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
932 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
933
934 offset = (src->x1 >> 16) * fb->format->cpp[0];
935 offset += (src->y1 >> 16) * fb->pitches[0];
936 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
937
938 /*
939 * For y-mirroring we need to move address
940 * to the beginning of the last line.
941 */
942 if (new_state->rotation & DRM_MODE_REFLECT_Y)
943 dma_addr += (actual_h - 1) * fb->pitches[0];
944
945 format = vop_convert_format(fb->format->format);
946
947 spin_lock(&vop->reg_lock);
948
949 if (rockchip_afbc(fb->modifier)) {
950 int afbc_format = vop_convert_afbc_format(fb->format->format);
951
952 VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16);
953 VOP_AFBC_SET(vop, hreg_block_split, 0);
954 VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win));
955 VOP_AFBC_SET(vop, hdr_ptr, dma_addr);
956 VOP_AFBC_SET(vop, pic_size, act_info);
957 }
958
959 VOP_WIN_SET(vop, win, format, format);
960 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
961 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
962 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
963 VOP_WIN_SET(vop, win, y_mir_en,
964 (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0);
965 VOP_WIN_SET(vop, win, x_mir_en,
966 (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
967
968 if (is_yuv) {
969 int hsub = fb->format->hsub;
970 int vsub = fb->format->vsub;
971 int bpp = fb->format->cpp[1];
972
973 uv_obj = fb->obj[1];
974 rk_uv_obj = to_rockchip_obj(uv_obj);
975
976 offset = (src->x1 >> 16) * bpp / hsub;
977 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
978
979 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
980 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
981 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
982
983 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
984 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,
985 win_yuv2yuv,
986 y2r_coefficients[i],
987 bt601_yuv2rgb[i]);
988 }
989 }
990
991 if (win->phy->scl)
992 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
993 drm_rect_width(dest), drm_rect_height(dest),
994 fb->format);
995
996 VOP_WIN_SET(vop, win, act_info, act_info);
997 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
998 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
999
1000 rb_swap = has_rb_swapped(fb->format->format);
1001 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1002
1003 /*
1004 * Blending win0 with the background color doesn't seem to work
1005 * correctly. We only get the background color, no matter the contents
1006 * of the win0 framebuffer. However, blending pre-multiplied color
1007 * with the default opaque black default background color is a no-op,
1008 * so we can just disable blending to get the correct result.
1009 */
1010 if (fb->format->has_alpha && win_index > 0) {
1011 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1012 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1013 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1014 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1015 SRC_BLEND_M0(ALPHA_PER_PIX) |
1016 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1017 SRC_FACTOR_M0(ALPHA_ONE);
1018 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1019
1020 VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL);
1021 VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX);
1022 VOP_WIN_SET(vop, win, alpha_en, 1);
1023 } else {
1024 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1025 VOP_WIN_SET(vop, win, alpha_en, 0);
1026 }
1027
1028 VOP_WIN_SET(vop, win, enable, 1);
1029 vop->win_enabled |= BIT(win_index);
1030 spin_unlock(&vop->reg_lock);
1031 }
1032
vop_plane_atomic_async_check(struct drm_plane * plane,struct drm_atomic_state * state)1033 static int vop_plane_atomic_async_check(struct drm_plane *plane,
1034 struct drm_atomic_state *state)
1035 {
1036 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
1037 plane);
1038 struct vop_win *vop_win = to_vop_win(plane);
1039 const struct vop_win_data *win = vop_win->data;
1040 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
1041 DRM_PLANE_HELPER_NO_SCALING;
1042 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
1043 DRM_PLANE_HELPER_NO_SCALING;
1044 struct drm_crtc_state *crtc_state;
1045
1046 if (plane != new_plane_state->crtc->cursor)
1047 return -EINVAL;
1048
1049 if (!plane->state)
1050 return -EINVAL;
1051
1052 if (!plane->state->fb)
1053 return -EINVAL;
1054
1055 if (state)
1056 crtc_state = drm_atomic_get_existing_crtc_state(state,
1057 new_plane_state->crtc);
1058 else /* Special case for asynchronous cursor updates. */
1059 crtc_state = plane->crtc->state;
1060
1061 return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
1062 min_scale, max_scale,
1063 true, true);
1064 }
1065
vop_plane_atomic_async_update(struct drm_plane * plane,struct drm_atomic_state * state)1066 static void vop_plane_atomic_async_update(struct drm_plane *plane,
1067 struct drm_atomic_state *state)
1068 {
1069 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
1070 plane);
1071 struct vop *vop = to_vop(plane->state->crtc);
1072 struct drm_framebuffer *old_fb = plane->state->fb;
1073
1074 plane->state->crtc_x = new_state->crtc_x;
1075 plane->state->crtc_y = new_state->crtc_y;
1076 plane->state->crtc_h = new_state->crtc_h;
1077 plane->state->crtc_w = new_state->crtc_w;
1078 plane->state->src_x = new_state->src_x;
1079 plane->state->src_y = new_state->src_y;
1080 plane->state->src_h = new_state->src_h;
1081 plane->state->src_w = new_state->src_w;
1082 swap(plane->state->fb, new_state->fb);
1083
1084 if (vop->is_enabled) {
1085 vop_plane_atomic_update(plane, state);
1086 spin_lock(&vop->reg_lock);
1087 vop_cfg_done(vop);
1088 spin_unlock(&vop->reg_lock);
1089
1090 /*
1091 * A scanout can still be occurring, so we can't drop the
1092 * reference to the old framebuffer. To solve this we get a
1093 * reference to old_fb and set a worker to release it later.
1094 * FIXME: if we perform 500 async_update calls before the
1095 * vblank, then we can have 500 different framebuffers waiting
1096 * to be released.
1097 */
1098 if (old_fb && plane->state->fb != old_fb) {
1099 drm_framebuffer_get(old_fb);
1100 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
1101 drm_flip_work_queue(&vop->fb_unref_work, old_fb);
1102 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1103 }
1104 }
1105 }
1106
1107 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1108 .atomic_check = vop_plane_atomic_check,
1109 .atomic_update = vop_plane_atomic_update,
1110 .atomic_disable = vop_plane_atomic_disable,
1111 .atomic_async_check = vop_plane_atomic_async_check,
1112 .atomic_async_update = vop_plane_atomic_async_update,
1113 };
1114
1115 static const struct drm_plane_funcs vop_plane_funcs = {
1116 .update_plane = drm_atomic_helper_update_plane,
1117 .disable_plane = drm_atomic_helper_disable_plane,
1118 .destroy = vop_plane_destroy,
1119 .reset = drm_atomic_helper_plane_reset,
1120 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1121 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1122 .format_mod_supported = rockchip_mod_supported,
1123 };
1124
vop_crtc_enable_vblank(struct drm_crtc * crtc)1125 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1126 {
1127 struct vop *vop = to_vop(crtc);
1128 unsigned long flags;
1129
1130 if (WARN_ON(!vop->is_enabled))
1131 return -EPERM;
1132
1133 spin_lock_irqsave(&vop->irq_lock, flags);
1134
1135 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1136 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1137
1138 spin_unlock_irqrestore(&vop->irq_lock, flags);
1139
1140 return 0;
1141 }
1142
vop_crtc_disable_vblank(struct drm_crtc * crtc)1143 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1144 {
1145 struct vop *vop = to_vop(crtc);
1146 unsigned long flags;
1147
1148 if (WARN_ON(!vop->is_enabled))
1149 return;
1150
1151 spin_lock_irqsave(&vop->irq_lock, flags);
1152
1153 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1154
1155 spin_unlock_irqrestore(&vop->irq_lock, flags);
1156 }
1157
vop_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1158 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1159 const struct drm_display_mode *mode,
1160 struct drm_display_mode *adjusted_mode)
1161 {
1162 struct vop *vop = to_vop(crtc);
1163 unsigned long rate;
1164
1165 /*
1166 * Clock craziness.
1167 *
1168 * Key points:
1169 *
1170 * - DRM works in in kHz.
1171 * - Clock framework works in Hz.
1172 * - Rockchip's clock driver picks the clock rate that is the
1173 * same _OR LOWER_ than the one requested.
1174 *
1175 * Action plan:
1176 *
1177 * 1. Try to set the exact rate first, and confirm the clock framework
1178 * can provide it.
1179 *
1180 * 2. If the clock framework cannot provide the exact rate, we should
1181 * add 999 Hz to the requested rate. That way if the clock we need
1182 * is 60000001 Hz (~60 MHz) and DRM tells us to make 60000 kHz then
1183 * the clock framework will actually give us the right clock.
1184 *
1185 * 3. Get the clock framework to round the rate for us to tell us
1186 * what it will actually make.
1187 *
1188 * 4. Store the rounded up rate so that we don't need to worry about
1189 * this in the actual clk_set_rate().
1190 */
1191 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000);
1192 if (rate / 1000 != adjusted_mode->clock)
1193 rate = clk_round_rate(vop->dclk,
1194 adjusted_mode->clock * 1000 + 999);
1195 adjusted_mode->clock = DIV_ROUND_UP(rate, 1000);
1196
1197 return true;
1198 }
1199
vop_dsp_lut_is_enabled(struct vop * vop)1200 static bool vop_dsp_lut_is_enabled(struct vop *vop)
1201 {
1202 return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en);
1203 }
1204
vop_crtc_write_gamma_lut(struct vop * vop,struct drm_crtc * crtc)1205 static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc)
1206 {
1207 struct drm_color_lut *lut = crtc->state->gamma_lut->data;
1208 unsigned int i;
1209
1210 for (i = 0; i < crtc->gamma_size; i++) {
1211 u32 word;
1212
1213 word = (drm_color_lut_extract(lut[i].red, 10) << 20) |
1214 (drm_color_lut_extract(lut[i].green, 10) << 10) |
1215 drm_color_lut_extract(lut[i].blue, 10);
1216 writel(word, vop->lut_regs + i * 4);
1217 }
1218 }
1219
vop_crtc_gamma_set(struct vop * vop,struct drm_crtc * crtc,struct drm_crtc_state * old_state)1220 static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc,
1221 struct drm_crtc_state *old_state)
1222 {
1223 struct drm_crtc_state *state = crtc->state;
1224 unsigned int idle;
1225 int ret;
1226
1227 if (!vop->lut_regs)
1228 return;
1229 /*
1230 * To disable gamma (gamma_lut is null) or to write
1231 * an update to the LUT, clear dsp_lut_en.
1232 */
1233 spin_lock(&vop->reg_lock);
1234 VOP_REG_SET(vop, common, dsp_lut_en, 0);
1235 vop_cfg_done(vop);
1236 spin_unlock(&vop->reg_lock);
1237
1238 /*
1239 * In order to write the LUT to the internal memory,
1240 * we need to first make sure the dsp_lut_en bit is cleared.
1241 */
1242 ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop,
1243 idle, !idle, 5, 30 * 1000);
1244 if (ret) {
1245 DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n");
1246 return;
1247 }
1248
1249 if (!state->gamma_lut)
1250 return;
1251
1252 spin_lock(&vop->reg_lock);
1253 vop_crtc_write_gamma_lut(vop, crtc);
1254 VOP_REG_SET(vop, common, dsp_lut_en, 1);
1255 vop_cfg_done(vop);
1256 spin_unlock(&vop->reg_lock);
1257 }
1258
vop_crtc_atomic_begin(struct drm_crtc * crtc,struct drm_atomic_state * state)1259 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1260 struct drm_atomic_state *state)
1261 {
1262 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1263 crtc);
1264 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1265 crtc);
1266 struct vop *vop = to_vop(crtc);
1267
1268 /*
1269 * Only update GAMMA if the 'active' flag is not changed,
1270 * otherwise it's updated by .atomic_enable.
1271 */
1272 if (crtc_state->color_mgmt_changed &&
1273 !crtc_state->active_changed)
1274 vop_crtc_gamma_set(vop, crtc, old_crtc_state);
1275 }
1276
vop_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)1277 static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
1278 struct drm_atomic_state *state)
1279 {
1280 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
1281 crtc);
1282 struct vop *vop = to_vop(crtc);
1283 const struct vop_data *vop_data = vop->data;
1284 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1285 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1286 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1287 u16 hdisplay = adjusted_mode->hdisplay;
1288 u16 htotal = adjusted_mode->htotal;
1289 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1290 u16 hact_end = hact_st + hdisplay;
1291 u16 vdisplay = adjusted_mode->vdisplay;
1292 u16 vtotal = adjusted_mode->vtotal;
1293 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1294 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1295 u16 vact_end = vact_st + vdisplay;
1296 uint32_t pin_pol, val;
1297 int dither_bpc = s->output_bpc ? s->output_bpc : 10;
1298 int ret;
1299
1300 if (old_state && old_state->self_refresh_active) {
1301 drm_crtc_vblank_on(crtc);
1302 rockchip_drm_set_win_enabled(crtc, true);
1303 return;
1304 }
1305
1306 /*
1307 * If we have a GAMMA LUT in the state, then let's make sure
1308 * it's updated. We might be coming out of suspend,
1309 * which means the LUT internal memory needs to be re-written.
1310 */
1311 if (crtc->state->gamma_lut)
1312 vop_crtc_gamma_set(vop, crtc, old_state);
1313
1314 mutex_lock(&vop->vop_lock);
1315
1316 WARN_ON(vop->event);
1317
1318 ret = vop_enable(crtc, old_state);
1319 if (ret) {
1320 mutex_unlock(&vop->vop_lock);
1321 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
1322 return;
1323 }
1324 pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
1325 BIT(HSYNC_POSITIVE) : 0;
1326 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
1327 BIT(VSYNC_POSITIVE) : 0;
1328 VOP_REG_SET(vop, output, pin_pol, pin_pol);
1329 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);
1330
1331 switch (s->output_type) {
1332 case DRM_MODE_CONNECTOR_LVDS:
1333 VOP_REG_SET(vop, output, rgb_dclk_pol, 1);
1334 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
1335 VOP_REG_SET(vop, output, rgb_en, 1);
1336 break;
1337 case DRM_MODE_CONNECTOR_eDP:
1338 VOP_REG_SET(vop, output, edp_dclk_pol, 1);
1339 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
1340 VOP_REG_SET(vop, output, edp_en, 1);
1341 break;
1342 case DRM_MODE_CONNECTOR_HDMIA:
1343 VOP_REG_SET(vop, output, hdmi_dclk_pol, 1);
1344 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
1345 VOP_REG_SET(vop, output, hdmi_en, 1);
1346 break;
1347 case DRM_MODE_CONNECTOR_DSI:
1348 VOP_REG_SET(vop, output, mipi_dclk_pol, 1);
1349 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
1350 VOP_REG_SET(vop, output, mipi_en, 1);
1351 VOP_REG_SET(vop, output, mipi_dual_channel_en,
1352 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL));
1353 break;
1354 case DRM_MODE_CONNECTOR_DisplayPort:
1355 VOP_REG_SET(vop, output, dp_dclk_pol, 0);
1356 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
1357 VOP_REG_SET(vop, output, dp_en, 1);
1358 break;
1359 default:
1360 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
1361 s->output_type);
1362 }
1363
1364 /*
1365 * if vop is not support RGB10 output, need force RGB10 to RGB888.
1366 */
1367 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1368 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
1369 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1370
1371 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8)
1372 VOP_REG_SET(vop, common, pre_dither_down, 1);
1373 else
1374 VOP_REG_SET(vop, common, pre_dither_down, 0);
1375
1376 if (dither_bpc == 6) {
1377 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO);
1378 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666);
1379 VOP_REG_SET(vop, common, dither_down_en, 1);
1380 } else {
1381 VOP_REG_SET(vop, common, dither_down_en, 0);
1382 }
1383
1384 VOP_REG_SET(vop, common, out_mode, s->output_mode);
1385
1386 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
1387 val = hact_st << 16;
1388 val |= hact_end;
1389 VOP_REG_SET(vop, modeset, hact_st_end, val);
1390 VOP_REG_SET(vop, modeset, hpost_st_end, val);
1391
1392 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
1393 val = vact_st << 16;
1394 val |= vact_end;
1395 VOP_REG_SET(vop, modeset, vact_st_end, val);
1396 VOP_REG_SET(vop, modeset, vpost_st_end, val);
1397
1398 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
1399
1400 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1401
1402 VOP_REG_SET(vop, common, standby, 0);
1403 mutex_unlock(&vop->vop_lock);
1404 }
1405
vop_fs_irq_is_pending(struct vop * vop)1406 static bool vop_fs_irq_is_pending(struct vop *vop)
1407 {
1408 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
1409 }
1410
vop_wait_for_irq_handler(struct vop * vop)1411 static void vop_wait_for_irq_handler(struct vop *vop)
1412 {
1413 bool pending;
1414 int ret;
1415
1416 /*
1417 * Spin until frame start interrupt status bit goes low, which means
1418 * that interrupt handler was invoked and cleared it. The timeout of
1419 * 10 msecs is really too long, but it is just a safety measure if
1420 * something goes really wrong. The wait will only happen in the very
1421 * unlikely case of a vblank happening exactly at the same time and
1422 * shouldn't exceed microseconds range.
1423 */
1424 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1425 !pending, 0, 10 * 1000);
1426 if (ret)
1427 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1428
1429 synchronize_irq(vop->irq);
1430 }
1431
vop_crtc_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)1432 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1433 struct drm_atomic_state *state)
1434 {
1435 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1436 crtc);
1437 struct vop *vop = to_vop(crtc);
1438 struct drm_plane *plane;
1439 struct drm_plane_state *plane_state;
1440 struct rockchip_crtc_state *s;
1441 int afbc_planes = 0;
1442
1443 if (vop->lut_regs && crtc_state->color_mgmt_changed &&
1444 crtc_state->gamma_lut) {
1445 unsigned int len;
1446
1447 len = drm_color_lut_size(crtc_state->gamma_lut);
1448 if (len != crtc->gamma_size) {
1449 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
1450 len, crtc->gamma_size);
1451 return -EINVAL;
1452 }
1453 }
1454
1455 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
1456 plane_state =
1457 drm_atomic_get_plane_state(crtc_state->state, plane);
1458 if (IS_ERR(plane_state)) {
1459 DRM_DEBUG_KMS("Cannot get plane state for plane %s\n",
1460 plane->name);
1461 return PTR_ERR(plane_state);
1462 }
1463
1464 if (drm_is_afbc(plane_state->fb->modifier))
1465 ++afbc_planes;
1466 }
1467
1468 if (afbc_planes > 1) {
1469 DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes);
1470 return -EINVAL;
1471 }
1472
1473 s = to_rockchip_crtc_state(crtc_state);
1474 s->enable_afbc = afbc_planes > 0;
1475
1476 return 0;
1477 }
1478
vop_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_atomic_state * state)1479 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1480 struct drm_atomic_state *state)
1481 {
1482 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1483 crtc);
1484 struct drm_atomic_state *old_state = old_crtc_state->state;
1485 struct drm_plane_state *old_plane_state, *new_plane_state;
1486 struct vop *vop = to_vop(crtc);
1487 struct drm_plane *plane;
1488 struct rockchip_crtc_state *s;
1489 int i;
1490
1491 if (WARN_ON(!vop->is_enabled))
1492 return;
1493
1494 spin_lock(&vop->reg_lock);
1495
1496 /* Enable AFBC if there is some AFBC window, disable otherwise. */
1497 s = to_rockchip_crtc_state(crtc->state);
1498 VOP_AFBC_SET(vop, enable, s->enable_afbc);
1499 vop_cfg_done(vop);
1500
1501 spin_unlock(&vop->reg_lock);
1502
1503 /*
1504 * There is a (rather unlikely) possiblity that a vblank interrupt
1505 * fired before we set the cfg_done bit. To avoid spuriously
1506 * signalling flip completion we need to wait for it to finish.
1507 */
1508 vop_wait_for_irq_handler(vop);
1509
1510 spin_lock_irq(&crtc->dev->event_lock);
1511 if (crtc->state->event) {
1512 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1513 WARN_ON(vop->event);
1514
1515 vop->event = crtc->state->event;
1516 crtc->state->event = NULL;
1517 }
1518 spin_unlock_irq(&crtc->dev->event_lock);
1519
1520 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
1521 new_plane_state, i) {
1522 if (!old_plane_state->fb)
1523 continue;
1524
1525 if (old_plane_state->fb == new_plane_state->fb)
1526 continue;
1527
1528 drm_framebuffer_get(old_plane_state->fb);
1529 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1530 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1531 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1532 }
1533 }
1534
1535 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1536 .mode_fixup = vop_crtc_mode_fixup,
1537 .atomic_check = vop_crtc_atomic_check,
1538 .atomic_begin = vop_crtc_atomic_begin,
1539 .atomic_flush = vop_crtc_atomic_flush,
1540 .atomic_enable = vop_crtc_atomic_enable,
1541 .atomic_disable = vop_crtc_atomic_disable,
1542 };
1543
vop_crtc_destroy(struct drm_crtc * crtc)1544 static void vop_crtc_destroy(struct drm_crtc *crtc)
1545 {
1546 drm_crtc_cleanup(crtc);
1547 }
1548
vop_crtc_duplicate_state(struct drm_crtc * crtc)1549 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1550 {
1551 struct rockchip_crtc_state *rockchip_state;
1552
1553 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1554 if (!rockchip_state)
1555 return NULL;
1556
1557 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1558 return &rockchip_state->base;
1559 }
1560
vop_crtc_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)1561 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1562 struct drm_crtc_state *state)
1563 {
1564 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1565
1566 __drm_atomic_helper_crtc_destroy_state(&s->base);
1567 kfree(s);
1568 }
1569
vop_crtc_reset(struct drm_crtc * crtc)1570 static void vop_crtc_reset(struct drm_crtc *crtc)
1571 {
1572 struct rockchip_crtc_state *crtc_state =
1573 kzalloc(sizeof(*crtc_state), GFP_KERNEL);
1574
1575 if (crtc->state)
1576 vop_crtc_destroy_state(crtc, crtc->state);
1577
1578 __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);
1579 }
1580
1581 #ifdef CONFIG_DRM_ANALOGIX_DP
vop_get_edp_connector(struct vop * vop)1582 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1583 {
1584 struct drm_connector *connector;
1585 struct drm_connector_list_iter conn_iter;
1586
1587 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1588 drm_for_each_connector_iter(connector, &conn_iter) {
1589 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1590 drm_connector_list_iter_end(&conn_iter);
1591 return connector;
1592 }
1593 }
1594 drm_connector_list_iter_end(&conn_iter);
1595
1596 return NULL;
1597 }
1598
vop_crtc_set_crc_source(struct drm_crtc * crtc,const char * source_name)1599 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1600 const char *source_name)
1601 {
1602 struct vop *vop = to_vop(crtc);
1603 struct drm_connector *connector;
1604 int ret;
1605
1606 connector = vop_get_edp_connector(vop);
1607 if (!connector)
1608 return -EINVAL;
1609
1610 if (source_name && strcmp(source_name, "auto") == 0)
1611 ret = analogix_dp_start_crc(connector);
1612 else if (!source_name)
1613 ret = analogix_dp_stop_crc(connector);
1614 else
1615 ret = -EINVAL;
1616
1617 return ret;
1618 }
1619
1620 static int
vop_crtc_verify_crc_source(struct drm_crtc * crtc,const char * source_name,size_t * values_cnt)1621 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1622 size_t *values_cnt)
1623 {
1624 if (source_name && strcmp(source_name, "auto") != 0)
1625 return -EINVAL;
1626
1627 *values_cnt = 3;
1628 return 0;
1629 }
1630
1631 #else
vop_crtc_set_crc_source(struct drm_crtc * crtc,const char * source_name)1632 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1633 const char *source_name)
1634 {
1635 return -ENODEV;
1636 }
1637
1638 static int
vop_crtc_verify_crc_source(struct drm_crtc * crtc,const char * source_name,size_t * values_cnt)1639 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1640 size_t *values_cnt)
1641 {
1642 return -ENODEV;
1643 }
1644 #endif
1645
1646 static const struct drm_crtc_funcs vop_crtc_funcs = {
1647 .set_config = drm_atomic_helper_set_config,
1648 .page_flip = drm_atomic_helper_page_flip,
1649 .destroy = vop_crtc_destroy,
1650 .reset = vop_crtc_reset,
1651 .atomic_duplicate_state = vop_crtc_duplicate_state,
1652 .atomic_destroy_state = vop_crtc_destroy_state,
1653 .enable_vblank = vop_crtc_enable_vblank,
1654 .disable_vblank = vop_crtc_disable_vblank,
1655 .set_crc_source = vop_crtc_set_crc_source,
1656 .verify_crc_source = vop_crtc_verify_crc_source,
1657 };
1658
vop_fb_unref_worker(struct drm_flip_work * work,void * val)1659 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1660 {
1661 struct vop *vop = container_of(work, struct vop, fb_unref_work);
1662 struct drm_framebuffer *fb = val;
1663
1664 drm_crtc_vblank_put(&vop->crtc);
1665 drm_framebuffer_put(fb);
1666 }
1667
vop_handle_vblank(struct vop * vop)1668 static void vop_handle_vblank(struct vop *vop)
1669 {
1670 struct drm_device *drm = vop->drm_dev;
1671 struct drm_crtc *crtc = &vop->crtc;
1672
1673 spin_lock(&drm->event_lock);
1674 if (vop->event) {
1675 drm_crtc_send_vblank_event(crtc, vop->event);
1676 drm_crtc_vblank_put(crtc);
1677 vop->event = NULL;
1678 }
1679 spin_unlock(&drm->event_lock);
1680
1681 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1682 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1683 }
1684
vop_isr(int irq,void * data)1685 static irqreturn_t vop_isr(int irq, void *data)
1686 {
1687 struct vop *vop = data;
1688 struct drm_crtc *crtc = &vop->crtc;
1689 uint32_t active_irqs;
1690 int ret = IRQ_NONE;
1691
1692 /*
1693 * The irq is shared with the iommu. If the runtime-pm state of the
1694 * vop-device is disabled the irq has to be targeted at the iommu.
1695 */
1696 if (!pm_runtime_get_if_in_use(vop->dev))
1697 return IRQ_NONE;
1698
1699 if (vop_core_clks_enable(vop)) {
1700 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n");
1701 goto out;
1702 }
1703
1704 /*
1705 * interrupt register has interrupt status, enable and clear bits, we
1706 * must hold irq_lock to avoid a race with enable/disable_vblank().
1707 */
1708 spin_lock(&vop->irq_lock);
1709
1710 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1711 /* Clear all active interrupt sources */
1712 if (active_irqs)
1713 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1714
1715 spin_unlock(&vop->irq_lock);
1716
1717 /* This is expected for vop iommu irqs, since the irq is shared */
1718 if (!active_irqs)
1719 goto out_disable;
1720
1721 if (active_irqs & DSP_HOLD_VALID_INTR) {
1722 complete(&vop->dsp_hold_completion);
1723 active_irqs &= ~DSP_HOLD_VALID_INTR;
1724 ret = IRQ_HANDLED;
1725 }
1726
1727 if (active_irqs & LINE_FLAG_INTR) {
1728 complete(&vop->line_flag_completion);
1729 active_irqs &= ~LINE_FLAG_INTR;
1730 ret = IRQ_HANDLED;
1731 }
1732
1733 if (active_irqs & FS_INTR) {
1734 drm_crtc_handle_vblank(crtc);
1735 vop_handle_vblank(vop);
1736 active_irqs &= ~FS_INTR;
1737 ret = IRQ_HANDLED;
1738 }
1739
1740 /* Unhandled irqs are spurious. */
1741 if (active_irqs)
1742 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1743 active_irqs);
1744
1745 out_disable:
1746 vop_core_clks_disable(vop);
1747 out:
1748 pm_runtime_put(vop->dev);
1749 return ret;
1750 }
1751
vop_plane_add_properties(struct drm_plane * plane,const struct vop_win_data * win_data)1752 static void vop_plane_add_properties(struct drm_plane *plane,
1753 const struct vop_win_data *win_data)
1754 {
1755 unsigned int flags = 0;
1756
1757 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0;
1758 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0;
1759 if (flags)
1760 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1761 DRM_MODE_ROTATE_0 | flags);
1762 }
1763
vop_create_crtc(struct vop * vop)1764 static int vop_create_crtc(struct vop *vop)
1765 {
1766 const struct vop_data *vop_data = vop->data;
1767 struct device *dev = vop->dev;
1768 struct drm_device *drm_dev = vop->drm_dev;
1769 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1770 struct drm_crtc *crtc = &vop->crtc;
1771 struct device_node *port;
1772 int ret;
1773 int i;
1774
1775 /*
1776 * Create drm_plane for primary and cursor planes first, since we need
1777 * to pass them to drm_crtc_init_with_planes, which sets the
1778 * "possible_crtcs" to the newly initialized crtc.
1779 */
1780 for (i = 0; i < vop_data->win_size; i++) {
1781 struct vop_win *vop_win = &vop->win[i];
1782 const struct vop_win_data *win_data = vop_win->data;
1783
1784 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1785 win_data->type != DRM_PLANE_TYPE_CURSOR)
1786 continue;
1787
1788 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1789 0, &vop_plane_funcs,
1790 win_data->phy->data_formats,
1791 win_data->phy->nformats,
1792 win_data->phy->format_modifiers,
1793 win_data->type, NULL);
1794 if (ret) {
1795 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1796 ret);
1797 goto err_cleanup_planes;
1798 }
1799
1800 plane = &vop_win->base;
1801 drm_plane_helper_add(plane, &plane_helper_funcs);
1802 vop_plane_add_properties(plane, win_data);
1803 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1804 primary = plane;
1805 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1806 cursor = plane;
1807 }
1808
1809 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1810 &vop_crtc_funcs, NULL);
1811 if (ret)
1812 goto err_cleanup_planes;
1813
1814 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1815 if (vop->lut_regs) {
1816 drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size);
1817 drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size);
1818 }
1819
1820 /*
1821 * Create drm_planes for overlay windows with possible_crtcs restricted
1822 * to the newly created crtc.
1823 */
1824 for (i = 0; i < vop_data->win_size; i++) {
1825 struct vop_win *vop_win = &vop->win[i];
1826 const struct vop_win_data *win_data = vop_win->data;
1827 unsigned long possible_crtcs = drm_crtc_mask(crtc);
1828
1829 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1830 continue;
1831
1832 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1833 possible_crtcs,
1834 &vop_plane_funcs,
1835 win_data->phy->data_formats,
1836 win_data->phy->nformats,
1837 win_data->phy->format_modifiers,
1838 win_data->type, NULL);
1839 if (ret) {
1840 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1841 ret);
1842 goto err_cleanup_crtc;
1843 }
1844 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1845 vop_plane_add_properties(&vop_win->base, win_data);
1846 }
1847
1848 port = of_get_child_by_name(dev->of_node, "port");
1849 if (!port) {
1850 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1851 dev->of_node);
1852 ret = -ENOENT;
1853 goto err_cleanup_crtc;
1854 }
1855
1856 drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1857 vop_fb_unref_worker);
1858
1859 init_completion(&vop->dsp_hold_completion);
1860 init_completion(&vop->line_flag_completion);
1861 crtc->port = port;
1862
1863 ret = drm_self_refresh_helper_init(crtc);
1864 if (ret)
1865 DRM_DEV_DEBUG_KMS(vop->dev,
1866 "Failed to init %s with SR helpers %d, ignoring\n",
1867 crtc->name, ret);
1868
1869 return 0;
1870
1871 err_cleanup_crtc:
1872 drm_crtc_cleanup(crtc);
1873 err_cleanup_planes:
1874 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1875 head)
1876 drm_plane_cleanup(plane);
1877 return ret;
1878 }
1879
vop_destroy_crtc(struct vop * vop)1880 static void vop_destroy_crtc(struct vop *vop)
1881 {
1882 struct drm_crtc *crtc = &vop->crtc;
1883 struct drm_device *drm_dev = vop->drm_dev;
1884 struct drm_plane *plane, *tmp;
1885
1886 drm_self_refresh_helper_cleanup(crtc);
1887
1888 of_node_put(crtc->port);
1889
1890 /*
1891 * We need to cleanup the planes now. Why?
1892 *
1893 * The planes are "&vop->win[i].base". That means the memory is
1894 * all part of the big "struct vop" chunk of memory. That memory
1895 * was devm allocated and associated with this component. We need to
1896 * free it ourselves before vop_unbind() finishes.
1897 */
1898 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1899 head)
1900 vop_plane_destroy(plane);
1901
1902 /*
1903 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1904 * references the CRTC.
1905 */
1906 drm_crtc_cleanup(crtc);
1907 drm_flip_work_cleanup(&vop->fb_unref_work);
1908 }
1909
vop_initial(struct vop * vop)1910 static int vop_initial(struct vop *vop)
1911 {
1912 struct reset_control *ahb_rst;
1913 int i, ret;
1914
1915 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1916 if (IS_ERR(vop->hclk)) {
1917 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
1918 return PTR_ERR(vop->hclk);
1919 }
1920 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1921 if (IS_ERR(vop->aclk)) {
1922 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
1923 return PTR_ERR(vop->aclk);
1924 }
1925 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1926 if (IS_ERR(vop->dclk)) {
1927 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
1928 return PTR_ERR(vop->dclk);
1929 }
1930
1931 ret = pm_runtime_get_sync(vop->dev);
1932 if (ret < 0) {
1933 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
1934 return ret;
1935 }
1936
1937 ret = clk_prepare(vop->dclk);
1938 if (ret < 0) {
1939 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
1940 goto err_put_pm_runtime;
1941 }
1942
1943 /* Enable both the hclk and aclk to setup the vop */
1944 ret = clk_prepare_enable(vop->hclk);
1945 if (ret < 0) {
1946 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
1947 goto err_unprepare_dclk;
1948 }
1949
1950 ret = clk_prepare_enable(vop->aclk);
1951 if (ret < 0) {
1952 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
1953 goto err_disable_hclk;
1954 }
1955
1956 /*
1957 * do hclk_reset, reset all vop registers.
1958 */
1959 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1960 if (IS_ERR(ahb_rst)) {
1961 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
1962 ret = PTR_ERR(ahb_rst);
1963 goto err_disable_aclk;
1964 }
1965 reset_control_assert(ahb_rst);
1966 usleep_range(10, 20);
1967 reset_control_deassert(ahb_rst);
1968
1969 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
1970 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
1971
1972 for (i = 0; i < vop->len; i += sizeof(u32))
1973 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
1974
1975 VOP_REG_SET(vop, misc, global_regdone_en, 1);
1976 VOP_REG_SET(vop, common, dsp_blank, 0);
1977
1978 for (i = 0; i < vop->data->win_size; i++) {
1979 struct vop_win *vop_win = &vop->win[i];
1980 const struct vop_win_data *win = vop_win->data;
1981 int channel = i * 2 + 1;
1982
1983 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
1984 vop_win_disable(vop, vop_win);
1985 VOP_WIN_SET(vop, win, gate, 1);
1986 }
1987
1988 vop_cfg_done(vop);
1989
1990 /*
1991 * do dclk_reset, let all config take affect.
1992 */
1993 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1994 if (IS_ERR(vop->dclk_rst)) {
1995 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
1996 ret = PTR_ERR(vop->dclk_rst);
1997 goto err_disable_aclk;
1998 }
1999 reset_control_assert(vop->dclk_rst);
2000 usleep_range(10, 20);
2001 reset_control_deassert(vop->dclk_rst);
2002
2003 clk_disable(vop->hclk);
2004 clk_disable(vop->aclk);
2005
2006 vop->is_enabled = false;
2007
2008 pm_runtime_put_sync(vop->dev);
2009
2010 return 0;
2011
2012 err_disable_aclk:
2013 clk_disable_unprepare(vop->aclk);
2014 err_disable_hclk:
2015 clk_disable_unprepare(vop->hclk);
2016 err_unprepare_dclk:
2017 clk_unprepare(vop->dclk);
2018 err_put_pm_runtime:
2019 pm_runtime_put_sync(vop->dev);
2020 return ret;
2021 }
2022
2023 /*
2024 * Initialize the vop->win array elements.
2025 */
vop_win_init(struct vop * vop)2026 static void vop_win_init(struct vop *vop)
2027 {
2028 const struct vop_data *vop_data = vop->data;
2029 unsigned int i;
2030
2031 for (i = 0; i < vop_data->win_size; i++) {
2032 struct vop_win *vop_win = &vop->win[i];
2033 const struct vop_win_data *win_data = &vop_data->win[i];
2034
2035 vop_win->data = win_data;
2036 vop_win->vop = vop;
2037
2038 if (vop_data->win_yuv2yuv)
2039 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i];
2040 }
2041 }
2042
2043 /**
2044 * rockchip_drm_wait_vact_end
2045 * @crtc: CRTC to enable line flag
2046 * @mstimeout: millisecond for timeout
2047 *
2048 * Wait for vact_end line flag irq or timeout.
2049 *
2050 * Returns:
2051 * Zero on success, negative errno on failure.
2052 */
rockchip_drm_wait_vact_end(struct drm_crtc * crtc,unsigned int mstimeout)2053 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
2054 {
2055 struct vop *vop = to_vop(crtc);
2056 unsigned long jiffies_left;
2057 int ret = 0;
2058
2059 if (!crtc || !vop->is_enabled)
2060 return -ENODEV;
2061
2062 mutex_lock(&vop->vop_lock);
2063 if (mstimeout <= 0) {
2064 ret = -EINVAL;
2065 goto out;
2066 }
2067
2068 if (vop_line_flag_irq_is_enabled(vop)) {
2069 ret = -EBUSY;
2070 goto out;
2071 }
2072
2073 reinit_completion(&vop->line_flag_completion);
2074 vop_line_flag_irq_enable(vop);
2075
2076 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2077 msecs_to_jiffies(mstimeout));
2078 vop_line_flag_irq_disable(vop);
2079
2080 if (jiffies_left == 0) {
2081 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
2082 ret = -ETIMEDOUT;
2083 goto out;
2084 }
2085
2086 out:
2087 mutex_unlock(&vop->vop_lock);
2088 return ret;
2089 }
2090 EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
2091
vop_bind(struct device * dev,struct device * master,void * data)2092 static int vop_bind(struct device *dev, struct device *master, void *data)
2093 {
2094 struct platform_device *pdev = to_platform_device(dev);
2095 const struct vop_data *vop_data;
2096 struct drm_device *drm_dev = data;
2097 struct vop *vop;
2098 struct resource *res;
2099 int ret, irq;
2100
2101 vop_data = of_device_get_match_data(dev);
2102 if (!vop_data)
2103 return -ENODEV;
2104
2105 /* Allocate vop struct and its vop_win array */
2106 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size),
2107 GFP_KERNEL);
2108 if (!vop)
2109 return -ENOMEM;
2110
2111 vop->dev = dev;
2112 vop->data = vop_data;
2113 vop->drm_dev = drm_dev;
2114 dev_set_drvdata(dev, vop);
2115
2116 vop_win_init(vop);
2117
2118 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2119 vop->len = resource_size(res);
2120 vop->regs = devm_ioremap_resource(dev, res);
2121 if (IS_ERR(vop->regs))
2122 return PTR_ERR(vop->regs);
2123
2124 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2125 if (res) {
2126 if (!vop_data->lut_size) {
2127 DRM_DEV_ERROR(dev, "no gamma LUT size defined\n");
2128 return -EINVAL;
2129 }
2130 vop->lut_regs = devm_ioremap_resource(dev, res);
2131 if (IS_ERR(vop->lut_regs))
2132 return PTR_ERR(vop->lut_regs);
2133 }
2134
2135 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2136 if (!vop->regsbak)
2137 return -ENOMEM;
2138
2139 irq = platform_get_irq(pdev, 0);
2140 if (irq < 0) {
2141 DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
2142 return irq;
2143 }
2144 vop->irq = (unsigned int)irq;
2145
2146 spin_lock_init(&vop->reg_lock);
2147 spin_lock_init(&vop->irq_lock);
2148 mutex_init(&vop->vop_lock);
2149
2150 ret = vop_create_crtc(vop);
2151 if (ret)
2152 return ret;
2153
2154 pm_runtime_enable(&pdev->dev);
2155
2156 ret = vop_initial(vop);
2157 if (ret < 0) {
2158 DRM_DEV_ERROR(&pdev->dev,
2159 "cannot initial vop dev - err %d\n", ret);
2160 goto err_disable_pm_runtime;
2161 }
2162
2163 ret = devm_request_irq(dev, vop->irq, vop_isr,
2164 IRQF_SHARED, dev_name(dev), vop);
2165 if (ret)
2166 goto err_disable_pm_runtime;
2167
2168 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) {
2169 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev);
2170 if (IS_ERR(vop->rgb)) {
2171 ret = PTR_ERR(vop->rgb);
2172 goto err_disable_pm_runtime;
2173 }
2174 }
2175
2176 return 0;
2177
2178 err_disable_pm_runtime:
2179 pm_runtime_disable(&pdev->dev);
2180 vop_destroy_crtc(vop);
2181 return ret;
2182 }
2183
vop_unbind(struct device * dev,struct device * master,void * data)2184 static void vop_unbind(struct device *dev, struct device *master, void *data)
2185 {
2186 struct vop *vop = dev_get_drvdata(dev);
2187
2188 if (vop->rgb)
2189 rockchip_rgb_fini(vop->rgb);
2190
2191 pm_runtime_disable(dev);
2192 vop_destroy_crtc(vop);
2193
2194 clk_unprepare(vop->aclk);
2195 clk_unprepare(vop->hclk);
2196 clk_unprepare(vop->dclk);
2197 }
2198
2199 const struct component_ops vop_component_ops = {
2200 .bind = vop_bind,
2201 .unbind = vop_unbind,
2202 };
2203 EXPORT_SYMBOL_GPL(vop_component_ops);
2204
