1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * skl_topology.h - Intel HDA Platform topology header file 4 * 5 * Copyright (C) 2014-15 Intel Corp 6 * Author: Jeeja KP <jeeja.kp@intel.com> 7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 8 * 9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 10 */ 11 12 #ifndef __SKL_TOPOLOGY_H__ 13 #define __SKL_TOPOLOGY_H__ 14 15 #include <linux/types.h> 16 17 #include <sound/hdaudio_ext.h> 18 #include <sound/soc.h> 19 #include <uapi/sound/skl-tplg-interface.h> 20 #include "skl.h" 21 22 #define BITS_PER_BYTE 8 23 #define MAX_TS_GROUPS 8 24 #define MAX_DMIC_TS_GROUPS 4 25 #define MAX_FIXED_DMIC_PARAMS_SIZE 727 26 27 /* Maximum number of coefficients up down mixer module */ 28 #define UP_DOWN_MIXER_MAX_COEFF 8 29 30 #define MODULE_MAX_IN_PINS 8 31 #define MODULE_MAX_OUT_PINS 8 32 33 #define SKL_MIC_CH_SUPPORT 4 34 #define SKL_MIC_MAX_CH_SUPPORT 8 35 #define SKL_DEFAULT_MIC_SEL_GAIN 0x3FF 36 #define SKL_MIC_SEL_SWITCH 0x3 37 38 #define SKL_OUTPUT_PIN 0 39 #define SKL_INPUT_PIN 1 40 #define SKL_MAX_PATH_CONFIGS 8 41 #define SKL_MAX_MODULES_IN_PIPE 8 42 #define SKL_MAX_MODULE_FORMATS 32 43 #define SKL_MAX_MODULE_RESOURCES 32 44 45 enum skl_channel_index { 46 SKL_CHANNEL_LEFT = 0, 47 SKL_CHANNEL_RIGHT = 1, 48 SKL_CHANNEL_CENTER = 2, 49 SKL_CHANNEL_LEFT_SURROUND = 3, 50 SKL_CHANNEL_CENTER_SURROUND = 3, 51 SKL_CHANNEL_RIGHT_SURROUND = 4, 52 SKL_CHANNEL_LFE = 7, 53 SKL_CHANNEL_INVALID = 0xF, 54 }; 55 56 enum skl_bitdepth { 57 SKL_DEPTH_8BIT = 8, 58 SKL_DEPTH_16BIT = 16, 59 SKL_DEPTH_24BIT = 24, 60 SKL_DEPTH_32BIT = 32, 61 SKL_DEPTH_INVALID 62 }; 63 64 65 enum skl_s_freq { 66 SKL_FS_8000 = 8000, 67 SKL_FS_11025 = 11025, 68 SKL_FS_12000 = 12000, 69 SKL_FS_16000 = 16000, 70 SKL_FS_22050 = 22050, 71 SKL_FS_24000 = 24000, 72 SKL_FS_32000 = 32000, 73 SKL_FS_44100 = 44100, 74 SKL_FS_48000 = 48000, 75 SKL_FS_64000 = 64000, 76 SKL_FS_88200 = 88200, 77 SKL_FS_96000 = 96000, 78 SKL_FS_128000 = 128000, 79 SKL_FS_176400 = 176400, 80 SKL_FS_192000 = 192000, 81 SKL_FS_INVALID 82 }; 83 84 enum skl_widget_type { 85 SKL_WIDGET_VMIXER = 1, 86 SKL_WIDGET_MIXER = 2, 87 SKL_WIDGET_PGA = 3, 88 SKL_WIDGET_MUX = 4 89 }; 90 91 struct skl_audio_data_format { 92 enum skl_s_freq s_freq; 93 enum skl_bitdepth bit_depth; 94 u32 channel_map; 95 enum skl_ch_cfg ch_cfg; 96 enum skl_interleaving interleaving; 97 u8 number_of_channels; 98 u8 valid_bit_depth; 99 u8 sample_type; 100 u8 reserved; 101 } __packed; 102 103 struct skl_base_cfg { 104 u32 cpc; 105 u32 ibs; 106 u32 obs; 107 u32 is_pages; 108 struct skl_audio_data_format audio_fmt; 109 }; 110 111 struct skl_cpr_gtw_cfg { 112 u32 node_id; 113 u32 dma_buffer_size; 114 u32 config_length; 115 /* not mandatory; required only for DMIC/I2S */ 116 u32 config_data[1]; 117 } __packed; 118 119 struct skl_dma_control { 120 u32 node_id; 121 u32 config_length; 122 u32 config_data[]; 123 } __packed; 124 125 struct skl_cpr_cfg { 126 struct skl_base_cfg base_cfg; 127 struct skl_audio_data_format out_fmt; 128 u32 cpr_feature_mask; 129 struct skl_cpr_gtw_cfg gtw_cfg; 130 } __packed; 131 132 struct skl_cpr_pin_fmt { 133 u32 sink_id; 134 struct skl_audio_data_format src_fmt; 135 struct skl_audio_data_format dst_fmt; 136 } __packed; 137 138 struct skl_src_module_cfg { 139 struct skl_base_cfg base_cfg; 140 enum skl_s_freq src_cfg; 141 } __packed; 142 143 struct skl_up_down_mixer_cfg { 144 struct skl_base_cfg base_cfg; 145 enum skl_ch_cfg out_ch_cfg; 146 /* This should be set to 1 if user coefficients are required */ 147 u32 coeff_sel; 148 /* Pass the user coeff in this array */ 149 s32 coeff[UP_DOWN_MIXER_MAX_COEFF]; 150 u32 ch_map; 151 } __packed; 152 153 struct skl_algo_cfg { 154 struct skl_base_cfg base_cfg; 155 char params[]; 156 } __packed; 157 158 struct skl_base_outfmt_cfg { 159 struct skl_base_cfg base_cfg; 160 struct skl_audio_data_format out_fmt; 161 } __packed; 162 163 enum skl_dma_type { 164 SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0, 165 SKL_DMA_HDA_HOST_INPUT_CLASS = 1, 166 SKL_DMA_HDA_HOST_INOUT_CLASS = 2, 167 SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8, 168 SKL_DMA_HDA_LINK_INPUT_CLASS = 9, 169 SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA, 170 SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB, 171 SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC, 172 SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD, 173 }; 174 175 union skl_ssp_dma_node { 176 u8 val; 177 struct { 178 u8 time_slot_index:4; 179 u8 i2s_instance:4; 180 } dma_node; 181 }; 182 183 union skl_connector_node_id { 184 u32 val; 185 struct { 186 u32 vindex:8; 187 u32 dma_type:4; 188 u32 rsvd:20; 189 } node; 190 }; 191 192 struct skl_module_fmt { 193 u32 channels; 194 u32 s_freq; 195 u32 bit_depth; 196 u32 valid_bit_depth; 197 u32 ch_cfg; 198 u32 interleaving_style; 199 u32 sample_type; 200 u32 ch_map; 201 }; 202 203 struct skl_module_cfg; 204 205 struct skl_mod_inst_map { 206 u16 mod_id; 207 u16 inst_id; 208 }; 209 210 struct skl_uuid_inst_map { 211 u16 inst_id; 212 u16 reserved; 213 guid_t mod_uuid; 214 } __packed; 215 216 struct skl_kpb_params { 217 u32 num_modules; 218 union { 219 struct skl_mod_inst_map map[0]; 220 struct skl_uuid_inst_map map_uuid[0]; 221 } u; 222 }; 223 224 struct skl_module_inst_id { 225 guid_t mod_uuid; 226 int module_id; 227 u32 instance_id; 228 int pvt_id; 229 }; 230 231 enum skl_module_pin_state { 232 SKL_PIN_UNBIND = 0, 233 SKL_PIN_BIND_DONE = 1, 234 }; 235 236 struct skl_module_pin { 237 struct skl_module_inst_id id; 238 bool is_dynamic; 239 bool in_use; 240 enum skl_module_pin_state pin_state; 241 struct skl_module_cfg *tgt_mcfg; 242 }; 243 244 struct skl_specific_cfg { 245 u32 set_params; 246 u32 param_id; 247 u32 caps_size; 248 u32 *caps; 249 }; 250 251 enum skl_pipe_state { 252 SKL_PIPE_INVALID = 0, 253 SKL_PIPE_CREATED = 1, 254 SKL_PIPE_PAUSED = 2, 255 SKL_PIPE_STARTED = 3, 256 SKL_PIPE_RESET = 4 257 }; 258 259 struct skl_pipe_module { 260 struct snd_soc_dapm_widget *w; 261 struct list_head node; 262 }; 263 264 struct skl_pipe_params { 265 u8 host_dma_id; 266 u8 link_dma_id; 267 u32 ch; 268 u32 s_freq; 269 u32 s_fmt; 270 u8 linktype; 271 snd_pcm_format_t format; 272 int link_index; 273 int stream; 274 unsigned int host_bps; 275 unsigned int link_bps; 276 }; 277 278 struct skl_pipe_fmt { 279 u32 freq; 280 u8 channels; 281 u8 bps; 282 }; 283 284 struct skl_pipe_mcfg { 285 u8 res_idx; 286 u8 fmt_idx; 287 }; 288 289 struct skl_path_config { 290 u8 mem_pages; 291 struct skl_pipe_fmt in_fmt; 292 struct skl_pipe_fmt out_fmt; 293 }; 294 295 struct skl_pipe { 296 u8 ppl_id; 297 u8 pipe_priority; 298 u16 conn_type; 299 u32 memory_pages; 300 u8 lp_mode; 301 struct skl_pipe_params *p_params; 302 enum skl_pipe_state state; 303 u8 direction; 304 u8 cur_config_idx; 305 u8 nr_cfgs; 306 struct skl_path_config configs[SKL_MAX_PATH_CONFIGS]; 307 struct list_head w_list; 308 bool passthru; 309 u32 pipe_config_idx; 310 }; 311 312 enum skl_module_state { 313 SKL_MODULE_UNINIT = 0, 314 SKL_MODULE_LOADED = 1, 315 SKL_MODULE_INIT_DONE = 2, 316 SKL_MODULE_BIND_DONE = 3, 317 SKL_MODULE_UNLOADED = 4, 318 }; 319 320 enum d0i3_capability { 321 SKL_D0I3_NONE = 0, 322 SKL_D0I3_STREAMING = 1, 323 SKL_D0I3_NON_STREAMING = 2, 324 }; 325 326 struct skl_module_pin_fmt { 327 u8 id; 328 struct skl_module_fmt fmt; 329 }; 330 331 struct skl_module_iface { 332 u8 fmt_idx; 333 u8 nr_in_fmt; 334 u8 nr_out_fmt; 335 struct skl_module_pin_fmt inputs[MAX_IN_QUEUE]; 336 struct skl_module_pin_fmt outputs[MAX_OUT_QUEUE]; 337 }; 338 339 struct skl_module_pin_resources { 340 u8 pin_index; 341 u32 buf_size; 342 }; 343 344 struct skl_module_res { 345 u8 id; 346 u32 is_pages; 347 u32 ibs; 348 u32 obs; 349 u32 dma_buffer_size; 350 u32 cpc; 351 u8 nr_input_pins; 352 u8 nr_output_pins; 353 struct skl_module_pin_resources input[MAX_IN_QUEUE]; 354 struct skl_module_pin_resources output[MAX_OUT_QUEUE]; 355 }; 356 357 struct skl_module { 358 guid_t uuid; 359 u8 loadable; 360 u8 input_pin_type; 361 u8 output_pin_type; 362 u8 max_input_pins; 363 u8 max_output_pins; 364 u8 nr_resources; 365 u8 nr_interfaces; 366 struct skl_module_res resources[SKL_MAX_MODULE_RESOURCES]; 367 struct skl_module_iface formats[SKL_MAX_MODULE_FORMATS]; 368 }; 369 370 struct skl_module_cfg { 371 u8 guid[16]; 372 struct skl_module_inst_id id; 373 struct skl_module *module; 374 int res_idx; 375 int fmt_idx; 376 u8 domain; 377 bool homogenous_inputs; 378 bool homogenous_outputs; 379 struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS]; 380 struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS]; 381 u8 max_in_queue; 382 u8 max_out_queue; 383 u8 in_queue_mask; 384 u8 out_queue_mask; 385 u8 in_queue; 386 u8 out_queue; 387 u8 is_loadable; 388 u8 core_id; 389 u8 dev_type; 390 u8 dma_id; 391 u8 time_slot; 392 u8 dmic_ch_combo_index; 393 u32 dmic_ch_type; 394 u32 params_fixup; 395 u32 converter; 396 u32 vbus_id; 397 u32 mem_pages; 398 enum d0i3_capability d0i3_caps; 399 u32 dma_buffer_size; /* in milli seconds */ 400 struct skl_module_pin *m_in_pin; 401 struct skl_module_pin *m_out_pin; 402 enum skl_module_type m_type; 403 enum skl_hw_conn_type hw_conn_type; 404 enum skl_module_state m_state; 405 struct skl_pipe *pipe; 406 struct skl_specific_cfg formats_config; 407 struct skl_pipe_mcfg mod_cfg[SKL_MAX_MODULES_IN_PIPE]; 408 }; 409 410 struct skl_algo_data { 411 u32 param_id; 412 u32 set_params; 413 u32 max; 414 u32 size; 415 char *params; 416 }; 417 418 struct skl_pipeline { 419 struct skl_pipe *pipe; 420 struct list_head node; 421 }; 422 423 struct skl_module_deferred_bind { 424 struct skl_module_cfg *src; 425 struct skl_module_cfg *dst; 426 struct list_head node; 427 }; 428 429 struct skl_mic_sel_config { 430 u16 mic_switch; 431 u16 flags; 432 u16 blob[SKL_MIC_MAX_CH_SUPPORT][SKL_MIC_MAX_CH_SUPPORT]; 433 } __packed; 434 435 enum skl_channel { 436 SKL_CH_MONO = 1, 437 SKL_CH_STEREO = 2, 438 SKL_CH_TRIO = 3, 439 SKL_CH_QUATRO = 4, 440 }; 441 get_skl_ctx(struct device * dev)442 static inline struct skl_dev *get_skl_ctx(struct device *dev) 443 { 444 struct hdac_bus *bus = dev_get_drvdata(dev); 445 446 return bus_to_skl(bus); 447 } 448 449 int skl_tplg_be_update_params(struct snd_soc_dai *dai, 450 struct skl_pipe_params *params); 451 int skl_dsp_set_dma_control(struct skl_dev *skl, u32 *caps, 452 u32 caps_size, u32 node_id); 453 void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai, 454 struct skl_pipe_params *params, int stream); 455 int skl_tplg_init(struct snd_soc_component *component, 456 struct hdac_bus *bus); 457 void skl_tplg_exit(struct snd_soc_component *component, 458 struct hdac_bus *bus); 459 struct skl_module_cfg *skl_tplg_fe_get_cpr_module( 460 struct snd_soc_dai *dai, int stream); 461 int skl_tplg_update_pipe_params(struct device *dev, 462 struct skl_module_cfg *mconfig, struct skl_pipe_params *params); 463 464 void skl_tplg_d0i3_get(struct skl_dev *skl, enum d0i3_capability caps); 465 void skl_tplg_d0i3_put(struct skl_dev *skl, enum d0i3_capability caps); 466 467 int skl_create_pipeline(struct skl_dev *skl, struct skl_pipe *pipe); 468 469 int skl_run_pipe(struct skl_dev *skl, struct skl_pipe *pipe); 470 471 int skl_pause_pipe(struct skl_dev *skl, struct skl_pipe *pipe); 472 473 int skl_delete_pipe(struct skl_dev *skl, struct skl_pipe *pipe); 474 475 int skl_stop_pipe(struct skl_dev *skl, struct skl_pipe *pipe); 476 477 int skl_reset_pipe(struct skl_dev *skl, struct skl_pipe *pipe); 478 479 int skl_init_module(struct skl_dev *skl, struct skl_module_cfg *mconfig); 480 481 int skl_bind_modules(struct skl_dev *skl, struct skl_module_cfg 482 *src_mcfg, struct skl_module_cfg *dst_mcfg); 483 484 int skl_unbind_modules(struct skl_dev *skl, struct skl_module_cfg 485 *src_mcfg, struct skl_module_cfg *dst_mcfg); 486 487 int skl_set_module_params(struct skl_dev *skl, u32 *params, int size, 488 u32 param_id, struct skl_module_cfg *mcfg); 489 int skl_get_module_params(struct skl_dev *skl, u32 *params, int size, 490 u32 param_id, struct skl_module_cfg *mcfg); 491 492 struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, 493 int stream); 494 enum skl_bitdepth skl_get_bit_depth(int params); 495 int skl_pcm_host_dma_prepare(struct device *dev, 496 struct skl_pipe_params *params); 497 int skl_pcm_link_dma_prepare(struct device *dev, 498 struct skl_pipe_params *params); 499 500 int skl_dai_load(struct snd_soc_component *cmp, int index, 501 struct snd_soc_dai_driver *dai_drv, 502 struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai); 503 void skl_tplg_add_moduleid_in_bind_params(struct skl_dev *skl, 504 struct snd_soc_dapm_widget *w); 505 #endif 506
