1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
3
4 /* e1000_hw.c
5 * Shared functions for accessing and configuring the MAC
6 */
7
8 #include "e1000.h"
9
10 static s32 e1000_check_downshift(struct e1000_hw *hw);
11 static s32 e1000_check_polarity(struct e1000_hw *hw,
12 e1000_rev_polarity *polarity);
13 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
14 static void e1000_clear_vfta(struct e1000_hw *hw);
15 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
16 bool link_up);
17 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
18 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
19 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
20 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
21 u16 *max_length);
22 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
23 static s32 e1000_id_led_init(struct e1000_hw *hw);
24 static void e1000_init_rx_addrs(struct e1000_hw *hw);
25 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
26 struct e1000_phy_info *phy_info);
27 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
28 struct e1000_phy_info *phy_info);
29 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
30 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
31 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
32 static s32 e1000_set_phy_type(struct e1000_hw *hw);
33 static void e1000_phy_init_script(struct e1000_hw *hw);
34 static s32 e1000_setup_copper_link(struct e1000_hw *hw);
35 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
36 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
37 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
38 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
39 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
40 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
41 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
42 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
43 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
44 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
45 u16 words, u16 *data);
46 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
47 u16 words, u16 *data);
48 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
49 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
50 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
51 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
52 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
53 u16 phy_data);
54 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
55 u16 *phy_data);
56 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
57 static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
58 static void e1000_release_eeprom(struct e1000_hw *hw);
59 static void e1000_standby_eeprom(struct e1000_hw *hw);
60 static s32 e1000_set_vco_speed(struct e1000_hw *hw);
61 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
62 static s32 e1000_set_phy_mode(struct e1000_hw *hw);
63 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
64 u16 *data);
65 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
66 u16 *data);
67
68 /* IGP cable length table */
69 static const
70 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
71 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
72 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
73 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
74 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
75 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
76 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,
77 100,
78 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
79 110, 110,
80 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,
81 120, 120
82 };
83
84 static DEFINE_MUTEX(e1000_eeprom_lock);
85 static DEFINE_SPINLOCK(e1000_phy_lock);
86
87 /**
88 * e1000_set_phy_type - Set the phy type member in the hw struct.
89 * @hw: Struct containing variables accessed by shared code
90 */
e1000_set_phy_type(struct e1000_hw * hw)91 static s32 e1000_set_phy_type(struct e1000_hw *hw)
92 {
93 if (hw->mac_type == e1000_undefined)
94 return -E1000_ERR_PHY_TYPE;
95
96 switch (hw->phy_id) {
97 case M88E1000_E_PHY_ID:
98 case M88E1000_I_PHY_ID:
99 case M88E1011_I_PHY_ID:
100 case M88E1111_I_PHY_ID:
101 case M88E1118_E_PHY_ID:
102 hw->phy_type = e1000_phy_m88;
103 break;
104 case IGP01E1000_I_PHY_ID:
105 if (hw->mac_type == e1000_82541 ||
106 hw->mac_type == e1000_82541_rev_2 ||
107 hw->mac_type == e1000_82547 ||
108 hw->mac_type == e1000_82547_rev_2)
109 hw->phy_type = e1000_phy_igp;
110 break;
111 case RTL8211B_PHY_ID:
112 hw->phy_type = e1000_phy_8211;
113 break;
114 case RTL8201N_PHY_ID:
115 hw->phy_type = e1000_phy_8201;
116 break;
117 default:
118 /* Should never have loaded on this device */
119 hw->phy_type = e1000_phy_undefined;
120 return -E1000_ERR_PHY_TYPE;
121 }
122
123 return E1000_SUCCESS;
124 }
125
126 /**
127 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY
128 * @hw: Struct containing variables accessed by shared code
129 */
e1000_phy_init_script(struct e1000_hw * hw)130 static void e1000_phy_init_script(struct e1000_hw *hw)
131 {
132 u16 phy_saved_data;
133
134 if (hw->phy_init_script) {
135 msleep(20);
136
137 /* Save off the current value of register 0x2F5B to be restored
138 * at the end of this routine.
139 */
140 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
141
142 /* Disabled the PHY transmitter */
143 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
144 msleep(20);
145
146 e1000_write_phy_reg(hw, 0x0000, 0x0140);
147 msleep(5);
148
149 switch (hw->mac_type) {
150 case e1000_82541:
151 case e1000_82547:
152 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
153 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
154 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
155 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
156 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
157 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
158 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
159 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
160 e1000_write_phy_reg(hw, 0x2010, 0x0008);
161 break;
162
163 case e1000_82541_rev_2:
164 case e1000_82547_rev_2:
165 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
166 break;
167 default:
168 break;
169 }
170
171 e1000_write_phy_reg(hw, 0x0000, 0x3300);
172 msleep(20);
173
174 /* Now enable the transmitter */
175 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
176
177 if (hw->mac_type == e1000_82547) {
178 u16 fused, fine, coarse;
179
180 /* Move to analog registers page */
181 e1000_read_phy_reg(hw,
182 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
183 &fused);
184
185 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
186 e1000_read_phy_reg(hw,
187 IGP01E1000_ANALOG_FUSE_STATUS,
188 &fused);
189
190 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
191 coarse =
192 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
193
194 if (coarse >
195 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
196 coarse -=
197 IGP01E1000_ANALOG_FUSE_COARSE_10;
198 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
199 } else if (coarse ==
200 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
201 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
202
203 fused =
204 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
205 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
206 (coarse &
207 IGP01E1000_ANALOG_FUSE_COARSE_MASK);
208
209 e1000_write_phy_reg(hw,
210 IGP01E1000_ANALOG_FUSE_CONTROL,
211 fused);
212 e1000_write_phy_reg(hw,
213 IGP01E1000_ANALOG_FUSE_BYPASS,
214 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
215 }
216 }
217 }
218 }
219
220 /**
221 * e1000_set_mac_type - Set the mac type member in the hw struct.
222 * @hw: Struct containing variables accessed by shared code
223 */
e1000_set_mac_type(struct e1000_hw * hw)224 s32 e1000_set_mac_type(struct e1000_hw *hw)
225 {
226 switch (hw->device_id) {
227 case E1000_DEV_ID_82542:
228 switch (hw->revision_id) {
229 case E1000_82542_2_0_REV_ID:
230 hw->mac_type = e1000_82542_rev2_0;
231 break;
232 case E1000_82542_2_1_REV_ID:
233 hw->mac_type = e1000_82542_rev2_1;
234 break;
235 default:
236 /* Invalid 82542 revision ID */
237 return -E1000_ERR_MAC_TYPE;
238 }
239 break;
240 case E1000_DEV_ID_82543GC_FIBER:
241 case E1000_DEV_ID_82543GC_COPPER:
242 hw->mac_type = e1000_82543;
243 break;
244 case E1000_DEV_ID_82544EI_COPPER:
245 case E1000_DEV_ID_82544EI_FIBER:
246 case E1000_DEV_ID_82544GC_COPPER:
247 case E1000_DEV_ID_82544GC_LOM:
248 hw->mac_type = e1000_82544;
249 break;
250 case E1000_DEV_ID_82540EM:
251 case E1000_DEV_ID_82540EM_LOM:
252 case E1000_DEV_ID_82540EP:
253 case E1000_DEV_ID_82540EP_LOM:
254 case E1000_DEV_ID_82540EP_LP:
255 hw->mac_type = e1000_82540;
256 break;
257 case E1000_DEV_ID_82545EM_COPPER:
258 case E1000_DEV_ID_82545EM_FIBER:
259 hw->mac_type = e1000_82545;
260 break;
261 case E1000_DEV_ID_82545GM_COPPER:
262 case E1000_DEV_ID_82545GM_FIBER:
263 case E1000_DEV_ID_82545GM_SERDES:
264 hw->mac_type = e1000_82545_rev_3;
265 break;
266 case E1000_DEV_ID_82546EB_COPPER:
267 case E1000_DEV_ID_82546EB_FIBER:
268 case E1000_DEV_ID_82546EB_QUAD_COPPER:
269 hw->mac_type = e1000_82546;
270 break;
271 case E1000_DEV_ID_82546GB_COPPER:
272 case E1000_DEV_ID_82546GB_FIBER:
273 case E1000_DEV_ID_82546GB_SERDES:
274 case E1000_DEV_ID_82546GB_PCIE:
275 case E1000_DEV_ID_82546GB_QUAD_COPPER:
276 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
277 hw->mac_type = e1000_82546_rev_3;
278 break;
279 case E1000_DEV_ID_82541EI:
280 case E1000_DEV_ID_82541EI_MOBILE:
281 case E1000_DEV_ID_82541ER_LOM:
282 hw->mac_type = e1000_82541;
283 break;
284 case E1000_DEV_ID_82541ER:
285 case E1000_DEV_ID_82541GI:
286 case E1000_DEV_ID_82541GI_LF:
287 case E1000_DEV_ID_82541GI_MOBILE:
288 hw->mac_type = e1000_82541_rev_2;
289 break;
290 case E1000_DEV_ID_82547EI:
291 case E1000_DEV_ID_82547EI_MOBILE:
292 hw->mac_type = e1000_82547;
293 break;
294 case E1000_DEV_ID_82547GI:
295 hw->mac_type = e1000_82547_rev_2;
296 break;
297 case E1000_DEV_ID_INTEL_CE4100_GBE:
298 hw->mac_type = e1000_ce4100;
299 break;
300 default:
301 /* Should never have loaded on this device */
302 return -E1000_ERR_MAC_TYPE;
303 }
304
305 switch (hw->mac_type) {
306 case e1000_82541:
307 case e1000_82547:
308 case e1000_82541_rev_2:
309 case e1000_82547_rev_2:
310 hw->asf_firmware_present = true;
311 break;
312 default:
313 break;
314 }
315
316 /* The 82543 chip does not count tx_carrier_errors properly in
317 * FD mode
318 */
319 if (hw->mac_type == e1000_82543)
320 hw->bad_tx_carr_stats_fd = true;
321
322 if (hw->mac_type > e1000_82544)
323 hw->has_smbus = true;
324
325 return E1000_SUCCESS;
326 }
327
328 /**
329 * e1000_set_media_type - Set media type and TBI compatibility.
330 * @hw: Struct containing variables accessed by shared code
331 */
e1000_set_media_type(struct e1000_hw * hw)332 void e1000_set_media_type(struct e1000_hw *hw)
333 {
334 u32 status;
335
336 if (hw->mac_type != e1000_82543) {
337 /* tbi_compatibility is only valid on 82543 */
338 hw->tbi_compatibility_en = false;
339 }
340
341 switch (hw->device_id) {
342 case E1000_DEV_ID_82545GM_SERDES:
343 case E1000_DEV_ID_82546GB_SERDES:
344 hw->media_type = e1000_media_type_internal_serdes;
345 break;
346 default:
347 switch (hw->mac_type) {
348 case e1000_82542_rev2_0:
349 case e1000_82542_rev2_1:
350 hw->media_type = e1000_media_type_fiber;
351 break;
352 case e1000_ce4100:
353 hw->media_type = e1000_media_type_copper;
354 break;
355 default:
356 status = er32(STATUS);
357 if (status & E1000_STATUS_TBIMODE) {
358 hw->media_type = e1000_media_type_fiber;
359 /* tbi_compatibility not valid on fiber */
360 hw->tbi_compatibility_en = false;
361 } else {
362 hw->media_type = e1000_media_type_copper;
363 }
364 break;
365 }
366 }
367 }
368
369 /**
370 * e1000_reset_hw - reset the hardware completely
371 * @hw: Struct containing variables accessed by shared code
372 *
373 * Reset the transmit and receive units; mask and clear all interrupts.
374 */
e1000_reset_hw(struct e1000_hw * hw)375 s32 e1000_reset_hw(struct e1000_hw *hw)
376 {
377 u32 ctrl;
378 u32 ctrl_ext;
379 u32 manc;
380 u32 led_ctrl;
381 s32 ret_val;
382
383 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
384 if (hw->mac_type == e1000_82542_rev2_0) {
385 e_dbg("Disabling MWI on 82542 rev 2.0\n");
386 e1000_pci_clear_mwi(hw);
387 }
388
389 /* Clear interrupt mask to stop board from generating interrupts */
390 e_dbg("Masking off all interrupts\n");
391 ew32(IMC, 0xffffffff);
392
393 /* Disable the Transmit and Receive units. Then delay to allow
394 * any pending transactions to complete before we hit the MAC with
395 * the global reset.
396 */
397 ew32(RCTL, 0);
398 ew32(TCTL, E1000_TCTL_PSP);
399 E1000_WRITE_FLUSH();
400
401 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
402 hw->tbi_compatibility_on = false;
403
404 /* Delay to allow any outstanding PCI transactions to complete before
405 * resetting the device
406 */
407 msleep(10);
408
409 ctrl = er32(CTRL);
410
411 /* Must reset the PHY before resetting the MAC */
412 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
413 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
414 E1000_WRITE_FLUSH();
415 msleep(5);
416 }
417
418 /* Issue a global reset to the MAC. This will reset the chip's
419 * transmit, receive, DMA, and link units. It will not effect
420 * the current PCI configuration. The global reset bit is self-
421 * clearing, and should clear within a microsecond.
422 */
423 e_dbg("Issuing a global reset to MAC\n");
424
425 switch (hw->mac_type) {
426 case e1000_82544:
427 case e1000_82540:
428 case e1000_82545:
429 case e1000_82546:
430 case e1000_82541:
431 case e1000_82541_rev_2:
432 /* These controllers can't ack the 64-bit write when issuing the
433 * reset, so use IO-mapping as a workaround to issue the reset
434 */
435 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
436 break;
437 case e1000_82545_rev_3:
438 case e1000_82546_rev_3:
439 /* Reset is performed on a shadow of the control register */
440 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
441 break;
442 case e1000_ce4100:
443 default:
444 ew32(CTRL, (ctrl | E1000_CTRL_RST));
445 break;
446 }
447
448 /* After MAC reset, force reload of EEPROM to restore power-on settings
449 * to device. Later controllers reload the EEPROM automatically, so
450 * just wait for reload to complete.
451 */
452 switch (hw->mac_type) {
453 case e1000_82542_rev2_0:
454 case e1000_82542_rev2_1:
455 case e1000_82543:
456 case e1000_82544:
457 /* Wait for reset to complete */
458 udelay(10);
459 ctrl_ext = er32(CTRL_EXT);
460 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
461 ew32(CTRL_EXT, ctrl_ext);
462 E1000_WRITE_FLUSH();
463 /* Wait for EEPROM reload */
464 msleep(2);
465 break;
466 case e1000_82541:
467 case e1000_82541_rev_2:
468 case e1000_82547:
469 case e1000_82547_rev_2:
470 /* Wait for EEPROM reload */
471 msleep(20);
472 break;
473 default:
474 /* Auto read done will delay 5ms or poll based on mac type */
475 ret_val = e1000_get_auto_rd_done(hw);
476 if (ret_val)
477 return ret_val;
478 break;
479 }
480
481 /* Disable HW ARPs on ASF enabled adapters */
482 if (hw->mac_type >= e1000_82540) {
483 manc = er32(MANC);
484 manc &= ~(E1000_MANC_ARP_EN);
485 ew32(MANC, manc);
486 }
487
488 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
489 e1000_phy_init_script(hw);
490
491 /* Configure activity LED after PHY reset */
492 led_ctrl = er32(LEDCTL);
493 led_ctrl &= IGP_ACTIVITY_LED_MASK;
494 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
495 ew32(LEDCTL, led_ctrl);
496 }
497
498 /* Clear interrupt mask to stop board from generating interrupts */
499 e_dbg("Masking off all interrupts\n");
500 ew32(IMC, 0xffffffff);
501
502 /* Clear any pending interrupt events. */
503 er32(ICR);
504
505 /* If MWI was previously enabled, reenable it. */
506 if (hw->mac_type == e1000_82542_rev2_0) {
507 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
508 e1000_pci_set_mwi(hw);
509 }
510
511 return E1000_SUCCESS;
512 }
513
514 /**
515 * e1000_init_hw - Performs basic configuration of the adapter.
516 * @hw: Struct containing variables accessed by shared code
517 *
518 * Assumes that the controller has previously been reset and is in a
519 * post-reset uninitialized state. Initializes the receive address registers,
520 * multicast table, and VLAN filter table. Calls routines to setup link
521 * configuration and flow control settings. Clears all on-chip counters. Leaves
522 * the transmit and receive units disabled and uninitialized.
523 */
e1000_init_hw(struct e1000_hw * hw)524 s32 e1000_init_hw(struct e1000_hw *hw)
525 {
526 u32 ctrl;
527 u32 i;
528 s32 ret_val;
529 u32 mta_size;
530 u32 ctrl_ext;
531
532 /* Initialize Identification LED */
533 ret_val = e1000_id_led_init(hw);
534 if (ret_val) {
535 e_dbg("Error Initializing Identification LED\n");
536 return ret_val;
537 }
538
539 /* Set the media type and TBI compatibility */
540 e1000_set_media_type(hw);
541
542 /* Disabling VLAN filtering. */
543 e_dbg("Initializing the IEEE VLAN\n");
544 if (hw->mac_type < e1000_82545_rev_3)
545 ew32(VET, 0);
546 e1000_clear_vfta(hw);
547
548 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
549 if (hw->mac_type == e1000_82542_rev2_0) {
550 e_dbg("Disabling MWI on 82542 rev 2.0\n");
551 e1000_pci_clear_mwi(hw);
552 ew32(RCTL, E1000_RCTL_RST);
553 E1000_WRITE_FLUSH();
554 msleep(5);
555 }
556
557 /* Setup the receive address. This involves initializing all of the
558 * Receive Address Registers (RARs 0 - 15).
559 */
560 e1000_init_rx_addrs(hw);
561
562 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
563 if (hw->mac_type == e1000_82542_rev2_0) {
564 ew32(RCTL, 0);
565 E1000_WRITE_FLUSH();
566 msleep(1);
567 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
568 e1000_pci_set_mwi(hw);
569 }
570
571 /* Zero out the Multicast HASH table */
572 e_dbg("Zeroing the MTA\n");
573 mta_size = E1000_MC_TBL_SIZE;
574 for (i = 0; i < mta_size; i++) {
575 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
576 /* use write flush to prevent Memory Write Block (MWB) from
577 * occurring when accessing our register space
578 */
579 E1000_WRITE_FLUSH();
580 }
581
582 /* Set the PCI priority bit correctly in the CTRL register. This
583 * determines if the adapter gives priority to receives, or if it
584 * gives equal priority to transmits and receives. Valid only on
585 * 82542 and 82543 silicon.
586 */
587 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
588 ctrl = er32(CTRL);
589 ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
590 }
591
592 switch (hw->mac_type) {
593 case e1000_82545_rev_3:
594 case e1000_82546_rev_3:
595 break;
596 default:
597 /* Workaround for PCI-X problem when BIOS sets MMRBC
598 * incorrectly.
599 */
600 if (hw->bus_type == e1000_bus_type_pcix &&
601 e1000_pcix_get_mmrbc(hw) > 2048)
602 e1000_pcix_set_mmrbc(hw, 2048);
603 break;
604 }
605
606 /* Call a subroutine to configure the link and setup flow control. */
607 ret_val = e1000_setup_link(hw);
608
609 /* Set the transmit descriptor write-back policy */
610 if (hw->mac_type > e1000_82544) {
611 ctrl = er32(TXDCTL);
612 ctrl =
613 (ctrl & ~E1000_TXDCTL_WTHRESH) |
614 E1000_TXDCTL_FULL_TX_DESC_WB;
615 ew32(TXDCTL, ctrl);
616 }
617
618 /* Clear all of the statistics registers (clear on read). It is
619 * important that we do this after we have tried to establish link
620 * because the symbol error count will increment wildly if there
621 * is no link.
622 */
623 e1000_clear_hw_cntrs(hw);
624
625 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
626 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
627 ctrl_ext = er32(CTRL_EXT);
628 /* Relaxed ordering must be disabled to avoid a parity
629 * error crash in a PCI slot.
630 */
631 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
632 ew32(CTRL_EXT, ctrl_ext);
633 }
634
635 return ret_val;
636 }
637
638 /**
639 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.
640 * @hw: Struct containing variables accessed by shared code.
641 */
e1000_adjust_serdes_amplitude(struct e1000_hw * hw)642 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
643 {
644 u16 eeprom_data;
645 s32 ret_val;
646
647 if (hw->media_type != e1000_media_type_internal_serdes)
648 return E1000_SUCCESS;
649
650 switch (hw->mac_type) {
651 case e1000_82545_rev_3:
652 case e1000_82546_rev_3:
653 break;
654 default:
655 return E1000_SUCCESS;
656 }
657
658 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
659 &eeprom_data);
660 if (ret_val)
661 return ret_val;
662
663 if (eeprom_data != EEPROM_RESERVED_WORD) {
664 /* Adjust SERDES output amplitude only. */
665 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
666 ret_val =
667 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
668 if (ret_val)
669 return ret_val;
670 }
671
672 return E1000_SUCCESS;
673 }
674
675 /**
676 * e1000_setup_link - Configures flow control and link settings.
677 * @hw: Struct containing variables accessed by shared code
678 *
679 * Determines which flow control settings to use. Calls the appropriate media-
680 * specific link configuration function. Configures the flow control settings.
681 * Assuming the adapter has a valid link partner, a valid link should be
682 * established. Assumes the hardware has previously been reset and the
683 * transmitter and receiver are not enabled.
684 */
e1000_setup_link(struct e1000_hw * hw)685 s32 e1000_setup_link(struct e1000_hw *hw)
686 {
687 u32 ctrl_ext;
688 s32 ret_val;
689 u16 eeprom_data;
690
691 /* Read and store word 0x0F of the EEPROM. This word contains bits
692 * that determine the hardware's default PAUSE (flow control) mode,
693 * a bit that determines whether the HW defaults to enabling or
694 * disabling auto-negotiation, and the direction of the
695 * SW defined pins. If there is no SW over-ride of the flow
696 * control setting, then the variable hw->fc will
697 * be initialized based on a value in the EEPROM.
698 */
699 if (hw->fc == E1000_FC_DEFAULT) {
700 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
701 1, &eeprom_data);
702 if (ret_val) {
703 e_dbg("EEPROM Read Error\n");
704 return -E1000_ERR_EEPROM;
705 }
706 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
707 hw->fc = E1000_FC_NONE;
708 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
709 EEPROM_WORD0F_ASM_DIR)
710 hw->fc = E1000_FC_TX_PAUSE;
711 else
712 hw->fc = E1000_FC_FULL;
713 }
714
715 /* We want to save off the original Flow Control configuration just
716 * in case we get disconnected and then reconnected into a different
717 * hub or switch with different Flow Control capabilities.
718 */
719 if (hw->mac_type == e1000_82542_rev2_0)
720 hw->fc &= (~E1000_FC_TX_PAUSE);
721
722 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
723 hw->fc &= (~E1000_FC_RX_PAUSE);
724
725 hw->original_fc = hw->fc;
726
727 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);
728
729 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
730 * polarity value for the SW controlled pins, and setup the
731 * Extended Device Control reg with that info.
732 * This is needed because one of the SW controlled pins is used for
733 * signal detection. So this should be done before e1000_setup_pcs_link()
734 * or e1000_phy_setup() is called.
735 */
736 if (hw->mac_type == e1000_82543) {
737 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
738 1, &eeprom_data);
739 if (ret_val) {
740 e_dbg("EEPROM Read Error\n");
741 return -E1000_ERR_EEPROM;
742 }
743 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
744 SWDPIO__EXT_SHIFT);
745 ew32(CTRL_EXT, ctrl_ext);
746 }
747
748 /* Call the necessary subroutine to configure the link. */
749 ret_val = (hw->media_type == e1000_media_type_copper) ?
750 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);
751
752 /* Initialize the flow control address, type, and PAUSE timer
753 * registers to their default values. This is done even if flow
754 * control is disabled, because it does not hurt anything to
755 * initialize these registers.
756 */
757 e_dbg("Initializing the Flow Control address, type and timer regs\n");
758
759 ew32(FCT, FLOW_CONTROL_TYPE);
760 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
761 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
762
763 ew32(FCTTV, hw->fc_pause_time);
764
765 /* Set the flow control receive threshold registers. Normally,
766 * these registers will be set to a default threshold that may be
767 * adjusted later by the driver's runtime code. However, if the
768 * ability to transmit pause frames in not enabled, then these
769 * registers will be set to 0.
770 */
771 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
772 ew32(FCRTL, 0);
773 ew32(FCRTH, 0);
774 } else {
775 /* We need to set up the Receive Threshold high and low water
776 * marks as well as (optionally) enabling the transmission of
777 * XON frames.
778 */
779 if (hw->fc_send_xon) {
780 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
781 ew32(FCRTH, hw->fc_high_water);
782 } else {
783 ew32(FCRTL, hw->fc_low_water);
784 ew32(FCRTH, hw->fc_high_water);
785 }
786 }
787 return ret_val;
788 }
789
790 /**
791 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link
792 * @hw: Struct containing variables accessed by shared code
793 *
794 * Manipulates Physical Coding Sublayer functions in order to configure
795 * link. Assumes the hardware has been previously reset and the transmitter
796 * and receiver are not enabled.
797 */
e1000_setup_fiber_serdes_link(struct e1000_hw * hw)798 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
799 {
800 u32 ctrl;
801 u32 status;
802 u32 txcw = 0;
803 u32 i;
804 u32 signal = 0;
805 s32 ret_val;
806
807 /* On adapters with a MAC newer than 82544, SWDP 1 will be
808 * set when the optics detect a signal. On older adapters, it will be
809 * cleared when there is a signal. This applies to fiber media only.
810 * If we're on serdes media, adjust the output amplitude to value
811 * set in the EEPROM.
812 */
813 ctrl = er32(CTRL);
814 if (hw->media_type == e1000_media_type_fiber)
815 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
816
817 ret_val = e1000_adjust_serdes_amplitude(hw);
818 if (ret_val)
819 return ret_val;
820
821 /* Take the link out of reset */
822 ctrl &= ~(E1000_CTRL_LRST);
823
824 /* Adjust VCO speed to improve BER performance */
825 ret_val = e1000_set_vco_speed(hw);
826 if (ret_val)
827 return ret_val;
828
829 e1000_config_collision_dist(hw);
830
831 /* Check for a software override of the flow control settings, and setup
832 * the device accordingly. If auto-negotiation is enabled, then
833 * software will have to set the "PAUSE" bits to the correct value in
834 * the Tranmsit Config Word Register (TXCW) and re-start
835 * auto-negotiation. However, if auto-negotiation is disabled, then
836 * software will have to manually configure the two flow control enable
837 * bits in the CTRL register.
838 *
839 * The possible values of the "fc" parameter are:
840 * 0: Flow control is completely disabled
841 * 1: Rx flow control is enabled (we can receive pause frames, but
842 * not send pause frames).
843 * 2: Tx flow control is enabled (we can send pause frames but we do
844 * not support receiving pause frames).
845 * 3: Both Rx and TX flow control (symmetric) are enabled.
846 */
847 switch (hw->fc) {
848 case E1000_FC_NONE:
849 /* Flow ctrl is completely disabled by a software over-ride */
850 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
851 break;
852 case E1000_FC_RX_PAUSE:
853 /* Rx Flow control is enabled and Tx Flow control is disabled by
854 * a software over-ride. Since there really isn't a way to
855 * advertise that we are capable of Rx Pause ONLY, we will
856 * advertise that we support both symmetric and asymmetric Rx
857 * PAUSE. Later, we will disable the adapter's ability to send
858 * PAUSE frames.
859 */
860 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
861 break;
862 case E1000_FC_TX_PAUSE:
863 /* Tx Flow control is enabled, and Rx Flow control is disabled,
864 * by a software over-ride.
865 */
866 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
867 break;
868 case E1000_FC_FULL:
869 /* Flow control (both Rx and Tx) is enabled by a software
870 * over-ride.
871 */
872 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
873 break;
874 default:
875 e_dbg("Flow control param set incorrectly\n");
876 return -E1000_ERR_CONFIG;
877 }
878
879 /* Since auto-negotiation is enabled, take the link out of reset (the
880 * link will be in reset, because we previously reset the chip). This
881 * will restart auto-negotiation. If auto-negotiation is successful
882 * then the link-up status bit will be set and the flow control enable
883 * bits (RFCE and TFCE) will be set according to their negotiated value.
884 */
885 e_dbg("Auto-negotiation enabled\n");
886
887 ew32(TXCW, txcw);
888 ew32(CTRL, ctrl);
889 E1000_WRITE_FLUSH();
890
891 hw->txcw = txcw;
892 msleep(1);
893
894 /* If we have a signal (the cable is plugged in) then poll for a
895 * "Link-Up" indication in the Device Status Register. Time-out if a
896 * link isn't seen in 500 milliseconds seconds (Auto-negotiation should
897 * complete in less than 500 milliseconds even if the other end is doing
898 * it in SW). For internal serdes, we just assume a signal is present,
899 * then poll.
900 */
901 if (hw->media_type == e1000_media_type_internal_serdes ||
902 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
903 e_dbg("Looking for Link\n");
904 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
905 msleep(10);
906 status = er32(STATUS);
907 if (status & E1000_STATUS_LU)
908 break;
909 }
910 if (i == (LINK_UP_TIMEOUT / 10)) {
911 e_dbg("Never got a valid link from auto-neg!!!\n");
912 hw->autoneg_failed = 1;
913 /* AutoNeg failed to achieve a link, so we'll call
914 * e1000_check_for_link. This routine will force the
915 * link up if we detect a signal. This will allow us to
916 * communicate with non-autonegotiating link partners.
917 */
918 ret_val = e1000_check_for_link(hw);
919 if (ret_val) {
920 e_dbg("Error while checking for link\n");
921 return ret_val;
922 }
923 hw->autoneg_failed = 0;
924 } else {
925 hw->autoneg_failed = 0;
926 e_dbg("Valid Link Found\n");
927 }
928 } else {
929 e_dbg("No Signal Detected\n");
930 }
931 return E1000_SUCCESS;
932 }
933
934 /**
935 * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series.
936 * @hw: Struct containing variables accessed by shared code
937 *
938 * Commits changes to PHY configuration by calling e1000_phy_reset().
939 */
e1000_copper_link_rtl_setup(struct e1000_hw * hw)940 static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)
941 {
942 s32 ret_val;
943
944 /* SW reset the PHY so all changes take effect */
945 ret_val = e1000_phy_reset(hw);
946 if (ret_val) {
947 e_dbg("Error Resetting the PHY\n");
948 return ret_val;
949 }
950
951 return E1000_SUCCESS;
952 }
953
gbe_dhg_phy_setup(struct e1000_hw * hw)954 static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)
955 {
956 s32 ret_val;
957 u32 ctrl_aux;
958
959 switch (hw->phy_type) {
960 case e1000_phy_8211:
961 ret_val = e1000_copper_link_rtl_setup(hw);
962 if (ret_val) {
963 e_dbg("e1000_copper_link_rtl_setup failed!\n");
964 return ret_val;
965 }
966 break;
967 case e1000_phy_8201:
968 /* Set RMII mode */
969 ctrl_aux = er32(CTL_AUX);
970 ctrl_aux |= E1000_CTL_AUX_RMII;
971 ew32(CTL_AUX, ctrl_aux);
972 E1000_WRITE_FLUSH();
973
974 /* Disable the J/K bits required for receive */
975 ctrl_aux = er32(CTL_AUX);
976 ctrl_aux |= 0x4;
977 ctrl_aux &= ~0x2;
978 ew32(CTL_AUX, ctrl_aux);
979 E1000_WRITE_FLUSH();
980 ret_val = e1000_copper_link_rtl_setup(hw);
981
982 if (ret_val) {
983 e_dbg("e1000_copper_link_rtl_setup failed!\n");
984 return ret_val;
985 }
986 break;
987 default:
988 e_dbg("Error Resetting the PHY\n");
989 return E1000_ERR_PHY_TYPE;
990 }
991
992 return E1000_SUCCESS;
993 }
994
995 /**
996 * e1000_copper_link_preconfig - early configuration for copper
997 * @hw: Struct containing variables accessed by shared code
998 *
999 * Make sure we have a valid PHY and change PHY mode before link setup.
1000 */
e1000_copper_link_preconfig(struct e1000_hw * hw)1001 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
1002 {
1003 u32 ctrl;
1004 s32 ret_val;
1005 u16 phy_data;
1006
1007 ctrl = er32(CTRL);
1008 /* With 82543, we need to force speed and duplex on the MAC equal to
1009 * what the PHY speed and duplex configuration is. In addition, we need
1010 * to perform a hardware reset on the PHY to take it out of reset.
1011 */
1012 if (hw->mac_type > e1000_82543) {
1013 ctrl |= E1000_CTRL_SLU;
1014 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1015 ew32(CTRL, ctrl);
1016 } else {
1017 ctrl |=
1018 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1019 ew32(CTRL, ctrl);
1020 ret_val = e1000_phy_hw_reset(hw);
1021 if (ret_val)
1022 return ret_val;
1023 }
1024
1025 /* Make sure we have a valid PHY */
1026 ret_val = e1000_detect_gig_phy(hw);
1027 if (ret_val) {
1028 e_dbg("Error, did not detect valid phy.\n");
1029 return ret_val;
1030 }
1031 e_dbg("Phy ID = %x\n", hw->phy_id);
1032
1033 /* Set PHY to class A mode (if necessary) */
1034 ret_val = e1000_set_phy_mode(hw);
1035 if (ret_val)
1036 return ret_val;
1037
1038 if ((hw->mac_type == e1000_82545_rev_3) ||
1039 (hw->mac_type == e1000_82546_rev_3)) {
1040 ret_val =
1041 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1042 phy_data |= 0x00000008;
1043 ret_val =
1044 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1045 }
1046
1047 if (hw->mac_type <= e1000_82543 ||
1048 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1049 hw->mac_type == e1000_82541_rev_2 ||
1050 hw->mac_type == e1000_82547_rev_2)
1051 hw->phy_reset_disable = false;
1052
1053 return E1000_SUCCESS;
1054 }
1055
1056 /**
1057 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.
1058 * @hw: Struct containing variables accessed by shared code
1059 */
e1000_copper_link_igp_setup(struct e1000_hw * hw)1060 static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1061 {
1062 u32 led_ctrl;
1063 s32 ret_val;
1064 u16 phy_data;
1065
1066 if (hw->phy_reset_disable)
1067 return E1000_SUCCESS;
1068
1069 ret_val = e1000_phy_reset(hw);
1070 if (ret_val) {
1071 e_dbg("Error Resetting the PHY\n");
1072 return ret_val;
1073 }
1074
1075 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1076 msleep(15);
1077 /* Configure activity LED after PHY reset */
1078 led_ctrl = er32(LEDCTL);
1079 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1080 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1081 ew32(LEDCTL, led_ctrl);
1082
1083 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1084 if (hw->phy_type == e1000_phy_igp) {
1085 /* disable lplu d3 during driver init */
1086 ret_val = e1000_set_d3_lplu_state(hw, false);
1087 if (ret_val) {
1088 e_dbg("Error Disabling LPLU D3\n");
1089 return ret_val;
1090 }
1091 }
1092
1093 /* Configure mdi-mdix settings */
1094 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1095 if (ret_val)
1096 return ret_val;
1097
1098 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1099 hw->dsp_config_state = e1000_dsp_config_disabled;
1100 /* Force MDI for earlier revs of the IGP PHY */
1101 phy_data &=
1102 ~(IGP01E1000_PSCR_AUTO_MDIX |
1103 IGP01E1000_PSCR_FORCE_MDI_MDIX);
1104 hw->mdix = 1;
1105
1106 } else {
1107 hw->dsp_config_state = e1000_dsp_config_enabled;
1108 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1109
1110 switch (hw->mdix) {
1111 case 1:
1112 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1113 break;
1114 case 2:
1115 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1116 break;
1117 case 0:
1118 default:
1119 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1120 break;
1121 }
1122 }
1123 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1124 if (ret_val)
1125 return ret_val;
1126
1127 /* set auto-master slave resolution settings */
1128 if (hw->autoneg) {
1129 e1000_ms_type phy_ms_setting = hw->master_slave;
1130
1131 if (hw->ffe_config_state == e1000_ffe_config_active)
1132 hw->ffe_config_state = e1000_ffe_config_enabled;
1133
1134 if (hw->dsp_config_state == e1000_dsp_config_activated)
1135 hw->dsp_config_state = e1000_dsp_config_enabled;
1136
1137 /* when autonegotiation advertisement is only 1000Mbps then we
1138 * should disable SmartSpeed and enable Auto MasterSlave
1139 * resolution as hardware default.
1140 */
1141 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1142 /* Disable SmartSpeed */
1143 ret_val =
1144 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1145 &phy_data);
1146 if (ret_val)
1147 return ret_val;
1148 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1149 ret_val =
1150 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1151 phy_data);
1152 if (ret_val)
1153 return ret_val;
1154 /* Set auto Master/Slave resolution process */
1155 ret_val =
1156 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1157 if (ret_val)
1158 return ret_val;
1159 phy_data &= ~CR_1000T_MS_ENABLE;
1160 ret_val =
1161 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1162 if (ret_val)
1163 return ret_val;
1164 }
1165
1166 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1167 if (ret_val)
1168 return ret_val;
1169
1170 /* load defaults for future use */
1171 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1172 ((phy_data & CR_1000T_MS_VALUE) ?
1173 e1000_ms_force_master :
1174 e1000_ms_force_slave) : e1000_ms_auto;
1175
1176 switch (phy_ms_setting) {
1177 case e1000_ms_force_master:
1178 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1179 break;
1180 case e1000_ms_force_slave:
1181 phy_data |= CR_1000T_MS_ENABLE;
1182 phy_data &= ~(CR_1000T_MS_VALUE);
1183 break;
1184 case e1000_ms_auto:
1185 phy_data &= ~CR_1000T_MS_ENABLE;
1186 default:
1187 break;
1188 }
1189 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1190 if (ret_val)
1191 return ret_val;
1192 }
1193
1194 return E1000_SUCCESS;
1195 }
1196
1197 /**
1198 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series.
1199 * @hw: Struct containing variables accessed by shared code
1200 */
e1000_copper_link_mgp_setup(struct e1000_hw * hw)1201 static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1202 {
1203 s32 ret_val;
1204 u16 phy_data;
1205
1206 if (hw->phy_reset_disable)
1207 return E1000_SUCCESS;
1208
1209 /* Enable CRS on TX. This must be set for half-duplex operation. */
1210 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1211 if (ret_val)
1212 return ret_val;
1213
1214 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1215
1216 /* Options:
1217 * MDI/MDI-X = 0 (default)
1218 * 0 - Auto for all speeds
1219 * 1 - MDI mode
1220 * 2 - MDI-X mode
1221 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1222 */
1223 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1224
1225 switch (hw->mdix) {
1226 case 1:
1227 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1228 break;
1229 case 2:
1230 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1231 break;
1232 case 3:
1233 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1234 break;
1235 case 0:
1236 default:
1237 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1238 break;
1239 }
1240
1241 /* Options:
1242 * disable_polarity_correction = 0 (default)
1243 * Automatic Correction for Reversed Cable Polarity
1244 * 0 - Disabled
1245 * 1 - Enabled
1246 */
1247 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1248 if (hw->disable_polarity_correction == 1)
1249 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1250 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1251 if (ret_val)
1252 return ret_val;
1253
1254 if (hw->phy_revision < M88E1011_I_REV_4) {
1255 /* Force TX_CLK in the Extended PHY Specific Control Register
1256 * to 25MHz clock.
1257 */
1258 ret_val =
1259 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1260 &phy_data);
1261 if (ret_val)
1262 return ret_val;
1263
1264 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1265
1266 if ((hw->phy_revision == E1000_REVISION_2) &&
1267 (hw->phy_id == M88E1111_I_PHY_ID)) {
1268 /* Vidalia Phy, set the downshift counter to 5x */
1269 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1270 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1271 ret_val = e1000_write_phy_reg(hw,
1272 M88E1000_EXT_PHY_SPEC_CTRL,
1273 phy_data);
1274 if (ret_val)
1275 return ret_val;
1276 } else {
1277 /* Configure Master and Slave downshift values */
1278 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1279 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1280 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1281 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1282 ret_val = e1000_write_phy_reg(hw,
1283 M88E1000_EXT_PHY_SPEC_CTRL,
1284 phy_data);
1285 if (ret_val)
1286 return ret_val;
1287 }
1288 }
1289
1290 /* SW Reset the PHY so all changes take effect */
1291 ret_val = e1000_phy_reset(hw);
1292 if (ret_val) {
1293 e_dbg("Error Resetting the PHY\n");
1294 return ret_val;
1295 }
1296
1297 return E1000_SUCCESS;
1298 }
1299
1300 /**
1301 * e1000_copper_link_autoneg - setup auto-neg
1302 * @hw: Struct containing variables accessed by shared code
1303 *
1304 * Setup auto-negotiation and flow control advertisements,
1305 * and then perform auto-negotiation.
1306 */
e1000_copper_link_autoneg(struct e1000_hw * hw)1307 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1308 {
1309 s32 ret_val;
1310 u16 phy_data;
1311
1312 /* Perform some bounds checking on the hw->autoneg_advertised
1313 * parameter. If this variable is zero, then set it to the default.
1314 */
1315 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1316
1317 /* If autoneg_advertised is zero, we assume it was not defaulted
1318 * by the calling code so we set to advertise full capability.
1319 */
1320 if (hw->autoneg_advertised == 0)
1321 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1322
1323 /* IFE/RTL8201N PHY only supports 10/100 */
1324 if (hw->phy_type == e1000_phy_8201)
1325 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1326
1327 e_dbg("Reconfiguring auto-neg advertisement params\n");
1328 ret_val = e1000_phy_setup_autoneg(hw);
1329 if (ret_val) {
1330 e_dbg("Error Setting up Auto-Negotiation\n");
1331 return ret_val;
1332 }
1333 e_dbg("Restarting Auto-Neg\n");
1334
1335 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1336 * the Auto Neg Restart bit in the PHY control register.
1337 */
1338 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1339 if (ret_val)
1340 return ret_val;
1341
1342 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1343 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1344 if (ret_val)
1345 return ret_val;
1346
1347 /* Does the user want to wait for Auto-Neg to complete here, or
1348 * check at a later time (for example, callback routine).
1349 */
1350 if (hw->wait_autoneg_complete) {
1351 ret_val = e1000_wait_autoneg(hw);
1352 if (ret_val) {
1353 e_dbg
1354 ("Error while waiting for autoneg to complete\n");
1355 return ret_val;
1356 }
1357 }
1358
1359 hw->get_link_status = true;
1360
1361 return E1000_SUCCESS;
1362 }
1363
1364 /**
1365 * e1000_copper_link_postconfig - post link setup
1366 * @hw: Struct containing variables accessed by shared code
1367 *
1368 * Config the MAC and the PHY after link is up.
1369 * 1) Set up the MAC to the current PHY speed/duplex
1370 * if we are on 82543. If we
1371 * are on newer silicon, we only need to configure
1372 * collision distance in the Transmit Control Register.
1373 * 2) Set up flow control on the MAC to that established with
1374 * the link partner.
1375 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1376 */
e1000_copper_link_postconfig(struct e1000_hw * hw)1377 static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1378 {
1379 s32 ret_val;
1380
1381 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) {
1382 e1000_config_collision_dist(hw);
1383 } else {
1384 ret_val = e1000_config_mac_to_phy(hw);
1385 if (ret_val) {
1386 e_dbg("Error configuring MAC to PHY settings\n");
1387 return ret_val;
1388 }
1389 }
1390 ret_val = e1000_config_fc_after_link_up(hw);
1391 if (ret_val) {
1392 e_dbg("Error Configuring Flow Control\n");
1393 return ret_val;
1394 }
1395
1396 /* Config DSP to improve Giga link quality */
1397 if (hw->phy_type == e1000_phy_igp) {
1398 ret_val = e1000_config_dsp_after_link_change(hw, true);
1399 if (ret_val) {
1400 e_dbg("Error Configuring DSP after link up\n");
1401 return ret_val;
1402 }
1403 }
1404
1405 return E1000_SUCCESS;
1406 }
1407
1408 /**
1409 * e1000_setup_copper_link - phy/speed/duplex setting
1410 * @hw: Struct containing variables accessed by shared code
1411 *
1412 * Detects which PHY is present and sets up the speed and duplex
1413 */
e1000_setup_copper_link(struct e1000_hw * hw)1414 static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1415 {
1416 s32 ret_val;
1417 u16 i;
1418 u16 phy_data;
1419
1420 /* Check if it is a valid PHY and set PHY mode if necessary. */
1421 ret_val = e1000_copper_link_preconfig(hw);
1422 if (ret_val)
1423 return ret_val;
1424
1425 if (hw->phy_type == e1000_phy_igp) {
1426 ret_val = e1000_copper_link_igp_setup(hw);
1427 if (ret_val)
1428 return ret_val;
1429 } else if (hw->phy_type == e1000_phy_m88) {
1430 ret_val = e1000_copper_link_mgp_setup(hw);
1431 if (ret_val)
1432 return ret_val;
1433 } else {
1434 ret_val = gbe_dhg_phy_setup(hw);
1435 if (ret_val) {
1436 e_dbg("gbe_dhg_phy_setup failed!\n");
1437 return ret_val;
1438 }
1439 }
1440
1441 if (hw->autoneg) {
1442 /* Setup autoneg and flow control advertisement
1443 * and perform autonegotiation
1444 */
1445 ret_val = e1000_copper_link_autoneg(hw);
1446 if (ret_val)
1447 return ret_val;
1448 } else {
1449 /* PHY will be set to 10H, 10F, 100H,or 100F
1450 * depending on value from forced_speed_duplex.
1451 */
1452 e_dbg("Forcing speed and duplex\n");
1453 ret_val = e1000_phy_force_speed_duplex(hw);
1454 if (ret_val) {
1455 e_dbg("Error Forcing Speed and Duplex\n");
1456 return ret_val;
1457 }
1458 }
1459
1460 /* Check link status. Wait up to 100 microseconds for link to become
1461 * valid.
1462 */
1463 for (i = 0; i < 10; i++) {
1464 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1465 if (ret_val)
1466 return ret_val;
1467 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1468 if (ret_val)
1469 return ret_val;
1470
1471 if (phy_data & MII_SR_LINK_STATUS) {
1472 /* Config the MAC and PHY after link is up */
1473 ret_val = e1000_copper_link_postconfig(hw);
1474 if (ret_val)
1475 return ret_val;
1476
1477 e_dbg("Valid link established!!!\n");
1478 return E1000_SUCCESS;
1479 }
1480 udelay(10);
1481 }
1482
1483 e_dbg("Unable to establish link!!!\n");
1484 return E1000_SUCCESS;
1485 }
1486
1487 /**
1488 * e1000_phy_setup_autoneg - phy settings
1489 * @hw: Struct containing variables accessed by shared code
1490 *
1491 * Configures PHY autoneg and flow control advertisement settings
1492 */
e1000_phy_setup_autoneg(struct e1000_hw * hw)1493 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1494 {
1495 s32 ret_val;
1496 u16 mii_autoneg_adv_reg;
1497 u16 mii_1000t_ctrl_reg;
1498
1499 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1500 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1501 if (ret_val)
1502 return ret_val;
1503
1504 /* Read the MII 1000Base-T Control Register (Address 9). */
1505 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1506 if (ret_val)
1507 return ret_val;
1508 else if (hw->phy_type == e1000_phy_8201)
1509 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1510
1511 /* Need to parse both autoneg_advertised and fc and set up
1512 * the appropriate PHY registers. First we will parse for
1513 * autoneg_advertised software override. Since we can advertise
1514 * a plethora of combinations, we need to check each bit
1515 * individually.
1516 */
1517
1518 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1519 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1520 * the 1000Base-T Control Register (Address 9).
1521 */
1522 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1523 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1524
1525 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised);
1526
1527 /* Do we want to advertise 10 Mb Half Duplex? */
1528 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1529 e_dbg("Advertise 10mb Half duplex\n");
1530 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1531 }
1532
1533 /* Do we want to advertise 10 Mb Full Duplex? */
1534 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1535 e_dbg("Advertise 10mb Full duplex\n");
1536 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1537 }
1538
1539 /* Do we want to advertise 100 Mb Half Duplex? */
1540 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1541 e_dbg("Advertise 100mb Half duplex\n");
1542 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1543 }
1544
1545 /* Do we want to advertise 100 Mb Full Duplex? */
1546 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1547 e_dbg("Advertise 100mb Full duplex\n");
1548 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1549 }
1550
1551 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1552 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1553 e_dbg
1554 ("Advertise 1000mb Half duplex requested, request denied!\n");
1555 }
1556
1557 /* Do we want to advertise 1000 Mb Full Duplex? */
1558 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1559 e_dbg("Advertise 1000mb Full duplex\n");
1560 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1561 }
1562
1563 /* Check for a software override of the flow control settings, and
1564 * setup the PHY advertisement registers accordingly. If
1565 * auto-negotiation is enabled, then software will have to set the
1566 * "PAUSE" bits to the correct value in the Auto-Negotiation
1567 * Advertisement Register (PHY_AUTONEG_ADV) and re-start
1568 * auto-negotiation.
1569 *
1570 * The possible values of the "fc" parameter are:
1571 * 0: Flow control is completely disabled
1572 * 1: Rx flow control is enabled (we can receive pause frames
1573 * but not send pause frames).
1574 * 2: Tx flow control is enabled (we can send pause frames
1575 * but we do not support receiving pause frames).
1576 * 3: Both Rx and TX flow control (symmetric) are enabled.
1577 * other: No software override. The flow control configuration
1578 * in the EEPROM is used.
1579 */
1580 switch (hw->fc) {
1581 case E1000_FC_NONE: /* 0 */
1582 /* Flow control (RX & TX) is completely disabled by a
1583 * software over-ride.
1584 */
1585 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1586 break;
1587 case E1000_FC_RX_PAUSE: /* 1 */
1588 /* RX Flow control is enabled, and TX Flow control is
1589 * disabled, by a software over-ride.
1590 */
1591 /* Since there really isn't a way to advertise that we are
1592 * capable of RX Pause ONLY, we will advertise that we
1593 * support both symmetric and asymmetric RX PAUSE. Later
1594 * (in e1000_config_fc_after_link_up) we will disable the
1595 * hw's ability to send PAUSE frames.
1596 */
1597 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1598 break;
1599 case E1000_FC_TX_PAUSE: /* 2 */
1600 /* TX Flow control is enabled, and RX Flow control is
1601 * disabled, by a software over-ride.
1602 */
1603 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1604 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1605 break;
1606 case E1000_FC_FULL: /* 3 */
1607 /* Flow control (both RX and TX) is enabled by a software
1608 * over-ride.
1609 */
1610 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1611 break;
1612 default:
1613 e_dbg("Flow control param set incorrectly\n");
1614 return -E1000_ERR_CONFIG;
1615 }
1616
1617 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1618 if (ret_val)
1619 return ret_val;
1620
1621 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1622
1623 if (hw->phy_type == e1000_phy_8201) {
1624 mii_1000t_ctrl_reg = 0;
1625 } else {
1626 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1627 mii_1000t_ctrl_reg);
1628 if (ret_val)
1629 return ret_val;
1630 }
1631
1632 return E1000_SUCCESS;
1633 }
1634
1635 /**
1636 * e1000_phy_force_speed_duplex - force link settings
1637 * @hw: Struct containing variables accessed by shared code
1638 *
1639 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1640 */
e1000_phy_force_speed_duplex(struct e1000_hw * hw)1641 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1642 {
1643 u32 ctrl;
1644 s32 ret_val;
1645 u16 mii_ctrl_reg;
1646 u16 mii_status_reg;
1647 u16 phy_data;
1648 u16 i;
1649
1650 /* Turn off Flow control if we are forcing speed and duplex. */
1651 hw->fc = E1000_FC_NONE;
1652
1653 e_dbg("hw->fc = %d\n", hw->fc);
1654
1655 /* Read the Device Control Register. */
1656 ctrl = er32(CTRL);
1657
1658 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1659 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1660 ctrl &= ~(DEVICE_SPEED_MASK);
1661
1662 /* Clear the Auto Speed Detect Enable bit. */
1663 ctrl &= ~E1000_CTRL_ASDE;
1664
1665 /* Read the MII Control Register. */
1666 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1667 if (ret_val)
1668 return ret_val;
1669
1670 /* We need to disable autoneg in order to force link and duplex. */
1671
1672 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1673
1674 /* Are we forcing Full or Half Duplex? */
1675 if (hw->forced_speed_duplex == e1000_100_full ||
1676 hw->forced_speed_duplex == e1000_10_full) {
1677 /* We want to force full duplex so we SET the full duplex bits
1678 * in the Device and MII Control Registers.
1679 */
1680 ctrl |= E1000_CTRL_FD;
1681 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1682 e_dbg("Full Duplex\n");
1683 } else {
1684 /* We want to force half duplex so we CLEAR the full duplex bits
1685 * in the Device and MII Control Registers.
1686 */
1687 ctrl &= ~E1000_CTRL_FD;
1688 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1689 e_dbg("Half Duplex\n");
1690 }
1691
1692 /* Are we forcing 100Mbps??? */
1693 if (hw->forced_speed_duplex == e1000_100_full ||
1694 hw->forced_speed_duplex == e1000_100_half) {
1695 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1696 ctrl |= E1000_CTRL_SPD_100;
1697 mii_ctrl_reg |= MII_CR_SPEED_100;
1698 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1699 e_dbg("Forcing 100mb ");
1700 } else {
1701 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1702 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1703 mii_ctrl_reg |= MII_CR_SPEED_10;
1704 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1705 e_dbg("Forcing 10mb ");
1706 }
1707
1708 e1000_config_collision_dist(hw);
1709
1710 /* Write the configured values back to the Device Control Reg. */
1711 ew32(CTRL, ctrl);
1712
1713 if (hw->phy_type == e1000_phy_m88) {
1714 ret_val =
1715 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1716 if (ret_val)
1717 return ret_val;
1718
1719 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires
1720 * MDI forced whenever speed are duplex are forced.
1721 */
1722 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1723 ret_val =
1724 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1725 if (ret_val)
1726 return ret_val;
1727
1728 e_dbg("M88E1000 PSCR: %x\n", phy_data);
1729
1730 /* Need to reset the PHY or these changes will be ignored */
1731 mii_ctrl_reg |= MII_CR_RESET;
1732
1733 /* Disable MDI-X support for 10/100 */
1734 } else {
1735 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1736 * forced whenever speed or duplex are forced.
1737 */
1738 ret_val =
1739 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1740 if (ret_val)
1741 return ret_val;
1742
1743 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1744 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1745
1746 ret_val =
1747 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1748 if (ret_val)
1749 return ret_val;
1750 }
1751
1752 /* Write back the modified PHY MII control register. */
1753 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1754 if (ret_val)
1755 return ret_val;
1756
1757 udelay(1);
1758
1759 /* The wait_autoneg_complete flag may be a little misleading here.
1760 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1761 * But we do want to delay for a period while forcing only so we
1762 * don't generate false No Link messages. So we will wait here
1763 * only if the user has set wait_autoneg_complete to 1, which is
1764 * the default.
1765 */
1766 if (hw->wait_autoneg_complete) {
1767 /* We will wait for autoneg to complete. */
1768 e_dbg("Waiting for forced speed/duplex link.\n");
1769 mii_status_reg = 0;
1770
1771 /* Wait for autoneg to complete or 4.5 seconds to expire */
1772 for (i = PHY_FORCE_TIME; i > 0; i--) {
1773 /* Read the MII Status Register and wait for Auto-Neg
1774 * Complete bit to be set.
1775 */
1776 ret_val =
1777 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1778 if (ret_val)
1779 return ret_val;
1780
1781 ret_val =
1782 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1783 if (ret_val)
1784 return ret_val;
1785
1786 if (mii_status_reg & MII_SR_LINK_STATUS)
1787 break;
1788 msleep(100);
1789 }
1790 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {
1791 /* We didn't get link. Reset the DSP and wait again
1792 * for link.
1793 */
1794 ret_val = e1000_phy_reset_dsp(hw);
1795 if (ret_val) {
1796 e_dbg("Error Resetting PHY DSP\n");
1797 return ret_val;
1798 }
1799 }
1800 /* This loop will early-out if the link condition has been
1801 * met
1802 */
1803 for (i = PHY_FORCE_TIME; i > 0; i--) {
1804 if (mii_status_reg & MII_SR_LINK_STATUS)
1805 break;
1806 msleep(100);
1807 /* Read the MII Status Register and wait for Auto-Neg
1808 * Complete bit to be set.
1809 */
1810 ret_val =
1811 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1812 if (ret_val)
1813 return ret_val;
1814
1815 ret_val =
1816 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1817 if (ret_val)
1818 return ret_val;
1819 }
1820 }
1821
1822 if (hw->phy_type == e1000_phy_m88) {
1823 /* Because we reset the PHY above, we need to re-force TX_CLK in
1824 * the Extended PHY Specific Control Register to 25MHz clock.
1825 * This value defaults back to a 2.5MHz clock when the PHY is
1826 * reset.
1827 */
1828 ret_val =
1829 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1830 &phy_data);
1831 if (ret_val)
1832 return ret_val;
1833
1834 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1835 ret_val =
1836 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1837 phy_data);
1838 if (ret_val)
1839 return ret_val;
1840
1841 /* In addition, because of the s/w reset above, we need to
1842 * enable CRS on Tx. This must be set for both full and half
1843 * duplex operation.
1844 */
1845 ret_val =
1846 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1847 if (ret_val)
1848 return ret_val;
1849
1850 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1851 ret_val =
1852 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1853 if (ret_val)
1854 return ret_val;
1855
1856 if ((hw->mac_type == e1000_82544 ||
1857 hw->mac_type == e1000_82543) &&
1858 (!hw->autoneg) &&
1859 (hw->forced_speed_duplex == e1000_10_full ||
1860 hw->forced_speed_duplex == e1000_10_half)) {
1861 ret_val = e1000_polarity_reversal_workaround(hw);
1862 if (ret_val)
1863 return ret_val;
1864 }
1865 }
1866 return E1000_SUCCESS;
1867 }
1868
1869 /**
1870 * e1000_config_collision_dist - set collision distance register
1871 * @hw: Struct containing variables accessed by shared code
1872 *
1873 * Sets the collision distance in the Transmit Control register.
1874 * Link should have been established previously. Reads the speed and duplex
1875 * information from the Device Status register.
1876 */
e1000_config_collision_dist(struct e1000_hw * hw)1877 void e1000_config_collision_dist(struct e1000_hw *hw)
1878 {
1879 u32 tctl, coll_dist;
1880
1881 if (hw->mac_type < e1000_82543)
1882 coll_dist = E1000_COLLISION_DISTANCE_82542;
1883 else
1884 coll_dist = E1000_COLLISION_DISTANCE;
1885
1886 tctl = er32(TCTL);
1887
1888 tctl &= ~E1000_TCTL_COLD;
1889 tctl |= coll_dist << E1000_COLD_SHIFT;
1890
1891 ew32(TCTL, tctl);
1892 E1000_WRITE_FLUSH();
1893 }
1894
1895 /**
1896 * e1000_config_mac_to_phy - sync phy and mac settings
1897 * @hw: Struct containing variables accessed by shared code
1898 *
1899 * Sets MAC speed and duplex settings to reflect the those in the PHY
1900 * The contents of the PHY register containing the needed information need to
1901 * be passed in.
1902 */
e1000_config_mac_to_phy(struct e1000_hw * hw)1903 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
1904 {
1905 u32 ctrl;
1906 s32 ret_val;
1907 u16 phy_data;
1908
1909 /* 82544 or newer MAC, Auto Speed Detection takes care of
1910 * MAC speed/duplex configuration.
1911 */
1912 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100))
1913 return E1000_SUCCESS;
1914
1915 /* Read the Device Control Register and set the bits to Force Speed
1916 * and Duplex.
1917 */
1918 ctrl = er32(CTRL);
1919 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1920 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1921
1922 switch (hw->phy_type) {
1923 case e1000_phy_8201:
1924 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1925 if (ret_val)
1926 return ret_val;
1927
1928 if (phy_data & RTL_PHY_CTRL_FD)
1929 ctrl |= E1000_CTRL_FD;
1930 else
1931 ctrl &= ~E1000_CTRL_FD;
1932
1933 if (phy_data & RTL_PHY_CTRL_SPD_100)
1934 ctrl |= E1000_CTRL_SPD_100;
1935 else
1936 ctrl |= E1000_CTRL_SPD_10;
1937
1938 e1000_config_collision_dist(hw);
1939 break;
1940 default:
1941 /* Set up duplex in the Device Control and Transmit Control
1942 * registers depending on negotiated values.
1943 */
1944 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1945 &phy_data);
1946 if (ret_val)
1947 return ret_val;
1948
1949 if (phy_data & M88E1000_PSSR_DPLX)
1950 ctrl |= E1000_CTRL_FD;
1951 else
1952 ctrl &= ~E1000_CTRL_FD;
1953
1954 e1000_config_collision_dist(hw);
1955
1956 /* Set up speed in the Device Control register depending on
1957 * negotiated values.
1958 */
1959 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1960 ctrl |= E1000_CTRL_SPD_1000;
1961 else if ((phy_data & M88E1000_PSSR_SPEED) ==
1962 M88E1000_PSSR_100MBS)
1963 ctrl |= E1000_CTRL_SPD_100;
1964 }
1965
1966 /* Write the configured values back to the Device Control Reg. */
1967 ew32(CTRL, ctrl);
1968 return E1000_SUCCESS;
1969 }
1970
1971 /**
1972 * e1000_force_mac_fc - force flow control settings
1973 * @hw: Struct containing variables accessed by shared code
1974 *
1975 * Forces the MAC's flow control settings.
1976 * Sets the TFCE and RFCE bits in the device control register to reflect
1977 * the adapter settings. TFCE and RFCE need to be explicitly set by
1978 * software when a Copper PHY is used because autonegotiation is managed
1979 * by the PHY rather than the MAC. Software must also configure these
1980 * bits when link is forced on a fiber connection.
1981 */
e1000_force_mac_fc(struct e1000_hw * hw)1982 s32 e1000_force_mac_fc(struct e1000_hw *hw)
1983 {
1984 u32 ctrl;
1985
1986 /* Get the current configuration of the Device Control Register */
1987 ctrl = er32(CTRL);
1988
1989 /* Because we didn't get link via the internal auto-negotiation
1990 * mechanism (we either forced link or we got link via PHY
1991 * auto-neg), we have to manually enable/disable transmit an
1992 * receive flow control.
1993 *
1994 * The "Case" statement below enables/disable flow control
1995 * according to the "hw->fc" parameter.
1996 *
1997 * The possible values of the "fc" parameter are:
1998 * 0: Flow control is completely disabled
1999 * 1: Rx flow control is enabled (we can receive pause
2000 * frames but not send pause frames).
2001 * 2: Tx flow control is enabled (we can send pause frames
2002 * frames but we do not receive pause frames).
2003 * 3: Both Rx and TX flow control (symmetric) is enabled.
2004 * other: No other values should be possible at this point.
2005 */
2006
2007 switch (hw->fc) {
2008 case E1000_FC_NONE:
2009 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2010 break;
2011 case E1000_FC_RX_PAUSE:
2012 ctrl &= (~E1000_CTRL_TFCE);
2013 ctrl |= E1000_CTRL_RFCE;
2014 break;
2015 case E1000_FC_TX_PAUSE:
2016 ctrl &= (~E1000_CTRL_RFCE);
2017 ctrl |= E1000_CTRL_TFCE;
2018 break;
2019 case E1000_FC_FULL:
2020 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2021 break;
2022 default:
2023 e_dbg("Flow control param set incorrectly\n");
2024 return -E1000_ERR_CONFIG;
2025 }
2026
2027 /* Disable TX Flow Control for 82542 (rev 2.0) */
2028 if (hw->mac_type == e1000_82542_rev2_0)
2029 ctrl &= (~E1000_CTRL_TFCE);
2030
2031 ew32(CTRL, ctrl);
2032 return E1000_SUCCESS;
2033 }
2034
2035 /**
2036 * e1000_config_fc_after_link_up - configure flow control after autoneg
2037 * @hw: Struct containing variables accessed by shared code
2038 *
2039 * Configures flow control settings after link is established
2040 * Should be called immediately after a valid link has been established.
2041 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2042 * and autonegotiation is enabled, the MAC flow control settings will be set
2043 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2044 * and RFCE bits will be automatically set to the negotiated flow control mode.
2045 */
e1000_config_fc_after_link_up(struct e1000_hw * hw)2046 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2047 {
2048 s32 ret_val;
2049 u16 mii_status_reg;
2050 u16 mii_nway_adv_reg;
2051 u16 mii_nway_lp_ability_reg;
2052 u16 speed;
2053 u16 duplex;
2054
2055 /* Check for the case where we have fiber media and auto-neg failed
2056 * so we had to force link. In this case, we need to force the
2057 * configuration of the MAC to match the "fc" parameter.
2058 */
2059 if (((hw->media_type == e1000_media_type_fiber) &&
2060 (hw->autoneg_failed)) ||
2061 ((hw->media_type == e1000_media_type_internal_serdes) &&
2062 (hw->autoneg_failed)) ||
2063 ((hw->media_type == e1000_media_type_copper) &&
2064 (!hw->autoneg))) {
2065 ret_val = e1000_force_mac_fc(hw);
2066 if (ret_val) {
2067 e_dbg("Error forcing flow control settings\n");
2068 return ret_val;
2069 }
2070 }
2071
2072 /* Check for the case where we have copper media and auto-neg is
2073 * enabled. In this case, we need to check and see if Auto-Neg
2074 * has completed, and if so, how the PHY and link partner has
2075 * flow control configured.
2076 */
2077 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2078 /* Read the MII Status Register and check to see if AutoNeg
2079 * has completed. We read this twice because this reg has
2080 * some "sticky" (latched) bits.
2081 */
2082 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2083 if (ret_val)
2084 return ret_val;
2085 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2086 if (ret_val)
2087 return ret_val;
2088
2089 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2090 /* The AutoNeg process has completed, so we now need to
2091 * read both the Auto Negotiation Advertisement Register
2092 * (Address 4) and the Auto_Negotiation Base Page
2093 * Ability Register (Address 5) to determine how flow
2094 * control was negotiated.
2095 */
2096 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2097 &mii_nway_adv_reg);
2098 if (ret_val)
2099 return ret_val;
2100 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2101 &mii_nway_lp_ability_reg);
2102 if (ret_val)
2103 return ret_val;
2104
2105 /* Two bits in the Auto Negotiation Advertisement
2106 * Register (Address 4) and two bits in the Auto
2107 * Negotiation Base Page Ability Register (Address 5)
2108 * determine flow control for both the PHY and the link
2109 * partner. The following table, taken out of the IEEE
2110 * 802.3ab/D6.0 dated March 25, 1999, describes these
2111 * PAUSE resolution bits and how flow control is
2112 * determined based upon these settings.
2113 * NOTE: DC = Don't Care
2114 *
2115 * LOCAL DEVICE | LINK PARTNER
2116 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2117 *-------|---------|-------|---------|------------------
2118 * 0 | 0 | DC | DC | E1000_FC_NONE
2119 * 0 | 1 | 0 | DC | E1000_FC_NONE
2120 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2121 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2122 * 1 | 0 | 0 | DC | E1000_FC_NONE
2123 * 1 | DC | 1 | DC | E1000_FC_FULL
2124 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2125 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2126 *
2127 */
2128 /* Are both PAUSE bits set to 1? If so, this implies
2129 * Symmetric Flow Control is enabled at both ends. The
2130 * ASM_DIR bits are irrelevant per the spec.
2131 *
2132 * For Symmetric Flow Control:
2133 *
2134 * LOCAL DEVICE | LINK PARTNER
2135 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2136 *-------|---------|-------|---------|------------------
2137 * 1 | DC | 1 | DC | E1000_FC_FULL
2138 *
2139 */
2140 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2141 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2142 /* Now we need to check if the user selected Rx
2143 * ONLY of pause frames. In this case, we had
2144 * to advertise FULL flow control because we
2145 * could not advertise Rx ONLY. Hence, we must
2146 * now check to see if we need to turn OFF the
2147 * TRANSMISSION of PAUSE frames.
2148 */
2149 if (hw->original_fc == E1000_FC_FULL) {
2150 hw->fc = E1000_FC_FULL;
2151 e_dbg("Flow Control = FULL.\n");
2152 } else {
2153 hw->fc = E1000_FC_RX_PAUSE;
2154 e_dbg
2155 ("Flow Control = RX PAUSE frames only.\n");
2156 }
2157 }
2158 /* For receiving PAUSE frames ONLY.
2159 *
2160 * LOCAL DEVICE | LINK PARTNER
2161 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2162 *-------|---------|-------|---------|------------------
2163 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2164 *
2165 */
2166 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2167 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2168 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2169 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2170 hw->fc = E1000_FC_TX_PAUSE;
2171 e_dbg
2172 ("Flow Control = TX PAUSE frames only.\n");
2173 }
2174 /* For transmitting PAUSE frames ONLY.
2175 *
2176 * LOCAL DEVICE | LINK PARTNER
2177 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2178 *-------|---------|-------|---------|------------------
2179 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2180 *
2181 */
2182 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2183 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2184 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2185 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2186 hw->fc = E1000_FC_RX_PAUSE;
2187 e_dbg
2188 ("Flow Control = RX PAUSE frames only.\n");
2189 }
2190 /* Per the IEEE spec, at this point flow control should
2191 * be disabled. However, we want to consider that we
2192 * could be connected to a legacy switch that doesn't
2193 * advertise desired flow control, but can be forced on
2194 * the link partner. So if we advertised no flow
2195 * control, that is what we will resolve to. If we
2196 * advertised some kind of receive capability (Rx Pause
2197 * Only or Full Flow Control) and the link partner
2198 * advertised none, we will configure ourselves to
2199 * enable Rx Flow Control only. We can do this safely
2200 * for two reasons: If the link partner really
2201 * didn't want flow control enabled, and we enable Rx,
2202 * no harm done since we won't be receiving any PAUSE
2203 * frames anyway. If the intent on the link partner was
2204 * to have flow control enabled, then by us enabling Rx
2205 * only, we can at least receive pause frames and
2206 * process them. This is a good idea because in most
2207 * cases, since we are predominantly a server NIC, more
2208 * times than not we will be asked to delay transmission
2209 * of packets than asking our link partner to pause
2210 * transmission of frames.
2211 */
2212 else if ((hw->original_fc == E1000_FC_NONE ||
2213 hw->original_fc == E1000_FC_TX_PAUSE) ||
2214 hw->fc_strict_ieee) {
2215 hw->fc = E1000_FC_NONE;
2216 e_dbg("Flow Control = NONE.\n");
2217 } else {
2218 hw->fc = E1000_FC_RX_PAUSE;
2219 e_dbg
2220 ("Flow Control = RX PAUSE frames only.\n");
2221 }
2222
2223 /* Now we need to do one last check... If we auto-
2224 * negotiated to HALF DUPLEX, flow control should not be
2225 * enabled per IEEE 802.3 spec.
2226 */
2227 ret_val =
2228 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2229 if (ret_val) {
2230 e_dbg
2231 ("Error getting link speed and duplex\n");
2232 return ret_val;
2233 }
2234
2235 if (duplex == HALF_DUPLEX)
2236 hw->fc = E1000_FC_NONE;
2237
2238 /* Now we call a subroutine to actually force the MAC
2239 * controller to use the correct flow control settings.
2240 */
2241 ret_val = e1000_force_mac_fc(hw);
2242 if (ret_val) {
2243 e_dbg
2244 ("Error forcing flow control settings\n");
2245 return ret_val;
2246 }
2247 } else {
2248 e_dbg
2249 ("Copper PHY and Auto Neg has not completed.\n");
2250 }
2251 }
2252 return E1000_SUCCESS;
2253 }
2254
2255 /**
2256 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
2257 * @hw: pointer to the HW structure
2258 *
2259 * Checks for link up on the hardware. If link is not up and we have
2260 * a signal, then we need to force link up.
2261 */
e1000_check_for_serdes_link_generic(struct e1000_hw * hw)2262 static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2263 {
2264 u32 rxcw;
2265 u32 ctrl;
2266 u32 status;
2267 s32 ret_val = E1000_SUCCESS;
2268
2269 ctrl = er32(CTRL);
2270 status = er32(STATUS);
2271 rxcw = er32(RXCW);
2272
2273 /* If we don't have link (auto-negotiation failed or link partner
2274 * cannot auto-negotiate), and our link partner is not trying to
2275 * auto-negotiate with us (we are receiving idles or data),
2276 * we need to force link up. We also need to give auto-negotiation
2277 * time to complete.
2278 */
2279 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
2280 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
2281 if (hw->autoneg_failed == 0) {
2282 hw->autoneg_failed = 1;
2283 goto out;
2284 }
2285 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
2286
2287 /* Disable auto-negotiation in the TXCW register */
2288 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2289
2290 /* Force link-up and also force full-duplex. */
2291 ctrl = er32(CTRL);
2292 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2293 ew32(CTRL, ctrl);
2294
2295 /* Configure Flow Control after forcing link up. */
2296 ret_val = e1000_config_fc_after_link_up(hw);
2297 if (ret_val) {
2298 e_dbg("Error configuring flow control\n");
2299 goto out;
2300 }
2301 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2302 /* If we are forcing link and we are receiving /C/ ordered
2303 * sets, re-enable auto-negotiation in the TXCW register
2304 * and disable forced link in the Device Control register
2305 * in an attempt to auto-negotiate with our link partner.
2306 */
2307 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
2308 ew32(TXCW, hw->txcw);
2309 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
2310
2311 hw->serdes_has_link = true;
2312 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
2313 /* If we force link for non-auto-negotiation switch, check
2314 * link status based on MAC synchronization for internal
2315 * serdes media type.
2316 */
2317 /* SYNCH bit and IV bit are sticky. */
2318 udelay(10);
2319 rxcw = er32(RXCW);
2320 if (rxcw & E1000_RXCW_SYNCH) {
2321 if (!(rxcw & E1000_RXCW_IV)) {
2322 hw->serdes_has_link = true;
2323 e_dbg("SERDES: Link up - forced.\n");
2324 }
2325 } else {
2326 hw->serdes_has_link = false;
2327 e_dbg("SERDES: Link down - force failed.\n");
2328 }
2329 }
2330
2331 if (E1000_TXCW_ANE & er32(TXCW)) {
2332 status = er32(STATUS);
2333 if (status & E1000_STATUS_LU) {
2334 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
2335 udelay(10);
2336 rxcw = er32(RXCW);
2337 if (rxcw & E1000_RXCW_SYNCH) {
2338 if (!(rxcw & E1000_RXCW_IV)) {
2339 hw->serdes_has_link = true;
2340 e_dbg("SERDES: Link up - autoneg "
2341 "completed successfully.\n");
2342 } else {
2343 hw->serdes_has_link = false;
2344 e_dbg("SERDES: Link down - invalid"
2345 "codewords detected in autoneg.\n");
2346 }
2347 } else {
2348 hw->serdes_has_link = false;
2349 e_dbg("SERDES: Link down - no sync.\n");
2350 }
2351 } else {
2352 hw->serdes_has_link = false;
2353 e_dbg("SERDES: Link down - autoneg failed\n");
2354 }
2355 }
2356
2357 out:
2358 return ret_val;
2359 }
2360
2361 /**
2362 * e1000_check_for_link
2363 * @hw: Struct containing variables accessed by shared code
2364 *
2365 * Checks to see if the link status of the hardware has changed.
2366 * Called by any function that needs to check the link status of the adapter.
2367 */
e1000_check_for_link(struct e1000_hw * hw)2368 s32 e1000_check_for_link(struct e1000_hw *hw)
2369 {
2370 u32 status;
2371 u32 rctl;
2372 u32 icr;
2373 s32 ret_val;
2374 u16 phy_data;
2375
2376 er32(CTRL);
2377 status = er32(STATUS);
2378
2379 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be
2380 * set when the optics detect a signal. On older adapters, it will be
2381 * cleared when there is a signal. This applies to fiber media only.
2382 */
2383 if ((hw->media_type == e1000_media_type_fiber) ||
2384 (hw->media_type == e1000_media_type_internal_serdes)) {
2385 er32(RXCW);
2386
2387 if (hw->media_type == e1000_media_type_fiber) {
2388 if (status & E1000_STATUS_LU)
2389 hw->get_link_status = false;
2390 }
2391 }
2392
2393 /* If we have a copper PHY then we only want to go out to the PHY
2394 * registers to see if Auto-Neg has completed and/or if our link
2395 * status has changed. The get_link_status flag will be set if we
2396 * receive a Link Status Change interrupt or we have Rx Sequence
2397 * Errors.
2398 */
2399 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2400 /* First we want to see if the MII Status Register reports
2401 * link. If so, then we want to get the current speed/duplex
2402 * of the PHY.
2403 * Read the register twice since the link bit is sticky.
2404 */
2405 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2406 if (ret_val)
2407 return ret_val;
2408 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2409 if (ret_val)
2410 return ret_val;
2411
2412 if (phy_data & MII_SR_LINK_STATUS) {
2413 hw->get_link_status = false;
2414 /* Check if there was DownShift, must be checked
2415 * immediately after link-up
2416 */
2417 e1000_check_downshift(hw);
2418
2419 /* If we are on 82544 or 82543 silicon and speed/duplex
2420 * are forced to 10H or 10F, then we will implement the
2421 * polarity reversal workaround. We disable interrupts
2422 * first, and upon returning, place the devices
2423 * interrupt state to its previous value except for the
2424 * link status change interrupt which will
2425 * happen due to the execution of this workaround.
2426 */
2427
2428 if ((hw->mac_type == e1000_82544 ||
2429 hw->mac_type == e1000_82543) &&
2430 (!hw->autoneg) &&
2431 (hw->forced_speed_duplex == e1000_10_full ||
2432 hw->forced_speed_duplex == e1000_10_half)) {
2433 ew32(IMC, 0xffffffff);
2434 ret_val =
2435 e1000_polarity_reversal_workaround(hw);
2436 icr = er32(ICR);
2437 ew32(ICS, (icr & ~E1000_ICS_LSC));
2438 ew32(IMS, IMS_ENABLE_MASK);
2439 }
2440
2441 } else {
2442 /* No link detected */
2443 e1000_config_dsp_after_link_change(hw, false);
2444 return 0;
2445 }
2446
2447 /* If we are forcing speed/duplex, then we simply return since
2448 * we have already determined whether we have link or not.
2449 */
2450 if (!hw->autoneg)
2451 return -E1000_ERR_CONFIG;
2452
2453 /* optimize the dsp settings for the igp phy */
2454 e1000_config_dsp_after_link_change(hw, true);
2455
2456 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2457 * have Si on board that is 82544 or newer, Auto
2458 * Speed Detection takes care of MAC speed/duplex
2459 * configuration. So we only need to configure Collision
2460 * Distance in the MAC. Otherwise, we need to force
2461 * speed/duplex on the MAC to the current PHY speed/duplex
2462 * settings.
2463 */
2464 if ((hw->mac_type >= e1000_82544) &&
2465 (hw->mac_type != e1000_ce4100))
2466 e1000_config_collision_dist(hw);
2467 else {
2468 ret_val = e1000_config_mac_to_phy(hw);
2469 if (ret_val) {
2470 e_dbg
2471 ("Error configuring MAC to PHY settings\n");
2472 return ret_val;
2473 }
2474 }
2475
2476 /* Configure Flow Control now that Auto-Neg has completed.
2477 * First, we need to restore the desired flow control settings
2478 * because we may have had to re-autoneg with a different link
2479 * partner.
2480 */
2481 ret_val = e1000_config_fc_after_link_up(hw);
2482 if (ret_val) {
2483 e_dbg("Error configuring flow control\n");
2484 return ret_val;
2485 }
2486
2487 /* At this point we know that we are on copper and we have
2488 * auto-negotiated link. These are conditions for checking the
2489 * link partner capability register. We use the link speed to
2490 * determine if TBI compatibility needs to be turned on or off.
2491 * If the link is not at gigabit speed, then TBI compatibility
2492 * is not needed. If we are at gigabit speed, we turn on TBI
2493 * compatibility.
2494 */
2495 if (hw->tbi_compatibility_en) {
2496 u16 speed, duplex;
2497
2498 ret_val =
2499 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2500
2501 if (ret_val) {
2502 e_dbg
2503 ("Error getting link speed and duplex\n");
2504 return ret_val;
2505 }
2506 if (speed != SPEED_1000) {
2507 /* If link speed is not set to gigabit speed, we
2508 * do not need to enable TBI compatibility.
2509 */
2510 if (hw->tbi_compatibility_on) {
2511 /* If we previously were in the mode,
2512 * turn it off.
2513 */
2514 rctl = er32(RCTL);
2515 rctl &= ~E1000_RCTL_SBP;
2516 ew32(RCTL, rctl);
2517 hw->tbi_compatibility_on = false;
2518 }
2519 } else {
2520 /* If TBI compatibility is was previously off,
2521 * turn it on. For compatibility with a TBI link
2522 * partner, we will store bad packets. Some
2523 * frames have an additional byte on the end and
2524 * will look like CRC errors to to the hardware.
2525 */
2526 if (!hw->tbi_compatibility_on) {
2527 hw->tbi_compatibility_on = true;
2528 rctl = er32(RCTL);
2529 rctl |= E1000_RCTL_SBP;
2530 ew32(RCTL, rctl);
2531 }
2532 }
2533 }
2534 }
2535
2536 if ((hw->media_type == e1000_media_type_fiber) ||
2537 (hw->media_type == e1000_media_type_internal_serdes))
2538 e1000_check_for_serdes_link_generic(hw);
2539
2540 return E1000_SUCCESS;
2541 }
2542
2543 /**
2544 * e1000_get_speed_and_duplex
2545 * @hw: Struct containing variables accessed by shared code
2546 * @speed: Speed of the connection
2547 * @duplex: Duplex setting of the connection
2548 *
2549 * Detects the current speed and duplex settings of the hardware.
2550 */
e1000_get_speed_and_duplex(struct e1000_hw * hw,u16 * speed,u16 * duplex)2551 s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
2552 {
2553 u32 status;
2554 s32 ret_val;
2555 u16 phy_data;
2556
2557 if (hw->mac_type >= e1000_82543) {
2558 status = er32(STATUS);
2559 if (status & E1000_STATUS_SPEED_1000) {
2560 *speed = SPEED_1000;
2561 e_dbg("1000 Mbs, ");
2562 } else if (status & E1000_STATUS_SPEED_100) {
2563 *speed = SPEED_100;
2564 e_dbg("100 Mbs, ");
2565 } else {
2566 *speed = SPEED_10;
2567 e_dbg("10 Mbs, ");
2568 }
2569
2570 if (status & E1000_STATUS_FD) {
2571 *duplex = FULL_DUPLEX;
2572 e_dbg("Full Duplex\n");
2573 } else {
2574 *duplex = HALF_DUPLEX;
2575 e_dbg(" Half Duplex\n");
2576 }
2577 } else {
2578 e_dbg("1000 Mbs, Full Duplex\n");
2579 *speed = SPEED_1000;
2580 *duplex = FULL_DUPLEX;
2581 }
2582
2583 /* IGP01 PHY may advertise full duplex operation after speed downgrade
2584 * even if it is operating at half duplex. Here we set the duplex
2585 * settings to match the duplex in the link partner's capabilities.
2586 */
2587 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2588 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2589 if (ret_val)
2590 return ret_val;
2591
2592 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2593 *duplex = HALF_DUPLEX;
2594 else {
2595 ret_val =
2596 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2597 if (ret_val)
2598 return ret_val;
2599 if ((*speed == SPEED_100 &&
2600 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2601 (*speed == SPEED_10 &&
2602 !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2603 *duplex = HALF_DUPLEX;
2604 }
2605 }
2606
2607 return E1000_SUCCESS;
2608 }
2609
2610 /**
2611 * e1000_wait_autoneg
2612 * @hw: Struct containing variables accessed by shared code
2613 *
2614 * Blocks until autoneg completes or times out (~4.5 seconds)
2615 */
e1000_wait_autoneg(struct e1000_hw * hw)2616 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2617 {
2618 s32 ret_val;
2619 u16 i;
2620 u16 phy_data;
2621
2622 e_dbg("Waiting for Auto-Neg to complete.\n");
2623
2624 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2625 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2626 /* Read the MII Status Register and wait for Auto-Neg
2627 * Complete bit to be set.
2628 */
2629 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2630 if (ret_val)
2631 return ret_val;
2632 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2633 if (ret_val)
2634 return ret_val;
2635 if (phy_data & MII_SR_AUTONEG_COMPLETE)
2636 return E1000_SUCCESS;
2637
2638 msleep(100);
2639 }
2640 return E1000_SUCCESS;
2641 }
2642
2643 /**
2644 * e1000_raise_mdi_clk - Raises the Management Data Clock
2645 * @hw: Struct containing variables accessed by shared code
2646 * @ctrl: Device control register's current value
2647 */
e1000_raise_mdi_clk(struct e1000_hw * hw,u32 * ctrl)2648 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2649 {
2650 /* Raise the clock input to the Management Data Clock (by setting the
2651 * MDC bit), and then delay 10 microseconds.
2652 */
2653 ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
2654 E1000_WRITE_FLUSH();
2655 udelay(10);
2656 }
2657
2658 /**
2659 * e1000_lower_mdi_clk - Lowers the Management Data Clock
2660 * @hw: Struct containing variables accessed by shared code
2661 * @ctrl: Device control register's current value
2662 */
e1000_lower_mdi_clk(struct e1000_hw * hw,u32 * ctrl)2663 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2664 {
2665 /* Lower the clock input to the Management Data Clock (by clearing the
2666 * MDC bit), and then delay 10 microseconds.
2667 */
2668 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
2669 E1000_WRITE_FLUSH();
2670 udelay(10);
2671 }
2672
2673 /**
2674 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY
2675 * @hw: Struct containing variables accessed by shared code
2676 * @data: Data to send out to the PHY
2677 * @count: Number of bits to shift out
2678 *
2679 * Bits are shifted out in MSB to LSB order.
2680 */
e1000_shift_out_mdi_bits(struct e1000_hw * hw,u32 data,u16 count)2681 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
2682 {
2683 u32 ctrl;
2684 u32 mask;
2685
2686 /* We need to shift "count" number of bits out to the PHY. So, the value
2687 * in the "data" parameter will be shifted out to the PHY one bit at a
2688 * time. In order to do this, "data" must be broken down into bits.
2689 */
2690 mask = 0x01;
2691 mask <<= (count - 1);
2692
2693 ctrl = er32(CTRL);
2694
2695 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2696 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2697
2698 while (mask) {
2699 /* A "1" is shifted out to the PHY by setting the MDIO bit to
2700 * "1" and then raising and lowering the Management Data Clock.
2701 * A "0" is shifted out to the PHY by setting the MDIO bit to
2702 * "0" and then raising and lowering the clock.
2703 */
2704 if (data & mask)
2705 ctrl |= E1000_CTRL_MDIO;
2706 else
2707 ctrl &= ~E1000_CTRL_MDIO;
2708
2709 ew32(CTRL, ctrl);
2710 E1000_WRITE_FLUSH();
2711
2712 udelay(10);
2713
2714 e1000_raise_mdi_clk(hw, &ctrl);
2715 e1000_lower_mdi_clk(hw, &ctrl);
2716
2717 mask = mask >> 1;
2718 }
2719 }
2720
2721 /**
2722 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY
2723 * @hw: Struct containing variables accessed by shared code
2724 *
2725 * Bits are shifted in in MSB to LSB order.
2726 */
e1000_shift_in_mdi_bits(struct e1000_hw * hw)2727 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2728 {
2729 u32 ctrl;
2730 u16 data = 0;
2731 u8 i;
2732
2733 /* In order to read a register from the PHY, we need to shift in a total
2734 * of 18 bits from the PHY. The first two bit (turnaround) times are
2735 * used to avoid contention on the MDIO pin when a read operation is
2736 * performed. These two bits are ignored by us and thrown away. Bits are
2737 * "shifted in" by raising the input to the Management Data Clock
2738 * (setting the MDC bit), and then reading the value of the MDIO bit.
2739 */
2740 ctrl = er32(CTRL);
2741
2742 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
2743 * input.
2744 */
2745 ctrl &= ~E1000_CTRL_MDIO_DIR;
2746 ctrl &= ~E1000_CTRL_MDIO;
2747
2748 ew32(CTRL, ctrl);
2749 E1000_WRITE_FLUSH();
2750
2751 /* Raise and Lower the clock before reading in the data. This accounts
2752 * for the turnaround bits. The first clock occurred when we clocked out
2753 * the last bit of the Register Address.
2754 */
2755 e1000_raise_mdi_clk(hw, &ctrl);
2756 e1000_lower_mdi_clk(hw, &ctrl);
2757
2758 for (data = 0, i = 0; i < 16; i++) {
2759 data = data << 1;
2760 e1000_raise_mdi_clk(hw, &ctrl);
2761 ctrl = er32(CTRL);
2762 /* Check to see if we shifted in a "1". */
2763 if (ctrl & E1000_CTRL_MDIO)
2764 data |= 1;
2765 e1000_lower_mdi_clk(hw, &ctrl);
2766 }
2767
2768 e1000_raise_mdi_clk(hw, &ctrl);
2769 e1000_lower_mdi_clk(hw, &ctrl);
2770
2771 return data;
2772 }
2773
2774 /**
2775 * e1000_read_phy_reg - read a phy register
2776 * @hw: Struct containing variables accessed by shared code
2777 * @reg_addr: address of the PHY register to read
2778 * @phy_data: pointer to the value on the PHY register
2779 *
2780 * Reads the value from a PHY register, if the value is on a specific non zero
2781 * page, sets the page first.
2782 */
e1000_read_phy_reg(struct e1000_hw * hw,u32 reg_addr,u16 * phy_data)2783 s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
2784 {
2785 u32 ret_val;
2786 unsigned long flags;
2787
2788 spin_lock_irqsave(&e1000_phy_lock, flags);
2789
2790 if ((hw->phy_type == e1000_phy_igp) &&
2791 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2792 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2793 (u16) reg_addr);
2794 if (ret_val)
2795 goto out;
2796 }
2797
2798 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2799 phy_data);
2800 out:
2801 spin_unlock_irqrestore(&e1000_phy_lock, flags);
2802
2803 return ret_val;
2804 }
2805
e1000_read_phy_reg_ex(struct e1000_hw * hw,u32 reg_addr,u16 * phy_data)2806 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2807 u16 *phy_data)
2808 {
2809 u32 i;
2810 u32 mdic = 0;
2811 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2812
2813 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2814 e_dbg("PHY Address %d is out of range\n", reg_addr);
2815 return -E1000_ERR_PARAM;
2816 }
2817
2818 if (hw->mac_type > e1000_82543) {
2819 /* Set up Op-code, Phy Address, and register address in the MDI
2820 * Control register. The MAC will take care of interfacing with
2821 * the PHY to retrieve the desired data.
2822 */
2823 if (hw->mac_type == e1000_ce4100) {
2824 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2825 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2826 (INTEL_CE_GBE_MDIC_OP_READ) |
2827 (INTEL_CE_GBE_MDIC_GO));
2828
2829 writel(mdic, E1000_MDIO_CMD);
2830
2831 /* Poll the ready bit to see if the MDI read
2832 * completed
2833 */
2834 for (i = 0; i < 64; i++) {
2835 udelay(50);
2836 mdic = readl(E1000_MDIO_CMD);
2837 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
2838 break;
2839 }
2840
2841 if (mdic & INTEL_CE_GBE_MDIC_GO) {
2842 e_dbg("MDI Read did not complete\n");
2843 return -E1000_ERR_PHY;
2844 }
2845
2846 mdic = readl(E1000_MDIO_STS);
2847 if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) {
2848 e_dbg("MDI Read Error\n");
2849 return -E1000_ERR_PHY;
2850 }
2851 *phy_data = (u16)mdic;
2852 } else {
2853 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2854 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2855 (E1000_MDIC_OP_READ));
2856
2857 ew32(MDIC, mdic);
2858
2859 /* Poll the ready bit to see if the MDI read
2860 * completed
2861 */
2862 for (i = 0; i < 64; i++) {
2863 udelay(50);
2864 mdic = er32(MDIC);
2865 if (mdic & E1000_MDIC_READY)
2866 break;
2867 }
2868 if (!(mdic & E1000_MDIC_READY)) {
2869 e_dbg("MDI Read did not complete\n");
2870 return -E1000_ERR_PHY;
2871 }
2872 if (mdic & E1000_MDIC_ERROR) {
2873 e_dbg("MDI Error\n");
2874 return -E1000_ERR_PHY;
2875 }
2876 *phy_data = (u16)mdic;
2877 }
2878 } else {
2879 /* We must first send a preamble through the MDIO pin to signal
2880 * the beginning of an MII instruction. This is done by sending
2881 * 32 consecutive "1" bits.
2882 */
2883 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2884
2885 /* Now combine the next few fields that are required for a read
2886 * operation. We use this method instead of calling the
2887 * e1000_shift_out_mdi_bits routine five different times. The
2888 * format of a MII read instruction consists of a shift out of
2889 * 14 bits and is defined as follows:
2890 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2891 * followed by a shift in of 18 bits. This first two bits
2892 * shifted in are TurnAround bits used to avoid contention on
2893 * the MDIO pin when a READ operation is performed. These two
2894 * bits are thrown away followed by a shift in of 16 bits which
2895 * contains the desired data.
2896 */
2897 mdic = ((reg_addr) | (phy_addr << 5) |
2898 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2899
2900 e1000_shift_out_mdi_bits(hw, mdic, 14);
2901
2902 /* Now that we've shifted out the read command to the MII, we
2903 * need to "shift in" the 16-bit value (18 total bits) of the
2904 * requested PHY register address.
2905 */
2906 *phy_data = e1000_shift_in_mdi_bits(hw);
2907 }
2908 return E1000_SUCCESS;
2909 }
2910
2911 /**
2912 * e1000_write_phy_reg - write a phy register
2913 *
2914 * @hw: Struct containing variables accessed by shared code
2915 * @reg_addr: address of the PHY register to write
2916 * @phy_data: data to write to the PHY
2917 *
2918 * Writes a value to a PHY register
2919 */
e1000_write_phy_reg(struct e1000_hw * hw,u32 reg_addr,u16 phy_data)2920 s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
2921 {
2922 u32 ret_val;
2923 unsigned long flags;
2924
2925 spin_lock_irqsave(&e1000_phy_lock, flags);
2926
2927 if ((hw->phy_type == e1000_phy_igp) &&
2928 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2929 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2930 (u16)reg_addr);
2931 if (ret_val) {
2932 spin_unlock_irqrestore(&e1000_phy_lock, flags);
2933 return ret_val;
2934 }
2935 }
2936
2937 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2938 phy_data);
2939 spin_unlock_irqrestore(&e1000_phy_lock, flags);
2940
2941 return ret_val;
2942 }
2943
e1000_write_phy_reg_ex(struct e1000_hw * hw,u32 reg_addr,u16 phy_data)2944 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2945 u16 phy_data)
2946 {
2947 u32 i;
2948 u32 mdic = 0;
2949 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2950
2951 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2952 e_dbg("PHY Address %d is out of range\n", reg_addr);
2953 return -E1000_ERR_PARAM;
2954 }
2955
2956 if (hw->mac_type > e1000_82543) {
2957 /* Set up Op-code, Phy Address, register address, and data
2958 * intended for the PHY register in the MDI Control register.
2959 * The MAC will take care of interfacing with the PHY to send
2960 * the desired data.
2961 */
2962 if (hw->mac_type == e1000_ce4100) {
2963 mdic = (((u32)phy_data) |
2964 (reg_addr << E1000_MDIC_REG_SHIFT) |
2965 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2966 (INTEL_CE_GBE_MDIC_OP_WRITE) |
2967 (INTEL_CE_GBE_MDIC_GO));
2968
2969 writel(mdic, E1000_MDIO_CMD);
2970
2971 /* Poll the ready bit to see if the MDI read
2972 * completed
2973 */
2974 for (i = 0; i < 640; i++) {
2975 udelay(5);
2976 mdic = readl(E1000_MDIO_CMD);
2977 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
2978 break;
2979 }
2980 if (mdic & INTEL_CE_GBE_MDIC_GO) {
2981 e_dbg("MDI Write did not complete\n");
2982 return -E1000_ERR_PHY;
2983 }
2984 } else {
2985 mdic = (((u32)phy_data) |
2986 (reg_addr << E1000_MDIC_REG_SHIFT) |
2987 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2988 (E1000_MDIC_OP_WRITE));
2989
2990 ew32(MDIC, mdic);
2991
2992 /* Poll the ready bit to see if the MDI read
2993 * completed
2994 */
2995 for (i = 0; i < 641; i++) {
2996 udelay(5);
2997 mdic = er32(MDIC);
2998 if (mdic & E1000_MDIC_READY)
2999 break;
3000 }
3001 if (!(mdic & E1000_MDIC_READY)) {
3002 e_dbg("MDI Write did not complete\n");
3003 return -E1000_ERR_PHY;
3004 }
3005 }
3006 } else {
3007 /* We'll need to use the SW defined pins to shift the write
3008 * command out to the PHY. We first send a preamble to the PHY
3009 * to signal the beginning of the MII instruction. This is done
3010 * by sending 32 consecutive "1" bits.
3011 */
3012 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3013
3014 /* Now combine the remaining required fields that will indicate
3015 * a write operation. We use this method instead of calling the
3016 * e1000_shift_out_mdi_bits routine for each field in the
3017 * command. The format of a MII write instruction is as follows:
3018 * <Preamble><SOF><OpCode><PhyAddr><RegAddr><Turnaround><Data>.
3019 */
3020 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3021 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3022 mdic <<= 16;
3023 mdic |= (u32)phy_data;
3024
3025 e1000_shift_out_mdi_bits(hw, mdic, 32);
3026 }
3027
3028 return E1000_SUCCESS;
3029 }
3030
3031 /**
3032 * e1000_phy_hw_reset - reset the phy, hardware style
3033 * @hw: Struct containing variables accessed by shared code
3034 *
3035 * Returns the PHY to the power-on reset state
3036 */
e1000_phy_hw_reset(struct e1000_hw * hw)3037 s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3038 {
3039 u32 ctrl, ctrl_ext;
3040 u32 led_ctrl;
3041
3042 e_dbg("Resetting Phy...\n");
3043
3044 if (hw->mac_type > e1000_82543) {
3045 /* Read the device control register and assert the
3046 * E1000_CTRL_PHY_RST bit. Then, take it out of reset.
3047 * For e1000 hardware, we delay for 10ms between the assert
3048 * and de-assert.
3049 */
3050 ctrl = er32(CTRL);
3051 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
3052 E1000_WRITE_FLUSH();
3053
3054 msleep(10);
3055
3056 ew32(CTRL, ctrl);
3057 E1000_WRITE_FLUSH();
3058
3059 } else {
3060 /* Read the Extended Device Control Register, assert the
3061 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it
3062 * out of reset.
3063 */
3064 ctrl_ext = er32(CTRL_EXT);
3065 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3066 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3067 ew32(CTRL_EXT, ctrl_ext);
3068 E1000_WRITE_FLUSH();
3069 msleep(10);
3070 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3071 ew32(CTRL_EXT, ctrl_ext);
3072 E1000_WRITE_FLUSH();
3073 }
3074 udelay(150);
3075
3076 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3077 /* Configure activity LED after PHY reset */
3078 led_ctrl = er32(LEDCTL);
3079 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3080 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3081 ew32(LEDCTL, led_ctrl);
3082 }
3083
3084 /* Wait for FW to finish PHY configuration. */
3085 return e1000_get_phy_cfg_done(hw);
3086 }
3087
3088 /**
3089 * e1000_phy_reset - reset the phy to commit settings
3090 * @hw: Struct containing variables accessed by shared code
3091 *
3092 * Resets the PHY
3093 * Sets bit 15 of the MII Control register
3094 */
e1000_phy_reset(struct e1000_hw * hw)3095 s32 e1000_phy_reset(struct e1000_hw *hw)
3096 {
3097 s32 ret_val;
3098 u16 phy_data;
3099
3100 switch (hw->phy_type) {
3101 case e1000_phy_igp:
3102 ret_val = e1000_phy_hw_reset(hw);
3103 if (ret_val)
3104 return ret_val;
3105 break;
3106 default:
3107 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3108 if (ret_val)
3109 return ret_val;
3110
3111 phy_data |= MII_CR_RESET;
3112 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3113 if (ret_val)
3114 return ret_val;
3115
3116 udelay(1);
3117 break;
3118 }
3119
3120 if (hw->phy_type == e1000_phy_igp)
3121 e1000_phy_init_script(hw);
3122
3123 return E1000_SUCCESS;
3124 }
3125
3126 /**
3127 * e1000_detect_gig_phy - check the phy type
3128 * @hw: Struct containing variables accessed by shared code
3129 *
3130 * Probes the expected PHY address for known PHY IDs
3131 */
e1000_detect_gig_phy(struct e1000_hw * hw)3132 static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
3133 {
3134 s32 phy_init_status, ret_val;
3135 u16 phy_id_high, phy_id_low;
3136 bool match = false;
3137
3138 if (hw->phy_id != 0)
3139 return E1000_SUCCESS;
3140
3141 /* Read the PHY ID Registers to identify which PHY is onboard. */
3142 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3143 if (ret_val)
3144 return ret_val;
3145
3146 hw->phy_id = (u32)(phy_id_high << 16);
3147 udelay(20);
3148 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3149 if (ret_val)
3150 return ret_val;
3151
3152 hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK);
3153 hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK;
3154
3155 switch (hw->mac_type) {
3156 case e1000_82543:
3157 if (hw->phy_id == M88E1000_E_PHY_ID)
3158 match = true;
3159 break;
3160 case e1000_82544:
3161 if (hw->phy_id == M88E1000_I_PHY_ID)
3162 match = true;
3163 break;
3164 case e1000_82540:
3165 case e1000_82545:
3166 case e1000_82545_rev_3:
3167 case e1000_82546:
3168 case e1000_82546_rev_3:
3169 if (hw->phy_id == M88E1011_I_PHY_ID)
3170 match = true;
3171 break;
3172 case e1000_ce4100:
3173 if ((hw->phy_id == RTL8211B_PHY_ID) ||
3174 (hw->phy_id == RTL8201N_PHY_ID) ||
3175 (hw->phy_id == M88E1118_E_PHY_ID))
3176 match = true;
3177 break;
3178 case e1000_82541:
3179 case e1000_82541_rev_2:
3180 case e1000_82547:
3181 case e1000_82547_rev_2:
3182 if (hw->phy_id == IGP01E1000_I_PHY_ID)
3183 match = true;
3184 break;
3185 default:
3186 e_dbg("Invalid MAC type %d\n", hw->mac_type);
3187 return -E1000_ERR_CONFIG;
3188 }
3189 phy_init_status = e1000_set_phy_type(hw);
3190
3191 if ((match) && (phy_init_status == E1000_SUCCESS)) {
3192 e_dbg("PHY ID 0x%X detected\n", hw->phy_id);
3193 return E1000_SUCCESS;
3194 }
3195 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id);
3196 return -E1000_ERR_PHY;
3197 }
3198
3199 /**
3200 * e1000_phy_reset_dsp - reset DSP
3201 * @hw: Struct containing variables accessed by shared code
3202 *
3203 * Resets the PHY's DSP
3204 */
e1000_phy_reset_dsp(struct e1000_hw * hw)3205 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
3206 {
3207 s32 ret_val;
3208
3209 do {
3210 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3211 if (ret_val)
3212 break;
3213 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
3214 if (ret_val)
3215 break;
3216 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
3217 if (ret_val)
3218 break;
3219 ret_val = E1000_SUCCESS;
3220 } while (0);
3221
3222 return ret_val;
3223 }
3224
3225 /**
3226 * e1000_phy_igp_get_info - get igp specific registers
3227 * @hw: Struct containing variables accessed by shared code
3228 * @phy_info: PHY information structure
3229 *
3230 * Get PHY information from various PHY registers for igp PHY only.
3231 */
e1000_phy_igp_get_info(struct e1000_hw * hw,struct e1000_phy_info * phy_info)3232 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
3233 struct e1000_phy_info *phy_info)
3234 {
3235 s32 ret_val;
3236 u16 phy_data, min_length, max_length, average;
3237 e1000_rev_polarity polarity;
3238
3239 /* The downshift status is checked only once, after link is established,
3240 * and it stored in the hw->speed_downgraded parameter.
3241 */
3242 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3243
3244 /* IGP01E1000 does not need to support it. */
3245 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3246
3247 /* IGP01E1000 always correct polarity reversal */
3248 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
3249
3250 /* Check polarity status */
3251 ret_val = e1000_check_polarity(hw, &polarity);
3252 if (ret_val)
3253 return ret_val;
3254
3255 phy_info->cable_polarity = polarity;
3256
3257 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3258 if (ret_val)
3259 return ret_val;
3260
3261 phy_info->mdix_mode =
3262 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >>
3263 IGP01E1000_PSSR_MDIX_SHIFT);
3264
3265 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3266 IGP01E1000_PSSR_SPEED_1000MBPS) {
3267 /* Local/Remote Receiver Information are only valid @ 1000
3268 * Mbps
3269 */
3270 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3271 if (ret_val)
3272 return ret_val;
3273
3274 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3275 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3276 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3277 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3278 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3279 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3280
3281 /* Get cable length */
3282 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
3283 if (ret_val)
3284 return ret_val;
3285
3286 /* Translate to old method */
3287 average = (max_length + min_length) / 2;
3288
3289 if (average <= e1000_igp_cable_length_50)
3290 phy_info->cable_length = e1000_cable_length_50;
3291 else if (average <= e1000_igp_cable_length_80)
3292 phy_info->cable_length = e1000_cable_length_50_80;
3293 else if (average <= e1000_igp_cable_length_110)
3294 phy_info->cable_length = e1000_cable_length_80_110;
3295 else if (average <= e1000_igp_cable_length_140)
3296 phy_info->cable_length = e1000_cable_length_110_140;
3297 else
3298 phy_info->cable_length = e1000_cable_length_140;
3299 }
3300
3301 return E1000_SUCCESS;
3302 }
3303
3304 /**
3305 * e1000_phy_m88_get_info - get m88 specific registers
3306 * @hw: Struct containing variables accessed by shared code
3307 * @phy_info: PHY information structure
3308 *
3309 * Get PHY information from various PHY registers for m88 PHY only.
3310 */
e1000_phy_m88_get_info(struct e1000_hw * hw,struct e1000_phy_info * phy_info)3311 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
3312 struct e1000_phy_info *phy_info)
3313 {
3314 s32 ret_val;
3315 u16 phy_data;
3316 e1000_rev_polarity polarity;
3317
3318 /* The downshift status is checked only once, after link is established,
3319 * and it stored in the hw->speed_downgraded parameter.
3320 */
3321 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3322
3323 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3324 if (ret_val)
3325 return ret_val;
3326
3327 phy_info->extended_10bt_distance =
3328 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3329 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
3330 e1000_10bt_ext_dist_enable_lower :
3331 e1000_10bt_ext_dist_enable_normal;
3332
3333 phy_info->polarity_correction =
3334 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3335 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
3336 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
3337
3338 /* Check polarity status */
3339 ret_val = e1000_check_polarity(hw, &polarity);
3340 if (ret_val)
3341 return ret_val;
3342 phy_info->cable_polarity = polarity;
3343
3344 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3345 if (ret_val)
3346 return ret_val;
3347
3348 phy_info->mdix_mode =
3349 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >>
3350 M88E1000_PSSR_MDIX_SHIFT);
3351
3352 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3353 /* Cable Length Estimation and Local/Remote Receiver Information
3354 * are only valid at 1000 Mbps.
3355 */
3356 phy_info->cable_length =
3357 (e1000_cable_length) ((phy_data &
3358 M88E1000_PSSR_CABLE_LENGTH) >>
3359 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3360
3361 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3362 if (ret_val)
3363 return ret_val;
3364
3365 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3366 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3367 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3368 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3369 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3370 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3371 }
3372
3373 return E1000_SUCCESS;
3374 }
3375
3376 /**
3377 * e1000_phy_get_info - request phy info
3378 * @hw: Struct containing variables accessed by shared code
3379 * @phy_info: PHY information structure
3380 *
3381 * Get PHY information from various PHY registers
3382 */
e1000_phy_get_info(struct e1000_hw * hw,struct e1000_phy_info * phy_info)3383 s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
3384 {
3385 s32 ret_val;
3386 u16 phy_data;
3387
3388 phy_info->cable_length = e1000_cable_length_undefined;
3389 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3390 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3391 phy_info->downshift = e1000_downshift_undefined;
3392 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3393 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3394 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3395 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3396
3397 if (hw->media_type != e1000_media_type_copper) {
3398 e_dbg("PHY info is only valid for copper media\n");
3399 return -E1000_ERR_CONFIG;
3400 }
3401
3402 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3403 if (ret_val)
3404 return ret_val;
3405
3406 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3407 if (ret_val)
3408 return ret_val;
3409
3410 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3411 e_dbg("PHY info is only valid if link is up\n");
3412 return -E1000_ERR_CONFIG;
3413 }
3414
3415 if (hw->phy_type == e1000_phy_igp)
3416 return e1000_phy_igp_get_info(hw, phy_info);
3417 else if ((hw->phy_type == e1000_phy_8211) ||
3418 (hw->phy_type == e1000_phy_8201))
3419 return E1000_SUCCESS;
3420 else
3421 return e1000_phy_m88_get_info(hw, phy_info);
3422 }
3423
e1000_validate_mdi_setting(struct e1000_hw * hw)3424 s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
3425 {
3426 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3427 e_dbg("Invalid MDI setting detected\n");
3428 hw->mdix = 1;
3429 return -E1000_ERR_CONFIG;
3430 }
3431 return E1000_SUCCESS;
3432 }
3433
3434 /**
3435 * e1000_init_eeprom_params - initialize sw eeprom vars
3436 * @hw: Struct containing variables accessed by shared code
3437 *
3438 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3439 * is configured.
3440 */
e1000_init_eeprom_params(struct e1000_hw * hw)3441 s32 e1000_init_eeprom_params(struct e1000_hw *hw)
3442 {
3443 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3444 u32 eecd = er32(EECD);
3445 s32 ret_val = E1000_SUCCESS;
3446 u16 eeprom_size;
3447
3448 switch (hw->mac_type) {
3449 case e1000_82542_rev2_0:
3450 case e1000_82542_rev2_1:
3451 case e1000_82543:
3452 case e1000_82544:
3453 eeprom->type = e1000_eeprom_microwire;
3454 eeprom->word_size = 64;
3455 eeprom->opcode_bits = 3;
3456 eeprom->address_bits = 6;
3457 eeprom->delay_usec = 50;
3458 break;
3459 case e1000_82540:
3460 case e1000_82545:
3461 case e1000_82545_rev_3:
3462 case e1000_82546:
3463 case e1000_82546_rev_3:
3464 eeprom->type = e1000_eeprom_microwire;
3465 eeprom->opcode_bits = 3;
3466 eeprom->delay_usec = 50;
3467 if (eecd & E1000_EECD_SIZE) {
3468 eeprom->word_size = 256;
3469 eeprom->address_bits = 8;
3470 } else {
3471 eeprom->word_size = 64;
3472 eeprom->address_bits = 6;
3473 }
3474 break;
3475 case e1000_82541:
3476 case e1000_82541_rev_2:
3477 case e1000_82547:
3478 case e1000_82547_rev_2:
3479 if (eecd & E1000_EECD_TYPE) {
3480 eeprom->type = e1000_eeprom_spi;
3481 eeprom->opcode_bits = 8;
3482 eeprom->delay_usec = 1;
3483 if (eecd & E1000_EECD_ADDR_BITS) {
3484 eeprom->page_size = 32;
3485 eeprom->address_bits = 16;
3486 } else {
3487 eeprom->page_size = 8;
3488 eeprom->address_bits = 8;
3489 }
3490 } else {
3491 eeprom->type = e1000_eeprom_microwire;
3492 eeprom->opcode_bits = 3;
3493 eeprom->delay_usec = 50;
3494 if (eecd & E1000_EECD_ADDR_BITS) {
3495 eeprom->word_size = 256;
3496 eeprom->address_bits = 8;
3497 } else {
3498 eeprom->word_size = 64;
3499 eeprom->address_bits = 6;
3500 }
3501 }
3502 break;
3503 default:
3504 break;
3505 }
3506
3507 if (eeprom->type == e1000_eeprom_spi) {
3508 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes
3509 * 128B to 32KB (incremented by powers of 2).
3510 */
3511 /* Set to default value for initial eeprom read. */
3512 eeprom->word_size = 64;
3513 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3514 if (ret_val)
3515 return ret_val;
3516 eeprom_size =
3517 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3518 /* 256B eeprom size was not supported in earlier hardware, so we
3519 * bump eeprom_size up one to ensure that "1" (which maps to
3520 * 256B) is never the result used in the shifting logic below.
3521 */
3522 if (eeprom_size)
3523 eeprom_size++;
3524
3525 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3526 }
3527 return ret_val;
3528 }
3529
3530 /**
3531 * e1000_raise_ee_clk - Raises the EEPROM's clock input.
3532 * @hw: Struct containing variables accessed by shared code
3533 * @eecd: EECD's current value
3534 */
e1000_raise_ee_clk(struct e1000_hw * hw,u32 * eecd)3535 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
3536 {
3537 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3538 * wait <delay> microseconds.
3539 */
3540 *eecd = *eecd | E1000_EECD_SK;
3541 ew32(EECD, *eecd);
3542 E1000_WRITE_FLUSH();
3543 udelay(hw->eeprom.delay_usec);
3544 }
3545
3546 /**
3547 * e1000_lower_ee_clk - Lowers the EEPROM's clock input.
3548 * @hw: Struct containing variables accessed by shared code
3549 * @eecd: EECD's current value
3550 */
e1000_lower_ee_clk(struct e1000_hw * hw,u32 * eecd)3551 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
3552 {
3553 /* Lower the clock input to the EEPROM (by clearing the SK bit), and
3554 * then wait 50 microseconds.
3555 */
3556 *eecd = *eecd & ~E1000_EECD_SK;
3557 ew32(EECD, *eecd);
3558 E1000_WRITE_FLUSH();
3559 udelay(hw->eeprom.delay_usec);
3560 }
3561
3562 /**
3563 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM.
3564 * @hw: Struct containing variables accessed by shared code
3565 * @data: data to send to the EEPROM
3566 * @count: number of bits to shift out
3567 */
e1000_shift_out_ee_bits(struct e1000_hw * hw,u16 data,u16 count)3568 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
3569 {
3570 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3571 u32 eecd;
3572 u32 mask;
3573
3574 /* We need to shift "count" bits out to the EEPROM. So, value in the
3575 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3576 * In order to do this, "data" must be broken down into bits.
3577 */
3578 mask = 0x01 << (count - 1);
3579 eecd = er32(EECD);
3580 if (eeprom->type == e1000_eeprom_microwire)
3581 eecd &= ~E1000_EECD_DO;
3582 else if (eeprom->type == e1000_eeprom_spi)
3583 eecd |= E1000_EECD_DO;
3584
3585 do {
3586 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a
3587 * "1", and then raising and then lowering the clock (the SK bit
3588 * controls the clock input to the EEPROM). A "0" is shifted
3589 * out to the EEPROM by setting "DI" to "0" and then raising and
3590 * then lowering the clock.
3591 */
3592 eecd &= ~E1000_EECD_DI;
3593
3594 if (data & mask)
3595 eecd |= E1000_EECD_DI;
3596
3597 ew32(EECD, eecd);
3598 E1000_WRITE_FLUSH();
3599
3600 udelay(eeprom->delay_usec);
3601
3602 e1000_raise_ee_clk(hw, &eecd);
3603 e1000_lower_ee_clk(hw, &eecd);
3604
3605 mask = mask >> 1;
3606
3607 } while (mask);
3608
3609 /* We leave the "DI" bit set to "0" when we leave this routine. */
3610 eecd &= ~E1000_EECD_DI;
3611 ew32(EECD, eecd);
3612 }
3613
3614 /**
3615 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM
3616 * @hw: Struct containing variables accessed by shared code
3617 * @count: number of bits to shift in
3618 */
e1000_shift_in_ee_bits(struct e1000_hw * hw,u16 count)3619 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
3620 {
3621 u32 eecd;
3622 u32 i;
3623 u16 data;
3624
3625 /* In order to read a register from the EEPROM, we need to shift 'count'
3626 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3627 * input to the EEPROM (setting the SK bit), and then reading the value
3628 * of the "DO" bit. During this "shifting in" process the "DI" bit
3629 * should always be clear.
3630 */
3631
3632 eecd = er32(EECD);
3633
3634 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3635 data = 0;
3636
3637 for (i = 0; i < count; i++) {
3638 data = data << 1;
3639 e1000_raise_ee_clk(hw, &eecd);
3640
3641 eecd = er32(EECD);
3642
3643 eecd &= ~(E1000_EECD_DI);
3644 if (eecd & E1000_EECD_DO)
3645 data |= 1;
3646
3647 e1000_lower_ee_clk(hw, &eecd);
3648 }
3649
3650 return data;
3651 }
3652
3653 /**
3654 * e1000_acquire_eeprom - Prepares EEPROM for access
3655 * @hw: Struct containing variables accessed by shared code
3656 *
3657 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3658 * function should be called before issuing a command to the EEPROM.
3659 */
e1000_acquire_eeprom(struct e1000_hw * hw)3660 static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
3661 {
3662 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3663 u32 eecd, i = 0;
3664
3665 eecd = er32(EECD);
3666
3667 /* Request EEPROM Access */
3668 if (hw->mac_type > e1000_82544) {
3669 eecd |= E1000_EECD_REQ;
3670 ew32(EECD, eecd);
3671 eecd = er32(EECD);
3672 while ((!(eecd & E1000_EECD_GNT)) &&
3673 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3674 i++;
3675 udelay(5);
3676 eecd = er32(EECD);
3677 }
3678 if (!(eecd & E1000_EECD_GNT)) {
3679 eecd &= ~E1000_EECD_REQ;
3680 ew32(EECD, eecd);
3681 e_dbg("Could not acquire EEPROM grant\n");
3682 return -E1000_ERR_EEPROM;
3683 }
3684 }
3685
3686 /* Setup EEPROM for Read/Write */
3687
3688 if (eeprom->type == e1000_eeprom_microwire) {
3689 /* Clear SK and DI */
3690 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3691 ew32(EECD, eecd);
3692
3693 /* Set CS */
3694 eecd |= E1000_EECD_CS;
3695 ew32(EECD, eecd);
3696 } else if (eeprom->type == e1000_eeprom_spi) {
3697 /* Clear SK and CS */
3698 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3699 ew32(EECD, eecd);
3700 E1000_WRITE_FLUSH();
3701 udelay(1);
3702 }
3703
3704 return E1000_SUCCESS;
3705 }
3706
3707 /**
3708 * e1000_standby_eeprom - Returns EEPROM to a "standby" state
3709 * @hw: Struct containing variables accessed by shared code
3710 */
e1000_standby_eeprom(struct e1000_hw * hw)3711 static void e1000_standby_eeprom(struct e1000_hw *hw)
3712 {
3713 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3714 u32 eecd;
3715
3716 eecd = er32(EECD);
3717
3718 if (eeprom->type == e1000_eeprom_microwire) {
3719 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3720 ew32(EECD, eecd);
3721 E1000_WRITE_FLUSH();
3722 udelay(eeprom->delay_usec);
3723
3724 /* Clock high */
3725 eecd |= E1000_EECD_SK;
3726 ew32(EECD, eecd);
3727 E1000_WRITE_FLUSH();
3728 udelay(eeprom->delay_usec);
3729
3730 /* Select EEPROM */
3731 eecd |= E1000_EECD_CS;
3732 ew32(EECD, eecd);
3733 E1000_WRITE_FLUSH();
3734 udelay(eeprom->delay_usec);
3735
3736 /* Clock low */
3737 eecd &= ~E1000_EECD_SK;
3738 ew32(EECD, eecd);
3739 E1000_WRITE_FLUSH();
3740 udelay(eeprom->delay_usec);
3741 } else if (eeprom->type == e1000_eeprom_spi) {
3742 /* Toggle CS to flush commands */
3743 eecd |= E1000_EECD_CS;
3744 ew32(EECD, eecd);
3745 E1000_WRITE_FLUSH();
3746 udelay(eeprom->delay_usec);
3747 eecd &= ~E1000_EECD_CS;
3748 ew32(EECD, eecd);
3749 E1000_WRITE_FLUSH();
3750 udelay(eeprom->delay_usec);
3751 }
3752 }
3753
3754 /**
3755 * e1000_release_eeprom - drop chip select
3756 * @hw: Struct containing variables accessed by shared code
3757 *
3758 * Terminates a command by inverting the EEPROM's chip select pin
3759 */
e1000_release_eeprom(struct e1000_hw * hw)3760 static void e1000_release_eeprom(struct e1000_hw *hw)
3761 {
3762 u32 eecd;
3763
3764 eecd = er32(EECD);
3765
3766 if (hw->eeprom.type == e1000_eeprom_spi) {
3767 eecd |= E1000_EECD_CS; /* Pull CS high */
3768 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3769
3770 ew32(EECD, eecd);
3771 E1000_WRITE_FLUSH();
3772
3773 udelay(hw->eeprom.delay_usec);
3774 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
3775 /* cleanup eeprom */
3776
3777 /* CS on Microwire is active-high */
3778 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3779
3780 ew32(EECD, eecd);
3781
3782 /* Rising edge of clock */
3783 eecd |= E1000_EECD_SK;
3784 ew32(EECD, eecd);
3785 E1000_WRITE_FLUSH();
3786 udelay(hw->eeprom.delay_usec);
3787
3788 /* Falling edge of clock */
3789 eecd &= ~E1000_EECD_SK;
3790 ew32(EECD, eecd);
3791 E1000_WRITE_FLUSH();
3792 udelay(hw->eeprom.delay_usec);
3793 }
3794
3795 /* Stop requesting EEPROM access */
3796 if (hw->mac_type > e1000_82544) {
3797 eecd &= ~E1000_EECD_REQ;
3798 ew32(EECD, eecd);
3799 }
3800 }
3801
3802 /**
3803 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM.
3804 * @hw: Struct containing variables accessed by shared code
3805 */
e1000_spi_eeprom_ready(struct e1000_hw * hw)3806 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3807 {
3808 u16 retry_count = 0;
3809 u8 spi_stat_reg;
3810
3811 /* Read "Status Register" repeatedly until the LSB is cleared. The
3812 * EEPROM will signal that the command has been completed by clearing
3813 * bit 0 of the internal status register. If it's not cleared within
3814 * 5 milliseconds, then error out.
3815 */
3816 retry_count = 0;
3817 do {
3818 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3819 hw->eeprom.opcode_bits);
3820 spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);
3821 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3822 break;
3823
3824 udelay(5);
3825 retry_count += 5;
3826
3827 e1000_standby_eeprom(hw);
3828 } while (retry_count < EEPROM_MAX_RETRY_SPI);
3829
3830 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3831 * only 0-5mSec on 5V devices)
3832 */
3833 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
3834 e_dbg("SPI EEPROM Status error\n");
3835 return -E1000_ERR_EEPROM;
3836 }
3837
3838 return E1000_SUCCESS;
3839 }
3840
3841 /**
3842 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM.
3843 * @hw: Struct containing variables accessed by shared code
3844 * @offset: offset of word in the EEPROM to read
3845 * @data: word read from the EEPROM
3846 * @words: number of words to read
3847 */
e1000_read_eeprom(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)3848 s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
3849 {
3850 s32 ret;
3851
3852 mutex_lock(&e1000_eeprom_lock);
3853 ret = e1000_do_read_eeprom(hw, offset, words, data);
3854 mutex_unlock(&e1000_eeprom_lock);
3855 return ret;
3856 }
3857
e1000_do_read_eeprom(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)3858 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3859 u16 *data)
3860 {
3861 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3862 u32 i = 0;
3863
3864 if (hw->mac_type == e1000_ce4100) {
3865 GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words,
3866 data);
3867 return E1000_SUCCESS;
3868 }
3869
3870 /* A check for invalid values: offset too large, too many words, and
3871 * not enough words.
3872 */
3873 if ((offset >= eeprom->word_size) ||
3874 (words > eeprom->word_size - offset) ||
3875 (words == 0)) {
3876 e_dbg("\"words\" parameter out of bounds. Words = %d,"
3877 "size = %d\n", offset, eeprom->word_size);
3878 return -E1000_ERR_EEPROM;
3879 }
3880
3881 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
3882 * directly. In this case, we need to acquire the EEPROM so that
3883 * FW or other port software does not interrupt.
3884 */
3885 /* Prepare the EEPROM for bit-bang reading */
3886 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3887 return -E1000_ERR_EEPROM;
3888
3889 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
3890 * acquired the EEPROM at this point, so any returns should release it
3891 */
3892 if (eeprom->type == e1000_eeprom_spi) {
3893 u16 word_in;
3894 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
3895
3896 if (e1000_spi_eeprom_ready(hw)) {
3897 e1000_release_eeprom(hw);
3898 return -E1000_ERR_EEPROM;
3899 }
3900
3901 e1000_standby_eeprom(hw);
3902
3903 /* Some SPI eeproms use the 8th address bit embedded in the
3904 * opcode
3905 */
3906 if ((eeprom->address_bits == 8) && (offset >= 128))
3907 read_opcode |= EEPROM_A8_OPCODE_SPI;
3908
3909 /* Send the READ command (opcode + addr) */
3910 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3911 e1000_shift_out_ee_bits(hw, (u16)(offset * 2),
3912 eeprom->address_bits);
3913
3914 /* Read the data. The address of the eeprom internally
3915 * increments with each byte (spi) being read, saving on the
3916 * overhead of eeprom setup and tear-down. The address counter
3917 * will roll over if reading beyond the size of the eeprom, thus
3918 * allowing the entire memory to be read starting from any
3919 * offset.
3920 */
3921 for (i = 0; i < words; i++) {
3922 word_in = e1000_shift_in_ee_bits(hw, 16);
3923 data[i] = (word_in >> 8) | (word_in << 8);
3924 }
3925 } else if (eeprom->type == e1000_eeprom_microwire) {
3926 for (i = 0; i < words; i++) {
3927 /* Send the READ command (opcode + addr) */
3928 e1000_shift_out_ee_bits(hw,
3929 EEPROM_READ_OPCODE_MICROWIRE,
3930 eeprom->opcode_bits);
3931 e1000_shift_out_ee_bits(hw, (u16)(offset + i),
3932 eeprom->address_bits);
3933
3934 /* Read the data. For microwire, each word requires the
3935 * overhead of eeprom setup and tear-down.
3936 */
3937 data[i] = e1000_shift_in_ee_bits(hw, 16);
3938 e1000_standby_eeprom(hw);
3939 cond_resched();
3940 }
3941 }
3942
3943 /* End this read operation */
3944 e1000_release_eeprom(hw);
3945
3946 return E1000_SUCCESS;
3947 }
3948
3949 /**
3950 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum
3951 * @hw: Struct containing variables accessed by shared code
3952 *
3953 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3954 * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3955 * valid.
3956 */
e1000_validate_eeprom_checksum(struct e1000_hw * hw)3957 s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3958 {
3959 u16 checksum = 0;
3960 u16 i, eeprom_data;
3961
3962 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3963 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3964 e_dbg("EEPROM Read Error\n");
3965 return -E1000_ERR_EEPROM;
3966 }
3967 checksum += eeprom_data;
3968 }
3969
3970 #ifdef CONFIG_PARISC
3971 /* This is a signature and not a checksum on HP c8000 */
3972 if ((hw->subsystem_vendor_id == 0x103C) && (eeprom_data == 0x16d6))
3973 return E1000_SUCCESS;
3974
3975 #endif
3976 if (checksum == (u16)EEPROM_SUM)
3977 return E1000_SUCCESS;
3978 else {
3979 e_dbg("EEPROM Checksum Invalid\n");
3980 return -E1000_ERR_EEPROM;
3981 }
3982 }
3983
3984 /**
3985 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum
3986 * @hw: Struct containing variables accessed by shared code
3987 *
3988 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
3989 * Writes the difference to word offset 63 of the EEPROM.
3990 */
e1000_update_eeprom_checksum(struct e1000_hw * hw)3991 s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
3992 {
3993 u16 checksum = 0;
3994 u16 i, eeprom_data;
3995
3996 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3997 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3998 e_dbg("EEPROM Read Error\n");
3999 return -E1000_ERR_EEPROM;
4000 }
4001 checksum += eeprom_data;
4002 }
4003 checksum = (u16)EEPROM_SUM - checksum;
4004 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
4005 e_dbg("EEPROM Write Error\n");
4006 return -E1000_ERR_EEPROM;
4007 }
4008 return E1000_SUCCESS;
4009 }
4010
4011 /**
4012 * e1000_write_eeprom - write words to the different EEPROM types.
4013 * @hw: Struct containing variables accessed by shared code
4014 * @offset: offset within the EEPROM to be written to
4015 * @words: number of words to write
4016 * @data: 16 bit word to be written to the EEPROM
4017 *
4018 * If e1000_update_eeprom_checksum is not called after this function, the
4019 * EEPROM will most likely contain an invalid checksum.
4020 */
e1000_write_eeprom(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)4021 s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
4022 {
4023 s32 ret;
4024
4025 mutex_lock(&e1000_eeprom_lock);
4026 ret = e1000_do_write_eeprom(hw, offset, words, data);
4027 mutex_unlock(&e1000_eeprom_lock);
4028 return ret;
4029 }
4030
e1000_do_write_eeprom(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)4031 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
4032 u16 *data)
4033 {
4034 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4035 s32 status = 0;
4036
4037 if (hw->mac_type == e1000_ce4100) {
4038 GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words,
4039 data);
4040 return E1000_SUCCESS;
4041 }
4042
4043 /* A check for invalid values: offset too large, too many words, and
4044 * not enough words.
4045 */
4046 if ((offset >= eeprom->word_size) ||
4047 (words > eeprom->word_size - offset) ||
4048 (words == 0)) {
4049 e_dbg("\"words\" parameter out of bounds\n");
4050 return -E1000_ERR_EEPROM;
4051 }
4052
4053 /* Prepare the EEPROM for writing */
4054 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4055 return -E1000_ERR_EEPROM;
4056
4057 if (eeprom->type == e1000_eeprom_microwire) {
4058 status = e1000_write_eeprom_microwire(hw, offset, words, data);
4059 } else {
4060 status = e1000_write_eeprom_spi(hw, offset, words, data);
4061 msleep(10);
4062 }
4063
4064 /* Done with writing */
4065 e1000_release_eeprom(hw);
4066
4067 return status;
4068 }
4069
4070 /**
4071 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM.
4072 * @hw: Struct containing variables accessed by shared code
4073 * @offset: offset within the EEPROM to be written to
4074 * @words: number of words to write
4075 * @data: pointer to array of 8 bit words to be written to the EEPROM
4076 */
e1000_write_eeprom_spi(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)4077 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
4078 u16 *data)
4079 {
4080 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4081 u16 widx = 0;
4082
4083 while (widx < words) {
4084 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
4085
4086 if (e1000_spi_eeprom_ready(hw))
4087 return -E1000_ERR_EEPROM;
4088
4089 e1000_standby_eeprom(hw);
4090 cond_resched();
4091
4092 /* Send the WRITE ENABLE command (8 bit opcode ) */
4093 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
4094 eeprom->opcode_bits);
4095
4096 e1000_standby_eeprom(hw);
4097
4098 /* Some SPI eeproms use the 8th address bit embedded in the
4099 * opcode
4100 */
4101 if ((eeprom->address_bits == 8) && (offset >= 128))
4102 write_opcode |= EEPROM_A8_OPCODE_SPI;
4103
4104 /* Send the Write command (8-bit opcode + addr) */
4105 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
4106
4107 e1000_shift_out_ee_bits(hw, (u16)((offset + widx) * 2),
4108 eeprom->address_bits);
4109
4110 /* Send the data */
4111
4112 /* Loop to allow for up to whole page write (32 bytes) of
4113 * eeprom
4114 */
4115 while (widx < words) {
4116 u16 word_out = data[widx];
4117
4118 word_out = (word_out >> 8) | (word_out << 8);
4119 e1000_shift_out_ee_bits(hw, word_out, 16);
4120 widx++;
4121
4122 /* Some larger eeprom sizes are capable of a 32-byte
4123 * PAGE WRITE operation, while the smaller eeproms are
4124 * capable of an 8-byte PAGE WRITE operation. Break the
4125 * inner loop to pass new address
4126 */
4127 if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
4128 e1000_standby_eeprom(hw);
4129 break;
4130 }
4131 }
4132 }
4133
4134 return E1000_SUCCESS;
4135 }
4136
4137 /**
4138 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM.
4139 * @hw: Struct containing variables accessed by shared code
4140 * @offset: offset within the EEPROM to be written to
4141 * @words: number of words to write
4142 * @data: pointer to array of 8 bit words to be written to the EEPROM
4143 */
e1000_write_eeprom_microwire(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)4144 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
4145 u16 words, u16 *data)
4146 {
4147 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4148 u32 eecd;
4149 u16 words_written = 0;
4150 u16 i = 0;
4151
4152 /* Send the write enable command to the EEPROM (3-bit opcode plus
4153 * 6/8-bit dummy address beginning with 11). It's less work to include
4154 * the 11 of the dummy address as part of the opcode than it is to shift
4155 * it over the correct number of bits for the address. This puts the
4156 * EEPROM into write/erase mode.
4157 */
4158 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4159 (u16)(eeprom->opcode_bits + 2));
4160
4161 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
4162
4163 /* Prepare the EEPROM */
4164 e1000_standby_eeprom(hw);
4165
4166 while (words_written < words) {
4167 /* Send the Write command (3-bit opcode + addr) */
4168 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4169 eeprom->opcode_bits);
4170
4171 e1000_shift_out_ee_bits(hw, (u16)(offset + words_written),
4172 eeprom->address_bits);
4173
4174 /* Send the data */
4175 e1000_shift_out_ee_bits(hw, data[words_written], 16);
4176
4177 /* Toggle the CS line. This in effect tells the EEPROM to
4178 * execute the previous command.
4179 */
4180 e1000_standby_eeprom(hw);
4181
4182 /* Read DO repeatedly until it is high (equal to '1'). The
4183 * EEPROM will signal that the command has been completed by
4184 * raising the DO signal. If DO does not go high in 10
4185 * milliseconds, then error out.
4186 */
4187 for (i = 0; i < 200; i++) {
4188 eecd = er32(EECD);
4189 if (eecd & E1000_EECD_DO)
4190 break;
4191 udelay(50);
4192 }
4193 if (i == 200) {
4194 e_dbg("EEPROM Write did not complete\n");
4195 return -E1000_ERR_EEPROM;
4196 }
4197
4198 /* Recover from write */
4199 e1000_standby_eeprom(hw);
4200 cond_resched();
4201
4202 words_written++;
4203 }
4204
4205 /* Send the write disable command to the EEPROM (3-bit opcode plus
4206 * 6/8-bit dummy address beginning with 10). It's less work to include
4207 * the 10 of the dummy address as part of the opcode than it is to shift
4208 * it over the correct number of bits for the address. This takes the
4209 * EEPROM out of write/erase mode.
4210 */
4211 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4212 (u16)(eeprom->opcode_bits + 2));
4213
4214 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
4215
4216 return E1000_SUCCESS;
4217 }
4218
4219 /**
4220 * e1000_read_mac_addr - read the adapters MAC from eeprom
4221 * @hw: Struct containing variables accessed by shared code
4222 *
4223 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
4224 * second function of dual function devices
4225 */
e1000_read_mac_addr(struct e1000_hw * hw)4226 s32 e1000_read_mac_addr(struct e1000_hw *hw)
4227 {
4228 u16 offset;
4229 u16 eeprom_data, i;
4230
4231 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
4232 offset = i >> 1;
4233 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4234 e_dbg("EEPROM Read Error\n");
4235 return -E1000_ERR_EEPROM;
4236 }
4237 hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF);
4238 hw->perm_mac_addr[i + 1] = (u8)(eeprom_data >> 8);
4239 }
4240
4241 switch (hw->mac_type) {
4242 default:
4243 break;
4244 case e1000_82546:
4245 case e1000_82546_rev_3:
4246 if (er32(STATUS) & E1000_STATUS_FUNC_1)
4247 hw->perm_mac_addr[5] ^= 0x01;
4248 break;
4249 }
4250
4251 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
4252 hw->mac_addr[i] = hw->perm_mac_addr[i];
4253 return E1000_SUCCESS;
4254 }
4255
4256 /**
4257 * e1000_init_rx_addrs - Initializes receive address filters.
4258 * @hw: Struct containing variables accessed by shared code
4259 *
4260 * Places the MAC address in receive address register 0 and clears the rest
4261 * of the receive address registers. Clears the multicast table. Assumes
4262 * the receiver is in reset when the routine is called.
4263 */
e1000_init_rx_addrs(struct e1000_hw * hw)4264 static void e1000_init_rx_addrs(struct e1000_hw *hw)
4265 {
4266 u32 i;
4267 u32 rar_num;
4268
4269 /* Setup the receive address. */
4270 e_dbg("Programming MAC Address into RAR[0]\n");
4271
4272 e1000_rar_set(hw, hw->mac_addr, 0);
4273
4274 rar_num = E1000_RAR_ENTRIES;
4275
4276 /* Zero out the following 14 receive addresses. RAR[15] is for
4277 * manageability
4278 */
4279 e_dbg("Clearing RAR[1-14]\n");
4280 for (i = 1; i < rar_num; i++) {
4281 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4282 E1000_WRITE_FLUSH();
4283 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4284 E1000_WRITE_FLUSH();
4285 }
4286 }
4287
4288 /**
4289 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table
4290 * @hw: Struct containing variables accessed by shared code
4291 * @mc_addr: the multicast address to hash
4292 */
e1000_hash_mc_addr(struct e1000_hw * hw,u8 * mc_addr)4293 u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
4294 {
4295 u32 hash_value = 0;
4296
4297 /* The portion of the address that is used for the hash table is
4298 * determined by the mc_filter_type setting.
4299 */
4300 switch (hw->mc_filter_type) {
4301 /* [0] [1] [2] [3] [4] [5]
4302 * 01 AA 00 12 34 56
4303 * LSB MSB
4304 */
4305 case 0:
4306 /* [47:36] i.e. 0x563 for above example address */
4307 hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
4308 break;
4309 case 1:
4310 /* [46:35] i.e. 0xAC6 for above example address */
4311 hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
4312 break;
4313 case 2:
4314 /* [45:34] i.e. 0x5D8 for above example address */
4315 hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
4316 break;
4317 case 3:
4318 /* [43:32] i.e. 0x634 for above example address */
4319 hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
4320 break;
4321 }
4322
4323 hash_value &= 0xFFF;
4324 return hash_value;
4325 }
4326
4327 /**
4328 * e1000_rar_set - Puts an ethernet address into a receive address register.
4329 * @hw: Struct containing variables accessed by shared code
4330 * @addr: Address to put into receive address register
4331 * @index: Receive address register to write
4332 */
e1000_rar_set(struct e1000_hw * hw,u8 * addr,u32 index)4333 void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
4334 {
4335 u32 rar_low, rar_high;
4336
4337 /* HW expects these in little endian so we reverse the byte order
4338 * from network order (big endian) to little endian
4339 */
4340 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
4341 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
4342 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
4343
4344 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
4345 * unit hang.
4346 *
4347 * Description:
4348 * If there are any Rx frames queued up or otherwise present in the HW
4349 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
4350 * hang. To work around this issue, we have to disable receives and
4351 * flush out all Rx frames before we enable RSS. To do so, we modify we
4352 * redirect all Rx traffic to manageability and then reset the HW.
4353 * This flushes away Rx frames, and (since the redirections to
4354 * manageability persists across resets) keeps new ones from coming in
4355 * while we work. Then, we clear the Address Valid AV bit for all MAC
4356 * addresses and undo the re-direction to manageability.
4357 * Now, frames are coming in again, but the MAC won't accept them, so
4358 * far so good. We now proceed to initialize RSS (if necessary) and
4359 * configure the Rx unit. Last, we re-enable the AV bits and continue
4360 * on our merry way.
4361 */
4362 switch (hw->mac_type) {
4363 default:
4364 /* Indicate to hardware the Address is Valid. */
4365 rar_high |= E1000_RAH_AV;
4366 break;
4367 }
4368
4369 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4370 E1000_WRITE_FLUSH();
4371 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4372 E1000_WRITE_FLUSH();
4373 }
4374
4375 /**
4376 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table.
4377 * @hw: Struct containing variables accessed by shared code
4378 * @offset: Offset in VLAN filer table to write
4379 * @value: Value to write into VLAN filter table
4380 */
e1000_write_vfta(struct e1000_hw * hw,u32 offset,u32 value)4381 void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
4382 {
4383 u32 temp;
4384
4385 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4386 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4387 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4388 E1000_WRITE_FLUSH();
4389 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4390 E1000_WRITE_FLUSH();
4391 } else {
4392 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4393 E1000_WRITE_FLUSH();
4394 }
4395 }
4396
4397 /**
4398 * e1000_clear_vfta - Clears the VLAN filer table
4399 * @hw: Struct containing variables accessed by shared code
4400 */
e1000_clear_vfta(struct e1000_hw * hw)4401 static void e1000_clear_vfta(struct e1000_hw *hw)
4402 {
4403 u32 offset;
4404
4405 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4406 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
4407 E1000_WRITE_FLUSH();
4408 }
4409 }
4410
e1000_id_led_init(struct e1000_hw * hw)4411 static s32 e1000_id_led_init(struct e1000_hw *hw)
4412 {
4413 u32 ledctl;
4414 const u32 ledctl_mask = 0x000000FF;
4415 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4416 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4417 u16 eeprom_data, i, temp;
4418 const u16 led_mask = 0x0F;
4419
4420 if (hw->mac_type < e1000_82540) {
4421 /* Nothing to do */
4422 return E1000_SUCCESS;
4423 }
4424
4425 ledctl = er32(LEDCTL);
4426 hw->ledctl_default = ledctl;
4427 hw->ledctl_mode1 = hw->ledctl_default;
4428 hw->ledctl_mode2 = hw->ledctl_default;
4429
4430 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4431 e_dbg("EEPROM Read Error\n");
4432 return -E1000_ERR_EEPROM;
4433 }
4434
4435 if ((eeprom_data == ID_LED_RESERVED_0000) ||
4436 (eeprom_data == ID_LED_RESERVED_FFFF)) {
4437 eeprom_data = ID_LED_DEFAULT;
4438 }
4439
4440 for (i = 0; i < 4; i++) {
4441 temp = (eeprom_data >> (i << 2)) & led_mask;
4442 switch (temp) {
4443 case ID_LED_ON1_DEF2:
4444 case ID_LED_ON1_ON2:
4445 case ID_LED_ON1_OFF2:
4446 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4447 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4448 break;
4449 case ID_LED_OFF1_DEF2:
4450 case ID_LED_OFF1_ON2:
4451 case ID_LED_OFF1_OFF2:
4452 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4453 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4454 break;
4455 default:
4456 /* Do nothing */
4457 break;
4458 }
4459 switch (temp) {
4460 case ID_LED_DEF1_ON2:
4461 case ID_LED_ON1_ON2:
4462 case ID_LED_OFF1_ON2:
4463 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4464 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4465 break;
4466 case ID_LED_DEF1_OFF2:
4467 case ID_LED_ON1_OFF2:
4468 case ID_LED_OFF1_OFF2:
4469 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4470 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4471 break;
4472 default:
4473 /* Do nothing */
4474 break;
4475 }
4476 }
4477 return E1000_SUCCESS;
4478 }
4479
4480 /**
4481 * e1000_setup_led
4482 * @hw: Struct containing variables accessed by shared code
4483 *
4484 * Prepares SW controlable LED for use and saves the current state of the LED.
4485 */
e1000_setup_led(struct e1000_hw * hw)4486 s32 e1000_setup_led(struct e1000_hw *hw)
4487 {
4488 u32 ledctl;
4489 s32 ret_val = E1000_SUCCESS;
4490
4491 switch (hw->mac_type) {
4492 case e1000_82542_rev2_0:
4493 case e1000_82542_rev2_1:
4494 case e1000_82543:
4495 case e1000_82544:
4496 /* No setup necessary */
4497 break;
4498 case e1000_82541:
4499 case e1000_82547:
4500 case e1000_82541_rev_2:
4501 case e1000_82547_rev_2:
4502 /* Turn off PHY Smart Power Down (if enabled) */
4503 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4504 &hw->phy_spd_default);
4505 if (ret_val)
4506 return ret_val;
4507 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4508 (u16)(hw->phy_spd_default &
4509 ~IGP01E1000_GMII_SPD));
4510 if (ret_val)
4511 return ret_val;
4512 fallthrough;
4513 default:
4514 if (hw->media_type == e1000_media_type_fiber) {
4515 ledctl = er32(LEDCTL);
4516 /* Save current LEDCTL settings */
4517 hw->ledctl_default = ledctl;
4518 /* Turn off LED0 */
4519 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4520 E1000_LEDCTL_LED0_BLINK |
4521 E1000_LEDCTL_LED0_MODE_MASK);
4522 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4523 E1000_LEDCTL_LED0_MODE_SHIFT);
4524 ew32(LEDCTL, ledctl);
4525 } else if (hw->media_type == e1000_media_type_copper)
4526 ew32(LEDCTL, hw->ledctl_mode1);
4527 break;
4528 }
4529
4530 return E1000_SUCCESS;
4531 }
4532
4533 /**
4534 * e1000_cleanup_led - Restores the saved state of the SW controlable LED.
4535 * @hw: Struct containing variables accessed by shared code
4536 */
e1000_cleanup_led(struct e1000_hw * hw)4537 s32 e1000_cleanup_led(struct e1000_hw *hw)
4538 {
4539 s32 ret_val = E1000_SUCCESS;
4540
4541 switch (hw->mac_type) {
4542 case e1000_82542_rev2_0:
4543 case e1000_82542_rev2_1:
4544 case e1000_82543:
4545 case e1000_82544:
4546 /* No cleanup necessary */
4547 break;
4548 case e1000_82541:
4549 case e1000_82547:
4550 case e1000_82541_rev_2:
4551 case e1000_82547_rev_2:
4552 /* Turn on PHY Smart Power Down (if previously enabled) */
4553 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4554 hw->phy_spd_default);
4555 if (ret_val)
4556 return ret_val;
4557 fallthrough;
4558 default:
4559 /* Restore LEDCTL settings */
4560 ew32(LEDCTL, hw->ledctl_default);
4561 break;
4562 }
4563
4564 return E1000_SUCCESS;
4565 }
4566
4567 /**
4568 * e1000_led_on - Turns on the software controllable LED
4569 * @hw: Struct containing variables accessed by shared code
4570 */
e1000_led_on(struct e1000_hw * hw)4571 s32 e1000_led_on(struct e1000_hw *hw)
4572 {
4573 u32 ctrl = er32(CTRL);
4574
4575 switch (hw->mac_type) {
4576 case e1000_82542_rev2_0:
4577 case e1000_82542_rev2_1:
4578 case e1000_82543:
4579 /* Set SW Defineable Pin 0 to turn on the LED */
4580 ctrl |= E1000_CTRL_SWDPIN0;
4581 ctrl |= E1000_CTRL_SWDPIO0;
4582 break;
4583 case e1000_82544:
4584 if (hw->media_type == e1000_media_type_fiber) {
4585 /* Set SW Defineable Pin 0 to turn on the LED */
4586 ctrl |= E1000_CTRL_SWDPIN0;
4587 ctrl |= E1000_CTRL_SWDPIO0;
4588 } else {
4589 /* Clear SW Defineable Pin 0 to turn on the LED */
4590 ctrl &= ~E1000_CTRL_SWDPIN0;
4591 ctrl |= E1000_CTRL_SWDPIO0;
4592 }
4593 break;
4594 default:
4595 if (hw->media_type == e1000_media_type_fiber) {
4596 /* Clear SW Defineable Pin 0 to turn on the LED */
4597 ctrl &= ~E1000_CTRL_SWDPIN0;
4598 ctrl |= E1000_CTRL_SWDPIO0;
4599 } else if (hw->media_type == e1000_media_type_copper) {
4600 ew32(LEDCTL, hw->ledctl_mode2);
4601 return E1000_SUCCESS;
4602 }
4603 break;
4604 }
4605
4606 ew32(CTRL, ctrl);
4607
4608 return E1000_SUCCESS;
4609 }
4610
4611 /**
4612 * e1000_led_off - Turns off the software controllable LED
4613 * @hw: Struct containing variables accessed by shared code
4614 */
e1000_led_off(struct e1000_hw * hw)4615 s32 e1000_led_off(struct e1000_hw *hw)
4616 {
4617 u32 ctrl = er32(CTRL);
4618
4619 switch (hw->mac_type) {
4620 case e1000_82542_rev2_0:
4621 case e1000_82542_rev2_1:
4622 case e1000_82543:
4623 /* Clear SW Defineable Pin 0 to turn off the LED */
4624 ctrl &= ~E1000_CTRL_SWDPIN0;
4625 ctrl |= E1000_CTRL_SWDPIO0;
4626 break;
4627 case e1000_82544:
4628 if (hw->media_type == e1000_media_type_fiber) {
4629 /* Clear SW Defineable Pin 0 to turn off the LED */
4630 ctrl &= ~E1000_CTRL_SWDPIN0;
4631 ctrl |= E1000_CTRL_SWDPIO0;
4632 } else {
4633 /* Set SW Defineable Pin 0 to turn off the LED */
4634 ctrl |= E1000_CTRL_SWDPIN0;
4635 ctrl |= E1000_CTRL_SWDPIO0;
4636 }
4637 break;
4638 default:
4639 if (hw->media_type == e1000_media_type_fiber) {
4640 /* Set SW Defineable Pin 0 to turn off the LED */
4641 ctrl |= E1000_CTRL_SWDPIN0;
4642 ctrl |= E1000_CTRL_SWDPIO0;
4643 } else if (hw->media_type == e1000_media_type_copper) {
4644 ew32(LEDCTL, hw->ledctl_mode1);
4645 return E1000_SUCCESS;
4646 }
4647 break;
4648 }
4649
4650 ew32(CTRL, ctrl);
4651
4652 return E1000_SUCCESS;
4653 }
4654
4655 /**
4656 * e1000_clear_hw_cntrs - Clears all hardware statistics counters.
4657 * @hw: Struct containing variables accessed by shared code
4658 */
e1000_clear_hw_cntrs(struct e1000_hw * hw)4659 static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
4660 {
4661 er32(CRCERRS);
4662 er32(SYMERRS);
4663 er32(MPC);
4664 er32(SCC);
4665 er32(ECOL);
4666 er32(MCC);
4667 er32(LATECOL);
4668 er32(COLC);
4669 er32(DC);
4670 er32(SEC);
4671 er32(RLEC);
4672 er32(XONRXC);
4673 er32(XONTXC);
4674 er32(XOFFRXC);
4675 er32(XOFFTXC);
4676 er32(FCRUC);
4677
4678 er32(PRC64);
4679 er32(PRC127);
4680 er32(PRC255);
4681 er32(PRC511);
4682 er32(PRC1023);
4683 er32(PRC1522);
4684
4685 er32(GPRC);
4686 er32(BPRC);
4687 er32(MPRC);
4688 er32(GPTC);
4689 er32(GORCL);
4690 er32(GORCH);
4691 er32(GOTCL);
4692 er32(GOTCH);
4693 er32(RNBC);
4694 er32(RUC);
4695 er32(RFC);
4696 er32(ROC);
4697 er32(RJC);
4698 er32(TORL);
4699 er32(TORH);
4700 er32(TOTL);
4701 er32(TOTH);
4702 er32(TPR);
4703 er32(TPT);
4704
4705 er32(PTC64);
4706 er32(PTC127);
4707 er32(PTC255);
4708 er32(PTC511);
4709 er32(PTC1023);
4710 er32(PTC1522);
4711
4712 er32(MPTC);
4713 er32(BPTC);
4714
4715 if (hw->mac_type < e1000_82543)
4716 return;
4717
4718 er32(ALGNERRC);
4719 er32(RXERRC);
4720 er32(TNCRS);
4721 er32(CEXTERR);
4722 er32(TSCTC);
4723 er32(TSCTFC);
4724
4725 if (hw->mac_type <= e1000_82544)
4726 return;
4727
4728 er32(MGTPRC);
4729 er32(MGTPDC);
4730 er32(MGTPTC);
4731 }
4732
4733 /**
4734 * e1000_reset_adaptive - Resets Adaptive IFS to its default state.
4735 * @hw: Struct containing variables accessed by shared code
4736 *
4737 * Call this after e1000_init_hw. You may override the IFS defaults by setting
4738 * hw->ifs_params_forced to true. However, you must initialize hw->
4739 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4740 * before calling this function.
4741 */
e1000_reset_adaptive(struct e1000_hw * hw)4742 void e1000_reset_adaptive(struct e1000_hw *hw)
4743 {
4744 if (hw->adaptive_ifs) {
4745 if (!hw->ifs_params_forced) {
4746 hw->current_ifs_val = 0;
4747 hw->ifs_min_val = IFS_MIN;
4748 hw->ifs_max_val = IFS_MAX;
4749 hw->ifs_step_size = IFS_STEP;
4750 hw->ifs_ratio = IFS_RATIO;
4751 }
4752 hw->in_ifs_mode = false;
4753 ew32(AIT, 0);
4754 } else {
4755 e_dbg("Not in Adaptive IFS mode!\n");
4756 }
4757 }
4758
4759 /**
4760 * e1000_update_adaptive - update adaptive IFS
4761 * @hw: Struct containing variables accessed by shared code
4762 *
4763 * Called during the callback/watchdog routine to update IFS value based on
4764 * the ratio of transmits to collisions.
4765 */
e1000_update_adaptive(struct e1000_hw * hw)4766 void e1000_update_adaptive(struct e1000_hw *hw)
4767 {
4768 if (hw->adaptive_ifs) {
4769 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
4770 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
4771 hw->in_ifs_mode = true;
4772 if (hw->current_ifs_val < hw->ifs_max_val) {
4773 if (hw->current_ifs_val == 0)
4774 hw->current_ifs_val =
4775 hw->ifs_min_val;
4776 else
4777 hw->current_ifs_val +=
4778 hw->ifs_step_size;
4779 ew32(AIT, hw->current_ifs_val);
4780 }
4781 }
4782 } else {
4783 if (hw->in_ifs_mode &&
4784 (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4785 hw->current_ifs_val = 0;
4786 hw->in_ifs_mode = false;
4787 ew32(AIT, 0);
4788 }
4789 }
4790 } else {
4791 e_dbg("Not in Adaptive IFS mode!\n");
4792 }
4793 }
4794
4795 /**
4796 * e1000_get_bus_info
4797 * @hw: Struct containing variables accessed by shared code
4798 *
4799 * Gets the current PCI bus type, speed, and width of the hardware
4800 */
e1000_get_bus_info(struct e1000_hw * hw)4801 void e1000_get_bus_info(struct e1000_hw *hw)
4802 {
4803 u32 status;
4804
4805 switch (hw->mac_type) {
4806 case e1000_82542_rev2_0:
4807 case e1000_82542_rev2_1:
4808 hw->bus_type = e1000_bus_type_pci;
4809 hw->bus_speed = e1000_bus_speed_unknown;
4810 hw->bus_width = e1000_bus_width_unknown;
4811 break;
4812 default:
4813 status = er32(STATUS);
4814 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4815 e1000_bus_type_pcix : e1000_bus_type_pci;
4816
4817 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4818 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4819 e1000_bus_speed_66 : e1000_bus_speed_120;
4820 } else if (hw->bus_type == e1000_bus_type_pci) {
4821 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4822 e1000_bus_speed_66 : e1000_bus_speed_33;
4823 } else {
4824 switch (status & E1000_STATUS_PCIX_SPEED) {
4825 case E1000_STATUS_PCIX_SPEED_66:
4826 hw->bus_speed = e1000_bus_speed_66;
4827 break;
4828 case E1000_STATUS_PCIX_SPEED_100:
4829 hw->bus_speed = e1000_bus_speed_100;
4830 break;
4831 case E1000_STATUS_PCIX_SPEED_133:
4832 hw->bus_speed = e1000_bus_speed_133;
4833 break;
4834 default:
4835 hw->bus_speed = e1000_bus_speed_reserved;
4836 break;
4837 }
4838 }
4839 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4840 e1000_bus_width_64 : e1000_bus_width_32;
4841 break;
4842 }
4843 }
4844
4845 /**
4846 * e1000_write_reg_io
4847 * @hw: Struct containing variables accessed by shared code
4848 * @offset: offset to write to
4849 * @value: value to write
4850 *
4851 * Writes a value to one of the devices registers using port I/O (as opposed to
4852 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4853 */
e1000_write_reg_io(struct e1000_hw * hw,u32 offset,u32 value)4854 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
4855 {
4856 unsigned long io_addr = hw->io_base;
4857 unsigned long io_data = hw->io_base + 4;
4858
4859 e1000_io_write(hw, io_addr, offset);
4860 e1000_io_write(hw, io_data, value);
4861 }
4862
4863 /**
4864 * e1000_get_cable_length - Estimates the cable length.
4865 * @hw: Struct containing variables accessed by shared code
4866 * @min_length: The estimated minimum length
4867 * @max_length: The estimated maximum length
4868 *
4869 * returns: - E1000_ERR_XXX
4870 * E1000_SUCCESS
4871 *
4872 * This function always returns a ranged length (minimum & maximum).
4873 * So for M88 phy's, this function interprets the one value returned from the
4874 * register to the minimum and maximum range.
4875 * For IGP phy's, the function calculates the range by the AGC registers.
4876 */
e1000_get_cable_length(struct e1000_hw * hw,u16 * min_length,u16 * max_length)4877 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
4878 u16 *max_length)
4879 {
4880 s32 ret_val;
4881 u16 agc_value = 0;
4882 u16 i, phy_data;
4883 u16 cable_length;
4884
4885 *min_length = *max_length = 0;
4886
4887 /* Use old method for Phy older than IGP */
4888 if (hw->phy_type == e1000_phy_m88) {
4889 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4890 &phy_data);
4891 if (ret_val)
4892 return ret_val;
4893 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4894 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
4895
4896 /* Convert the enum value to ranged values */
4897 switch (cable_length) {
4898 case e1000_cable_length_50:
4899 *min_length = 0;
4900 *max_length = e1000_igp_cable_length_50;
4901 break;
4902 case e1000_cable_length_50_80:
4903 *min_length = e1000_igp_cable_length_50;
4904 *max_length = e1000_igp_cable_length_80;
4905 break;
4906 case e1000_cable_length_80_110:
4907 *min_length = e1000_igp_cable_length_80;
4908 *max_length = e1000_igp_cable_length_110;
4909 break;
4910 case e1000_cable_length_110_140:
4911 *min_length = e1000_igp_cable_length_110;
4912 *max_length = e1000_igp_cable_length_140;
4913 break;
4914 case e1000_cable_length_140:
4915 *min_length = e1000_igp_cable_length_140;
4916 *max_length = e1000_igp_cable_length_170;
4917 break;
4918 default:
4919 return -E1000_ERR_PHY;
4920 }
4921 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
4922 u16 cur_agc_value;
4923 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
4924 static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
4925 IGP01E1000_PHY_AGC_A,
4926 IGP01E1000_PHY_AGC_B,
4927 IGP01E1000_PHY_AGC_C,
4928 IGP01E1000_PHY_AGC_D
4929 };
4930 /* Read the AGC registers for all channels */
4931 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4932 ret_val =
4933 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
4934 if (ret_val)
4935 return ret_val;
4936
4937 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
4938
4939 /* Value bound check. */
4940 if ((cur_agc_value >=
4941 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
4942 (cur_agc_value == 0))
4943 return -E1000_ERR_PHY;
4944
4945 agc_value += cur_agc_value;
4946
4947 /* Update minimal AGC value. */
4948 if (min_agc_value > cur_agc_value)
4949 min_agc_value = cur_agc_value;
4950 }
4951
4952 /* Remove the minimal AGC result for length < 50m */
4953 if (agc_value <
4954 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
4955 agc_value -= min_agc_value;
4956
4957 /* Get the average length of the remaining 3 channels */
4958 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
4959 } else {
4960 /* Get the average length of all the 4 channels. */
4961 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
4962 }
4963
4964 /* Set the range of the calculated length. */
4965 *min_length = ((e1000_igp_cable_length_table[agc_value] -
4966 IGP01E1000_AGC_RANGE) > 0) ?
4967 (e1000_igp_cable_length_table[agc_value] -
4968 IGP01E1000_AGC_RANGE) : 0;
4969 *max_length = e1000_igp_cable_length_table[agc_value] +
4970 IGP01E1000_AGC_RANGE;
4971 }
4972
4973 return E1000_SUCCESS;
4974 }
4975
4976 /**
4977 * e1000_check_polarity - Check the cable polarity
4978 * @hw: Struct containing variables accessed by shared code
4979 * @polarity: output parameter : 0 - Polarity is not reversed
4980 * 1 - Polarity is reversed.
4981 *
4982 * returns: - E1000_ERR_XXX
4983 * E1000_SUCCESS
4984 *
4985 * For phy's older than IGP, this function simply reads the polarity bit in the
4986 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
4987 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
4988 * return 0. If the link speed is 1000 Mbps the polarity status is in the
4989 * IGP01E1000_PHY_PCS_INIT_REG.
4990 */
e1000_check_polarity(struct e1000_hw * hw,e1000_rev_polarity * polarity)4991 static s32 e1000_check_polarity(struct e1000_hw *hw,
4992 e1000_rev_polarity *polarity)
4993 {
4994 s32 ret_val;
4995 u16 phy_data;
4996
4997 if (hw->phy_type == e1000_phy_m88) {
4998 /* return the Polarity bit in the Status register. */
4999 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5000 &phy_data);
5001 if (ret_val)
5002 return ret_val;
5003 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
5004 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
5005 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
5006
5007 } else if (hw->phy_type == e1000_phy_igp) {
5008 /* Read the Status register to check the speed */
5009 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
5010 &phy_data);
5011 if (ret_val)
5012 return ret_val;
5013
5014 /* If speed is 1000 Mbps, must read the
5015 * IGP01E1000_PHY_PCS_INIT_REG to find the polarity status
5016 */
5017 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
5018 IGP01E1000_PSSR_SPEED_1000MBPS) {
5019 /* Read the GIG initialization PCS register (0x00B4) */
5020 ret_val =
5021 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
5022 &phy_data);
5023 if (ret_val)
5024 return ret_val;
5025
5026 /* Check the polarity bits */
5027 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
5028 e1000_rev_polarity_reversed :
5029 e1000_rev_polarity_normal;
5030 } else {
5031 /* For 10 Mbps, read the polarity bit in the status
5032 * register. (for 100 Mbps this bit is always 0)
5033 */
5034 *polarity =
5035 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
5036 e1000_rev_polarity_reversed :
5037 e1000_rev_polarity_normal;
5038 }
5039 }
5040 return E1000_SUCCESS;
5041 }
5042
5043 /**
5044 * e1000_check_downshift - Check if Downshift occurred
5045 * @hw: Struct containing variables accessed by shared code
5046 *
5047 * returns: - E1000_ERR_XXX
5048 * E1000_SUCCESS
5049 *
5050 * For phy's older than IGP, this function reads the Downshift bit in the Phy
5051 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
5052 * Link Health register. In IGP this bit is latched high, so the driver must
5053 * read it immediately after link is established.
5054 */
e1000_check_downshift(struct e1000_hw * hw)5055 static s32 e1000_check_downshift(struct e1000_hw *hw)
5056 {
5057 s32 ret_val;
5058 u16 phy_data;
5059
5060 if (hw->phy_type == e1000_phy_igp) {
5061 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
5062 &phy_data);
5063 if (ret_val)
5064 return ret_val;
5065
5066 hw->speed_downgraded =
5067 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
5068 } else if (hw->phy_type == e1000_phy_m88) {
5069 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5070 &phy_data);
5071 if (ret_val)
5072 return ret_val;
5073
5074 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
5075 M88E1000_PSSR_DOWNSHIFT_SHIFT;
5076 }
5077
5078 return E1000_SUCCESS;
5079 }
5080
5081 static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
5082 IGP01E1000_PHY_AGC_PARAM_A,
5083 IGP01E1000_PHY_AGC_PARAM_B,
5084 IGP01E1000_PHY_AGC_PARAM_C,
5085 IGP01E1000_PHY_AGC_PARAM_D
5086 };
5087
e1000_1000Mb_check_cable_length(struct e1000_hw * hw)5088 static s32 e1000_1000Mb_check_cable_length(struct e1000_hw *hw)
5089 {
5090 u16 min_length, max_length;
5091 u16 phy_data, i;
5092 s32 ret_val;
5093
5094 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
5095 if (ret_val)
5096 return ret_val;
5097
5098 if (hw->dsp_config_state != e1000_dsp_config_enabled)
5099 return 0;
5100
5101 if (min_length >= e1000_igp_cable_length_50) {
5102 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5103 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
5104 &phy_data);
5105 if (ret_val)
5106 return ret_val;
5107
5108 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5109
5110 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
5111 phy_data);
5112 if (ret_val)
5113 return ret_val;
5114 }
5115 hw->dsp_config_state = e1000_dsp_config_activated;
5116 } else {
5117 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5118 u32 idle_errs = 0;
5119
5120 /* clear previous idle error counts */
5121 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
5122 if (ret_val)
5123 return ret_val;
5124
5125 for (i = 0; i < ffe_idle_err_timeout; i++) {
5126 udelay(1000);
5127 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5128 &phy_data);
5129 if (ret_val)
5130 return ret_val;
5131
5132 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
5133 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
5134 hw->ffe_config_state = e1000_ffe_config_active;
5135
5136 ret_val = e1000_write_phy_reg(hw,
5137 IGP01E1000_PHY_DSP_FFE,
5138 IGP01E1000_PHY_DSP_FFE_CM_CP);
5139 if (ret_val)
5140 return ret_val;
5141 break;
5142 }
5143
5144 if (idle_errs)
5145 ffe_idle_err_timeout =
5146 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5147 }
5148 }
5149
5150 return 0;
5151 }
5152
5153 /**
5154 * e1000_config_dsp_after_link_change
5155 * @hw: Struct containing variables accessed by shared code
5156 * @link_up: was link up at the time this was called
5157 *
5158 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5159 * E1000_SUCCESS at any other case.
5160 *
5161 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
5162 * gigabit link is achieved to improve link quality.
5163 */
5164
e1000_config_dsp_after_link_change(struct e1000_hw * hw,bool link_up)5165 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
5166 {
5167 s32 ret_val;
5168 u16 phy_data, phy_saved_data, speed, duplex, i;
5169
5170 if (hw->phy_type != e1000_phy_igp)
5171 return E1000_SUCCESS;
5172
5173 if (link_up) {
5174 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
5175 if (ret_val) {
5176 e_dbg("Error getting link speed and duplex\n");
5177 return ret_val;
5178 }
5179
5180 if (speed == SPEED_1000) {
5181 ret_val = e1000_1000Mb_check_cable_length(hw);
5182 if (ret_val)
5183 return ret_val;
5184 }
5185 } else {
5186 if (hw->dsp_config_state == e1000_dsp_config_activated) {
5187 /* Save off the current value of register 0x2F5B to be
5188 * restored at the end of the routines.
5189 */
5190 ret_val =
5191 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5192
5193 if (ret_val)
5194 return ret_val;
5195
5196 /* Disable the PHY transmitter */
5197 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5198
5199 if (ret_val)
5200 return ret_val;
5201
5202 msleep(20);
5203
5204 ret_val = e1000_write_phy_reg(hw, 0x0000,
5205 IGP01E1000_IEEE_FORCE_GIGA);
5206 if (ret_val)
5207 return ret_val;
5208 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5209 ret_val =
5210 e1000_read_phy_reg(hw, dsp_reg_array[i],
5211 &phy_data);
5212 if (ret_val)
5213 return ret_val;
5214
5215 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5216 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5217
5218 ret_val =
5219 e1000_write_phy_reg(hw, dsp_reg_array[i],
5220 phy_data);
5221 if (ret_val)
5222 return ret_val;
5223 }
5224
5225 ret_val = e1000_write_phy_reg(hw, 0x0000,
5226 IGP01E1000_IEEE_RESTART_AUTONEG);
5227 if (ret_val)
5228 return ret_val;
5229
5230 msleep(20);
5231
5232 /* Now enable the transmitter */
5233 ret_val =
5234 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5235
5236 if (ret_val)
5237 return ret_val;
5238
5239 hw->dsp_config_state = e1000_dsp_config_enabled;
5240 }
5241
5242 if (hw->ffe_config_state == e1000_ffe_config_active) {
5243 /* Save off the current value of register 0x2F5B to be
5244 * restored at the end of the routines.
5245 */
5246 ret_val =
5247 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5248
5249 if (ret_val)
5250 return ret_val;
5251
5252 /* Disable the PHY transmitter */
5253 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5254
5255 if (ret_val)
5256 return ret_val;
5257
5258 msleep(20);
5259
5260 ret_val = e1000_write_phy_reg(hw, 0x0000,
5261 IGP01E1000_IEEE_FORCE_GIGA);
5262 if (ret_val)
5263 return ret_val;
5264 ret_val =
5265 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5266 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5267 if (ret_val)
5268 return ret_val;
5269
5270 ret_val = e1000_write_phy_reg(hw, 0x0000,
5271 IGP01E1000_IEEE_RESTART_AUTONEG);
5272 if (ret_val)
5273 return ret_val;
5274
5275 msleep(20);
5276
5277 /* Now enable the transmitter */
5278 ret_val =
5279 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5280
5281 if (ret_val)
5282 return ret_val;
5283
5284 hw->ffe_config_state = e1000_ffe_config_enabled;
5285 }
5286 }
5287 return E1000_SUCCESS;
5288 }
5289
5290 /**
5291 * e1000_set_phy_mode - Set PHY to class A mode
5292 * @hw: Struct containing variables accessed by shared code
5293 *
5294 * Assumes the following operations will follow to enable the new class mode.
5295 * 1. Do a PHY soft reset
5296 * 2. Restart auto-negotiation or force link.
5297 */
e1000_set_phy_mode(struct e1000_hw * hw)5298 static s32 e1000_set_phy_mode(struct e1000_hw *hw)
5299 {
5300 s32 ret_val;
5301 u16 eeprom_data;
5302
5303 if ((hw->mac_type == e1000_82545_rev_3) &&
5304 (hw->media_type == e1000_media_type_copper)) {
5305 ret_val =
5306 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
5307 &eeprom_data);
5308 if (ret_val)
5309 return ret_val;
5310
5311 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
5312 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5313 ret_val =
5314 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5315 0x000B);
5316 if (ret_val)
5317 return ret_val;
5318 ret_val =
5319 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
5320 0x8104);
5321 if (ret_val)
5322 return ret_val;
5323
5324 hw->phy_reset_disable = false;
5325 }
5326 }
5327
5328 return E1000_SUCCESS;
5329 }
5330
5331 /**
5332 * e1000_set_d3_lplu_state - set d3 link power state
5333 * @hw: Struct containing variables accessed by shared code
5334 * @active: true to enable lplu false to disable lplu.
5335 *
5336 * This function sets the lplu state according to the active flag. When
5337 * activating lplu this function also disables smart speed and vise versa.
5338 * lplu will not be activated unless the device autonegotiation advertisement
5339 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5340 *
5341 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5342 * E1000_SUCCESS at any other case.
5343 */
e1000_set_d3_lplu_state(struct e1000_hw * hw,bool active)5344 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
5345 {
5346 s32 ret_val;
5347 u16 phy_data;
5348
5349 if (hw->phy_type != e1000_phy_igp)
5350 return E1000_SUCCESS;
5351
5352 /* During driver activity LPLU should not be used or it will attain link
5353 * from the lowest speeds starting from 10Mbps. The capability is used
5354 * for Dx transitions and states
5355 */
5356 if (hw->mac_type == e1000_82541_rev_2 ||
5357 hw->mac_type == e1000_82547_rev_2) {
5358 ret_val =
5359 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5360 if (ret_val)
5361 return ret_val;
5362 }
5363
5364 if (!active) {
5365 if (hw->mac_type == e1000_82541_rev_2 ||
5366 hw->mac_type == e1000_82547_rev_2) {
5367 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5368 ret_val =
5369 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5370 phy_data);
5371 if (ret_val)
5372 return ret_val;
5373 }
5374
5375 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
5376 * during Dx states where the power conservation is most
5377 * important. During driver activity we should enable
5378 * SmartSpeed, so performance is maintained.
5379 */
5380 if (hw->smart_speed == e1000_smart_speed_on) {
5381 ret_val =
5382 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5383 &phy_data);
5384 if (ret_val)
5385 return ret_val;
5386
5387 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5388 ret_val =
5389 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5390 phy_data);
5391 if (ret_val)
5392 return ret_val;
5393 } else if (hw->smart_speed == e1000_smart_speed_off) {
5394 ret_val =
5395 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5396 &phy_data);
5397 if (ret_val)
5398 return ret_val;
5399
5400 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5401 ret_val =
5402 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5403 phy_data);
5404 if (ret_val)
5405 return ret_val;
5406 }
5407 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
5408 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
5409 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5410 if (hw->mac_type == e1000_82541_rev_2 ||
5411 hw->mac_type == e1000_82547_rev_2) {
5412 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5413 ret_val =
5414 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5415 phy_data);
5416 if (ret_val)
5417 return ret_val;
5418 }
5419
5420 /* When LPLU is enabled we should disable SmartSpeed */
5421 ret_val =
5422 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5423 &phy_data);
5424 if (ret_val)
5425 return ret_val;
5426
5427 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5428 ret_val =
5429 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5430 phy_data);
5431 if (ret_val)
5432 return ret_val;
5433 }
5434 return E1000_SUCCESS;
5435 }
5436
5437 /**
5438 * e1000_set_vco_speed
5439 * @hw: Struct containing variables accessed by shared code
5440 *
5441 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
5442 */
e1000_set_vco_speed(struct e1000_hw * hw)5443 static s32 e1000_set_vco_speed(struct e1000_hw *hw)
5444 {
5445 s32 ret_val;
5446 u16 default_page = 0;
5447 u16 phy_data;
5448
5449 switch (hw->mac_type) {
5450 case e1000_82545_rev_3:
5451 case e1000_82546_rev_3:
5452 break;
5453 default:
5454 return E1000_SUCCESS;
5455 }
5456
5457 /* Set PHY register 30, page 5, bit 8 to 0 */
5458
5459 ret_val =
5460 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5461 if (ret_val)
5462 return ret_val;
5463
5464 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5465 if (ret_val)
5466 return ret_val;
5467
5468 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5469 if (ret_val)
5470 return ret_val;
5471
5472 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5473 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5474 if (ret_val)
5475 return ret_val;
5476
5477 /* Set PHY register 30, page 4, bit 11 to 1 */
5478
5479 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5480 if (ret_val)
5481 return ret_val;
5482
5483 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5484 if (ret_val)
5485 return ret_val;
5486
5487 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5488 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5489 if (ret_val)
5490 return ret_val;
5491
5492 ret_val =
5493 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5494 if (ret_val)
5495 return ret_val;
5496
5497 return E1000_SUCCESS;
5498 }
5499
5500 /**
5501 * e1000_enable_mng_pass_thru - check for bmc pass through
5502 * @hw: Struct containing variables accessed by shared code
5503 *
5504 * Verifies the hardware needs to allow ARPs to be processed by the host
5505 * returns: - true/false
5506 */
e1000_enable_mng_pass_thru(struct e1000_hw * hw)5507 u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
5508 {
5509 u32 manc;
5510
5511 if (hw->asf_firmware_present) {
5512 manc = er32(MANC);
5513
5514 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
5515 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
5516 return false;
5517 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
5518 return true;
5519 }
5520 return false;
5521 }
5522
e1000_polarity_reversal_workaround(struct e1000_hw * hw)5523 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5524 {
5525 s32 ret_val;
5526 u16 mii_status_reg;
5527 u16 i;
5528
5529 /* Polarity reversal workaround for forced 10F/10H links. */
5530
5531 /* Disable the transmitter on the PHY */
5532
5533 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5534 if (ret_val)
5535 return ret_val;
5536 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
5537 if (ret_val)
5538 return ret_val;
5539
5540 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5541 if (ret_val)
5542 return ret_val;
5543
5544 /* This loop will early-out if the NO link condition has been met. */
5545 for (i = PHY_FORCE_TIME; i > 0; i--) {
5546 /* Read the MII Status Register and wait for Link Status bit
5547 * to be clear.
5548 */
5549
5550 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5551 if (ret_val)
5552 return ret_val;
5553
5554 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5555 if (ret_val)
5556 return ret_val;
5557
5558 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
5559 break;
5560 msleep(100);
5561 }
5562
5563 /* Recommended delay time after link has been lost */
5564 msleep(1000);
5565
5566 /* Now we will re-enable th transmitter on the PHY */
5567
5568 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5569 if (ret_val)
5570 return ret_val;
5571 msleep(50);
5572 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
5573 if (ret_val)
5574 return ret_val;
5575 msleep(50);
5576 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
5577 if (ret_val)
5578 return ret_val;
5579 msleep(50);
5580 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
5581 if (ret_val)
5582 return ret_val;
5583
5584 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5585 if (ret_val)
5586 return ret_val;
5587
5588 /* This loop will early-out if the link condition has been met. */
5589 for (i = PHY_FORCE_TIME; i > 0; i--) {
5590 /* Read the MII Status Register and wait for Link Status bit
5591 * to be set.
5592 */
5593
5594 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5595 if (ret_val)
5596 return ret_val;
5597
5598 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5599 if (ret_val)
5600 return ret_val;
5601
5602 if (mii_status_reg & MII_SR_LINK_STATUS)
5603 break;
5604 msleep(100);
5605 }
5606 return E1000_SUCCESS;
5607 }
5608
5609 /**
5610 * e1000_get_auto_rd_done
5611 * @hw: Struct containing variables accessed by shared code
5612 *
5613 * Check for EEPROM Auto Read bit done.
5614 * returns: - E1000_ERR_RESET if fail to reset MAC
5615 * E1000_SUCCESS at any other case.
5616 */
e1000_get_auto_rd_done(struct e1000_hw * hw)5617 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
5618 {
5619 msleep(5);
5620 return E1000_SUCCESS;
5621 }
5622
5623 /**
5624 * e1000_get_phy_cfg_done
5625 * @hw: Struct containing variables accessed by shared code
5626 *
5627 * Checks if the PHY configuration is done
5628 * returns: - E1000_ERR_RESET if fail to reset MAC
5629 * E1000_SUCCESS at any other case.
5630 */
e1000_get_phy_cfg_done(struct e1000_hw * hw)5631 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
5632 {
5633 msleep(10);
5634 return E1000_SUCCESS;
5635 }
5636
