1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2014 Samsung Electronics Co.Ltd 4 */ 5 6 #ifndef EXYNOS_REGS_DECON5433_H 7 #define EXYNOS_REGS_DECON5433_H 8 9 /* Exynos543X DECON */ 10 #define DECON_VIDCON0 0x0000 11 #define DECON_VIDOUTCON0 0x0010 12 #define DECON_WINCONx(n) (0x0020 + ((n) * 4)) 13 #define DECON_VIDOSDxH(n) (0x0080 + ((n) * 4)) 14 #define DECON_SHADOWCON 0x00A0 15 #define DECON_VIDOSDxA(n) (0x00B0 + ((n) * 0x20)) 16 #define DECON_VIDOSDxB(n) (0x00B4 + ((n) * 0x20)) 17 #define DECON_VIDOSDxC(n) (0x00B8 + ((n) * 0x20)) 18 #define DECON_VIDOSDxD(n) (0x00BC + ((n) * 0x20)) 19 #define DECON_VIDOSDxE(n) (0x00C0 + ((n) * 0x20)) 20 #define DECON_VIDW0xADD0B0(n) (0x0150 + ((n) * 0x10)) 21 #define DECON_VIDW0xADD0B1(n) (0x0154 + ((n) * 0x10)) 22 #define DECON_VIDW0xADD0B2(n) (0x0158 + ((n) * 0x10)) 23 #define DECON_VIDW0xADD1B0(n) (0x01A0 + ((n) * 0x10)) 24 #define DECON_VIDW0xADD1B1(n) (0x01A4 + ((n) * 0x10)) 25 #define DECON_VIDW0xADD1B2(n) (0x01A8 + ((n) * 0x10)) 26 #define DECON_VIDW0xADD2(n) (0x0200 + ((n) * 4)) 27 #define DECON_LOCALxSIZE(n) (0x0214 + ((n) * 4)) 28 #define DECON_VIDINTCON0 0x0220 29 #define DECON_VIDINTCON1 0x0224 30 #define DECON_WxKEYCON0(n) (0x0230 + ((n - 1) * 8)) 31 #define DECON_WxKEYCON1(n) (0x0234 + ((n - 1) * 8)) 32 #define DECON_WxKEYALPHA(n) (0x0250 + ((n - 1) * 4)) 33 #define DECON_WINxMAP(n) (0x0270 + ((n) * 4)) 34 #define DECON_QOSLUT07_00 0x02C0 35 #define DECON_QOSLUT15_08 0x02C4 36 #define DECON_QOSCTRL 0x02C8 37 #define DECON_BLENDERQx(n) (0x0300 + ((n - 1) * 4)) 38 #define DECON_BLENDCON 0x0310 39 #define DECON_OPE_VIDW0xADD0(n) (0x0400 + ((n) * 4)) 40 #define DECON_OPE_VIDW0xADD1(n) (0x0414 + ((n) * 4)) 41 #define DECON_FRAMEFIFO_REG7 0x051C 42 #define DECON_FRAMEFIFO_REG8 0x0520 43 #define DECON_FRAMEFIFO_STATUS 0x0524 44 #define DECON_CMU 0x1404 45 #define DECON_UPDATE 0x1410 46 #define DECON_CRFMID 0x1414 47 #define DECON_UPDATE_SCHEME 0x1438 48 #define DECON_VIDCON1 0x2000 49 #define DECON_VIDCON2 0x2004 50 #define DECON_VIDCON3 0x2008 51 #define DECON_VIDCON4 0x200C 52 #define DECON_VIDTCON2 0x2028 53 #define DECON_FRAME_SIZE 0x2038 54 #define DECON_LINECNT_OP_THRESHOLD 0x203C 55 #define DECON_TRIGCON 0x2040 56 #define DECON_TRIGSKIP 0x2050 57 #define DECON_CRCRDATA 0x20B0 58 #define DECON_CRCCTRL 0x20B4 59 60 /* Exynos5430 DECON */ 61 #define DECON_VIDTCON0 0x2020 62 #define DECON_VIDTCON1 0x2024 63 64 /* Exynos5433 DECON */ 65 #define DECON_VIDTCON00 0x2010 66 #define DECON_VIDTCON01 0x2014 67 #define DECON_VIDTCON10 0x2018 68 #define DECON_VIDTCON11 0x201C 69 70 /* Exynos543X DECON Internal */ 71 #define DECON_W013DSTREOCON 0x0320 72 #define DECON_W233DSTREOCON 0x0324 73 #define DECON_FRAMEFIFO_REG0 0x0500 74 #define DECON_ENHANCER_CTRL 0x2100 75 76 /* Exynos543X DECON TV */ 77 #define DECON_VCLKCON0 0x0014 78 #define DECON_VIDINTCON2 0x0228 79 #define DECON_VIDINTCON3 0x022C 80 81 /* VIDCON0 */ 82 #define VIDCON0_SWRESET (1 << 28) 83 #define VIDCON0_CLKVALUP (1 << 14) 84 #define VIDCON0_VLCKFREE (1 << 5) 85 #define VIDCON0_STOP_STATUS (1 << 2) 86 #define VIDCON0_ENVID (1 << 1) 87 #define VIDCON0_ENVID_F (1 << 0) 88 89 /* VIDOUTCON0 */ 90 #define VIDOUT_INTERLACE_FIELD_F (1 << 29) 91 #define VIDOUT_INTERLACE_EN_F (1 << 28) 92 #define VIDOUT_LCD_ON (1 << 24) 93 #define VIDOUT_IF_F_MASK (0x3 << 20) 94 #define VIDOUT_RGB_IF (0x0 << 20) 95 #define VIDOUT_COMMAND_IF (0x2 << 20) 96 97 /* WINCONx */ 98 #define WINCONx_HAWSWP_F (1 << 16) 99 #define WINCONx_WSWP_F (1 << 15) 100 #define WINCONx_BURSTLEN_MASK (0x3 << 10) 101 #define WINCONx_BURSTLEN_16WORD (0x0 << 10) 102 #define WINCONx_BURSTLEN_8WORD (0x1 << 10) 103 #define WINCONx_BURSTLEN_4WORD (0x2 << 10) 104 #define WINCONx_ALPHA_MUL_F (1 << 7) 105 #define WINCONx_BLD_PIX_F (1 << 6) 106 #define WINCONx_BPPMODE_MASK (0xf << 2) 107 #define WINCONx_BPPMODE_16BPP_565 (0x5 << 2) 108 #define WINCONx_BPPMODE_16BPP_A1555 (0x6 << 2) 109 #define WINCONx_BPPMODE_16BPP_I1555 (0x7 << 2) 110 #define WINCONx_BPPMODE_24BPP_888 (0xb << 2) 111 #define WINCONx_BPPMODE_24BPP_A1887 (0xc << 2) 112 #define WINCONx_BPPMODE_25BPP_A1888 (0xd << 2) 113 #define WINCONx_BPPMODE_32BPP_A8888 (0xd << 2) 114 #define WINCONx_BPPMODE_16BPP_A4444 (0xe << 2) 115 #define WINCONx_ALPHA_SEL_F (1 << 1) 116 #define WINCONx_ENWIN_F (1 << 0) 117 #define WINCONx_BLEND_MODE_MASK (0xc2) 118 119 /* SHADOWCON */ 120 #define SHADOWCON_PROTECT_MASK GENMASK(14, 10) 121 #define SHADOWCON_Wx_PROTECT(n) (1 << (10 + (n))) 122 123 /* VIDOSDxC */ 124 #define VIDOSDxC_ALPHA0_RGB_MASK (0xffffff) 125 126 /* VIDOSDxD */ 127 #define VIDOSD_Wx_ALPHA_R_F(n) (((n) & 0xff) << 16) 128 #define VIDOSD_Wx_ALPHA_G_F(n) (((n) & 0xff) << 8) 129 #define VIDOSD_Wx_ALPHA_B_F(n) (((n) & 0xff) << 0) 130 131 /* VIDINTCON0 */ 132 #define VIDINTCON0_FRAMEDONE (1 << 17) 133 #define VIDINTCON0_FRAMESEL_BP (0 << 15) 134 #define VIDINTCON0_FRAMESEL_VS (1 << 15) 135 #define VIDINTCON0_FRAMESEL_AC (2 << 15) 136 #define VIDINTCON0_FRAMESEL_FP (3 << 15) 137 #define VIDINTCON0_INTFRMEN (1 << 12) 138 #define VIDINTCON0_INTEN (1 << 0) 139 140 /* VIDINTCON1 */ 141 #define VIDINTCON1_INTFRMDONEPEND (1 << 2) 142 #define VIDINTCON1_INTFRMPEND (1 << 1) 143 #define VIDINTCON1_INTFIFOPEND (1 << 0) 144 145 /* DECON_CMU */ 146 #define CMU_CLKGAGE_MODE_SFR_F (1 << 1) 147 #define CMU_CLKGAGE_MODE_MEM_F (1 << 0) 148 149 /* DECON_UPDATE */ 150 #define STANDALONE_UPDATE_F (1 << 0) 151 152 /* DECON_VIDCON1 */ 153 #define VIDCON1_LINECNT_MASK (0x0fff << 16) 154 #define VIDCON1_I80_ACTIVE (1 << 15) 155 #define VIDCON1_VSTATUS_MASK (0x3 << 13) 156 #define VIDCON1_VSTATUS_VS (0 << 13) 157 #define VIDCON1_VSTATUS_BP (1 << 13) 158 #define VIDCON1_VSTATUS_AC (2 << 13) 159 #define VIDCON1_VSTATUS_FP (3 << 13) 160 #define VIDCON1_VCLK_MASK (0x3 << 9) 161 #define VIDCON1_VCLK_RUN_VDEN_DISABLE (0x3 << 9) 162 #define VIDCON1_VCLK_HOLD (0x0 << 9) 163 #define VIDCON1_VCLK_RUN (0x1 << 9) 164 165 166 /* DECON_VIDTCON00 */ 167 #define VIDTCON00_VBPD_F(x) (((x) & 0xfff) << 16) 168 #define VIDTCON00_VFPD_F(x) ((x) & 0xfff) 169 170 /* DECON_VIDTCON01 */ 171 #define VIDTCON01_VSPW_F(x) (((x) & 0xfff) << 16) 172 173 /* DECON_VIDTCON10 */ 174 #define VIDTCON10_HBPD_F(x) (((x) & 0xfff) << 16) 175 #define VIDTCON10_HFPD_F(x) ((x) & 0xfff) 176 177 /* DECON_VIDTCON11 */ 178 #define VIDTCON11_HSPW_F(x) (((x) & 0xfff) << 16) 179 180 /* DECON_VIDTCON2 */ 181 #define VIDTCON2_LINEVAL(x) (((x) & 0xfff) << 16) 182 #define VIDTCON2_HOZVAL(x) ((x) & 0xfff) 183 184 /* TRIGCON */ 185 #define TRIGCON_TRIGEN_PER_F (1 << 31) 186 #define TRIGCON_TRIGEN_F (1 << 30) 187 #define TRIGCON_TE_AUTO_MASK (1 << 29) 188 #define TRIGCON_WB_SWTRIGCMD (1 << 28) 189 #define TRIGCON_SWTRIGCMD_W4BUF (1 << 26) 190 #define TRIGCON_TRIGMODE_W4BUF (1 << 25) 191 #define TRIGCON_SWTRIGCMD_W3BUF (1 << 21) 192 #define TRIGCON_TRIGMODE_W3BUF (1 << 20) 193 #define TRIGCON_SWTRIGCMD_W2BUF (1 << 16) 194 #define TRIGCON_TRIGMODE_W2BUF (1 << 15) 195 #define TRIGCON_SWTRIGCMD_W1BUF (1 << 11) 196 #define TRIGCON_TRIGMODE_W1BUF (1 << 10) 197 #define TRIGCON_SWTRIGCMD_W0BUF (1 << 6) 198 #define TRIGCON_TRIGMODE_W0BUF (1 << 5) 199 #define TRIGCON_HWTRIGMASK (1 << 4) 200 #define TRIGCON_HWTRIGEN (1 << 3) 201 #define TRIGCON_HWTRIG_INV (1 << 2) 202 #define TRIGCON_SWTRIGCMD (1 << 1) 203 #define TRIGCON_SWTRIGEN (1 << 0) 204 205 /* DECON_CRCCTRL */ 206 #define CRCCTRL_CRCCLKEN (0x1 << 2) 207 #define CRCCTRL_CRCSTART_F (0x1 << 1) 208 #define CRCCTRL_CRCEN (0x1 << 0) 209 #define CRCCTRL_MASK (0x7) 210 211 /* BLENDCON */ 212 #define BLEND_NEW (1 << 0) 213 214 /* BLENDERQx */ 215 #define BLENDERQ_ZERO 0x0 216 #define BLENDERQ_ONE 0x1 217 #define BLENDERQ_ALPHA_A 0x2 218 #define BLENDERQ_ONE_MINUS_ALPHA_A 0x3 219 #define BLENDERQ_ALPHA0 0x6 220 #define BLENDERQ_Q_FUNC_F(n) (n << 18) 221 #define BLENDERQ_P_FUNC_F(n) (n << 12) 222 #define BLENDERQ_B_FUNC_F(n) (n << 6) 223 #define BLENDERQ_A_FUNC_F(n) (n << 0) 224 225 /* BLENDCON */ 226 #define BLEND_NEW (1 << 0) 227 228 #endif /* EXYNOS_REGS_DECON5433_H */ 229
