1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _LINUX_IRQ_H
3 #define _LINUX_IRQ_H
4
5 /*
6 * Please do not include this file in generic code. There is currently
7 * no requirement for any architecture to implement anything held
8 * within this file.
9 *
10 * Thanks. --rmk
11 */
12
13 #include <linux/cache.h>
14 #include <linux/spinlock.h>
15 #include <linux/cpumask.h>
16 #include <linux/irqhandler.h>
17 #include <linux/irqreturn.h>
18 #include <linux/irqnr.h>
19 #include <linux/topology.h>
20 #include <linux/io.h>
21 #include <linux/slab.h>
22
23 #include <asm/irq.h>
24 #include <asm/ptrace.h>
25 #include <asm/irq_regs.h>
26
27 struct seq_file;
28 struct module;
29 struct msi_msg;
30 enum irqchip_irq_state;
31
32 /*
33 * IRQ line status.
34 *
35 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
36 *
37 * IRQ_TYPE_NONE - default, unspecified type
38 * IRQ_TYPE_EDGE_RISING - rising edge triggered
39 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
40 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
41 * IRQ_TYPE_LEVEL_HIGH - high level triggered
42 * IRQ_TYPE_LEVEL_LOW - low level triggered
43 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
44 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
45 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
46 * to setup the HW to a sane default (used
47 * by irqdomain map() callbacks to synchronize
48 * the HW state and SW flags for a newly
49 * allocated descriptor).
50 *
51 * IRQ_TYPE_PROBE - Special flag for probing in progress
52 *
53 * Bits which can be modified via irq_set/clear/modify_status_flags()
54 * IRQ_LEVEL - Interrupt is level type. Will be also
55 * updated in the code when the above trigger
56 * bits are modified via irq_set_irq_type()
57 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
58 * it from affinity setting
59 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
60 * IRQ_NOREQUEST - Interrupt cannot be requested via
61 * request_irq()
62 * IRQ_NOTHREAD - Interrupt cannot be threaded
63 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
64 * request/setup_irq()
65 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
66 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
67 * IRQ_NESTED_THREAD - Interrupt nests into another thread
68 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
69 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
70 * it from the spurious interrupt detection
71 * mechanism and from core side polling.
72 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
73 */
74 enum {
75 IRQ_TYPE_NONE = 0x00000000,
76 IRQ_TYPE_EDGE_RISING = 0x00000001,
77 IRQ_TYPE_EDGE_FALLING = 0x00000002,
78 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
79 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
80 IRQ_TYPE_LEVEL_LOW = 0x00000008,
81 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
82 IRQ_TYPE_SENSE_MASK = 0x0000000f,
83 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
84
85 IRQ_TYPE_PROBE = 0x00000010,
86
87 IRQ_LEVEL = (1 << 8),
88 IRQ_PER_CPU = (1 << 9),
89 IRQ_NOPROBE = (1 << 10),
90 IRQ_NOREQUEST = (1 << 11),
91 IRQ_NOAUTOEN = (1 << 12),
92 IRQ_NO_BALANCING = (1 << 13),
93 IRQ_MOVE_PCNTXT = (1 << 14),
94 IRQ_NESTED_THREAD = (1 << 15),
95 IRQ_NOTHREAD = (1 << 16),
96 IRQ_PER_CPU_DEVID = (1 << 17),
97 IRQ_IS_POLLED = (1 << 18),
98 IRQ_DISABLE_UNLAZY = (1 << 19),
99 };
100
101 #define IRQF_MODIFY_MASK \
102 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
103 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
104 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
105 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY)
106
107 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
108
109 /*
110 * Return value for chip->irq_set_affinity()
111 *
112 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
113 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
114 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
115 * support stacked irqchips, which indicates skipping
116 * all descendent irqchips.
117 */
118 enum {
119 IRQ_SET_MASK_OK = 0,
120 IRQ_SET_MASK_OK_NOCOPY,
121 IRQ_SET_MASK_OK_DONE,
122 };
123
124 struct msi_desc;
125 struct irq_domain;
126
127 /**
128 * struct irq_common_data - per irq data shared by all irqchips
129 * @state_use_accessors: status information for irq chip functions.
130 * Use accessor functions to deal with it
131 * @node: node index useful for balancing
132 * @handler_data: per-IRQ data for the irq_chip methods
133 * @affinity: IRQ affinity on SMP. If this is an IPI
134 * related irq, then this is the mask of the
135 * CPUs to which an IPI can be sent.
136 * @effective_affinity: The effective IRQ affinity on SMP as some irq
137 * chips do not allow multi CPU destinations.
138 * A subset of @affinity.
139 * @msi_desc: MSI descriptor
140 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional.
141 */
142 struct irq_common_data {
143 unsigned int __private state_use_accessors;
144 #ifdef CONFIG_NUMA
145 unsigned int node;
146 #endif
147 void *handler_data;
148 struct msi_desc *msi_desc;
149 cpumask_var_t affinity;
150 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
151 cpumask_var_t effective_affinity;
152 #endif
153 #ifdef CONFIG_GENERIC_IRQ_IPI
154 unsigned int ipi_offset;
155 #endif
156 };
157
158 /**
159 * struct irq_data - per irq chip data passed down to chip functions
160 * @mask: precomputed bitmask for accessing the chip registers
161 * @irq: interrupt number
162 * @hwirq: hardware interrupt number, local to the interrupt domain
163 * @common: point to data shared by all irqchips
164 * @chip: low level interrupt hardware access
165 * @domain: Interrupt translation domain; responsible for mapping
166 * between hwirq number and linux irq number.
167 * @parent_data: pointer to parent struct irq_data to support hierarchy
168 * irq_domain
169 * @chip_data: platform-specific per-chip private data for the chip
170 * methods, to allow shared chip implementations
171 */
172 struct irq_data {
173 u32 mask;
174 unsigned int irq;
175 unsigned long hwirq;
176 struct irq_common_data *common;
177 struct irq_chip *chip;
178 struct irq_domain *domain;
179 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
180 struct irq_data *parent_data;
181 #endif
182 void *chip_data;
183 };
184
185 /*
186 * Bit masks for irq_common_data.state_use_accessors
187 *
188 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
189 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
190 * IRQD_ACTIVATED - Interrupt has already been activated
191 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
192 * IRQD_PER_CPU - Interrupt is per cpu
193 * IRQD_AFFINITY_SET - Interrupt affinity was set
194 * IRQD_LEVEL - Interrupt is level triggered
195 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
196 * from suspend
197 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
198 * context
199 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
200 * IRQD_IRQ_MASKED - Masked state of the interrupt
201 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
202 * IRQD_WAKEUP_ARMED - Wakeup mode armed
203 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
204 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel
205 * IRQD_IRQ_STARTED - Startup state of the interrupt
206 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity
207 * mask. Applies only to affinity managed irqs.
208 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target
209 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set
210 * IRQD_CAN_RESERVE - Can use reservation mode
211 */
212 enum {
213 IRQD_TRIGGER_MASK = 0xf,
214 IRQD_SETAFFINITY_PENDING = (1 << 8),
215 IRQD_ACTIVATED = (1 << 9),
216 IRQD_NO_BALANCING = (1 << 10),
217 IRQD_PER_CPU = (1 << 11),
218 IRQD_AFFINITY_SET = (1 << 12),
219 IRQD_LEVEL = (1 << 13),
220 IRQD_WAKEUP_STATE = (1 << 14),
221 IRQD_MOVE_PCNTXT = (1 << 15),
222 IRQD_IRQ_DISABLED = (1 << 16),
223 IRQD_IRQ_MASKED = (1 << 17),
224 IRQD_IRQ_INPROGRESS = (1 << 18),
225 IRQD_WAKEUP_ARMED = (1 << 19),
226 IRQD_FORWARDED_TO_VCPU = (1 << 20),
227 IRQD_AFFINITY_MANAGED = (1 << 21),
228 IRQD_IRQ_STARTED = (1 << 22),
229 IRQD_MANAGED_SHUTDOWN = (1 << 23),
230 IRQD_SINGLE_TARGET = (1 << 24),
231 IRQD_DEFAULT_TRIGGER_SET = (1 << 25),
232 IRQD_CAN_RESERVE = (1 << 26),
233 };
234
235 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
236
irqd_is_setaffinity_pending(struct irq_data * d)237 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
238 {
239 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
240 }
241
irqd_is_per_cpu(struct irq_data * d)242 static inline bool irqd_is_per_cpu(struct irq_data *d)
243 {
244 return __irqd_to_state(d) & IRQD_PER_CPU;
245 }
246
irqd_can_balance(struct irq_data * d)247 static inline bool irqd_can_balance(struct irq_data *d)
248 {
249 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
250 }
251
irqd_affinity_was_set(struct irq_data * d)252 static inline bool irqd_affinity_was_set(struct irq_data *d)
253 {
254 return __irqd_to_state(d) & IRQD_AFFINITY_SET;
255 }
256
irqd_mark_affinity_was_set(struct irq_data * d)257 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
258 {
259 __irqd_to_state(d) |= IRQD_AFFINITY_SET;
260 }
261
irqd_trigger_type_was_set(struct irq_data * d)262 static inline bool irqd_trigger_type_was_set(struct irq_data *d)
263 {
264 return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET;
265 }
266
irqd_get_trigger_type(struct irq_data * d)267 static inline u32 irqd_get_trigger_type(struct irq_data *d)
268 {
269 return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
270 }
271
272 /*
273 * Must only be called inside irq_chip.irq_set_type() functions or
274 * from the DT/ACPI setup code.
275 */
irqd_set_trigger_type(struct irq_data * d,u32 type)276 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
277 {
278 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
279 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
280 __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET;
281 }
282
irqd_is_level_type(struct irq_data * d)283 static inline bool irqd_is_level_type(struct irq_data *d)
284 {
285 return __irqd_to_state(d) & IRQD_LEVEL;
286 }
287
288 /*
289 * Must only be called of irqchip.irq_set_affinity() or low level
290 * hieararchy domain allocation functions.
291 */
irqd_set_single_target(struct irq_data * d)292 static inline void irqd_set_single_target(struct irq_data *d)
293 {
294 __irqd_to_state(d) |= IRQD_SINGLE_TARGET;
295 }
296
irqd_is_single_target(struct irq_data * d)297 static inline bool irqd_is_single_target(struct irq_data *d)
298 {
299 return __irqd_to_state(d) & IRQD_SINGLE_TARGET;
300 }
301
irqd_is_wakeup_set(struct irq_data * d)302 static inline bool irqd_is_wakeup_set(struct irq_data *d)
303 {
304 return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
305 }
306
irqd_can_move_in_process_context(struct irq_data * d)307 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
308 {
309 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT;
310 }
311
irqd_irq_disabled(struct irq_data * d)312 static inline bool irqd_irq_disabled(struct irq_data *d)
313 {
314 return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
315 }
316
irqd_irq_masked(struct irq_data * d)317 static inline bool irqd_irq_masked(struct irq_data *d)
318 {
319 return __irqd_to_state(d) & IRQD_IRQ_MASKED;
320 }
321
irqd_irq_inprogress(struct irq_data * d)322 static inline bool irqd_irq_inprogress(struct irq_data *d)
323 {
324 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
325 }
326
irqd_is_wakeup_armed(struct irq_data * d)327 static inline bool irqd_is_wakeup_armed(struct irq_data *d)
328 {
329 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
330 }
331
irqd_is_forwarded_to_vcpu(struct irq_data * d)332 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d)
333 {
334 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU;
335 }
336
irqd_set_forwarded_to_vcpu(struct irq_data * d)337 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d)
338 {
339 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU;
340 }
341
irqd_clr_forwarded_to_vcpu(struct irq_data * d)342 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d)
343 {
344 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU;
345 }
346
irqd_affinity_is_managed(struct irq_data * d)347 static inline bool irqd_affinity_is_managed(struct irq_data *d)
348 {
349 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED;
350 }
351
irqd_is_activated(struct irq_data * d)352 static inline bool irqd_is_activated(struct irq_data *d)
353 {
354 return __irqd_to_state(d) & IRQD_ACTIVATED;
355 }
356
irqd_set_activated(struct irq_data * d)357 static inline void irqd_set_activated(struct irq_data *d)
358 {
359 __irqd_to_state(d) |= IRQD_ACTIVATED;
360 }
361
irqd_clr_activated(struct irq_data * d)362 static inline void irqd_clr_activated(struct irq_data *d)
363 {
364 __irqd_to_state(d) &= ~IRQD_ACTIVATED;
365 }
366
irqd_is_started(struct irq_data * d)367 static inline bool irqd_is_started(struct irq_data *d)
368 {
369 return __irqd_to_state(d) & IRQD_IRQ_STARTED;
370 }
371
irqd_is_managed_and_shutdown(struct irq_data * d)372 static inline bool irqd_is_managed_and_shutdown(struct irq_data *d)
373 {
374 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN;
375 }
376
irqd_set_can_reserve(struct irq_data * d)377 static inline void irqd_set_can_reserve(struct irq_data *d)
378 {
379 __irqd_to_state(d) |= IRQD_CAN_RESERVE;
380 }
381
irqd_clr_can_reserve(struct irq_data * d)382 static inline void irqd_clr_can_reserve(struct irq_data *d)
383 {
384 __irqd_to_state(d) &= ~IRQD_CAN_RESERVE;
385 }
386
irqd_can_reserve(struct irq_data * d)387 static inline bool irqd_can_reserve(struct irq_data *d)
388 {
389 return __irqd_to_state(d) & IRQD_CAN_RESERVE;
390 }
391
392 #undef __irqd_to_state
393
irqd_to_hwirq(struct irq_data * d)394 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
395 {
396 return d->hwirq;
397 }
398
399 /**
400 * struct irq_chip - hardware interrupt chip descriptor
401 *
402 * @parent_device: pointer to parent device for irqchip
403 * @name: name for /proc/interrupts
404 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
405 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
406 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
407 * @irq_disable: disable the interrupt
408 * @irq_ack: start of a new interrupt
409 * @irq_mask: mask an interrupt source
410 * @irq_mask_ack: ack and mask an interrupt source
411 * @irq_unmask: unmask an interrupt source
412 * @irq_eoi: end of interrupt
413 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force
414 * argument is true, it tells the driver to
415 * unconditionally apply the affinity setting. Sanity
416 * checks against the supplied affinity mask are not
417 * required. This is used for CPU hotplug where the
418 * target CPU is not yet set in the cpu_online_mask.
419 * @irq_retrigger: resend an IRQ to the CPU
420 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
421 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
422 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
423 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
424 * @irq_cpu_online: configure an interrupt source for a secondary CPU
425 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
426 * @irq_suspend: function called from core code on suspend once per
427 * chip, when one or more interrupts are installed
428 * @irq_resume: function called from core code on resume once per chip,
429 * when one ore more interrupts are installed
430 * @irq_pm_shutdown: function called from core code on shutdown once per chip
431 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
432 * @irq_print_chip: optional to print special chip info in show_interrupts
433 * @irq_request_resources: optional to request resources before calling
434 * any other callback related to this irq
435 * @irq_release_resources: optional to release resources acquired with
436 * irq_request_resources
437 * @irq_compose_msi_msg: optional to compose message content for MSI
438 * @irq_write_msi_msg: optional to write message content for MSI
439 * @irq_get_irqchip_state: return the internal state of an interrupt
440 * @irq_set_irqchip_state: set the internal state of a interrupt
441 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
442 * @ipi_send_single: send a single IPI to destination cpus
443 * @ipi_send_mask: send an IPI to destination cpus in cpumask
444 * @flags: chip specific flags
445 */
446 struct irq_chip {
447 struct device *parent_device;
448 const char *name;
449 unsigned int (*irq_startup)(struct irq_data *data);
450 void (*irq_shutdown)(struct irq_data *data);
451 void (*irq_enable)(struct irq_data *data);
452 void (*irq_disable)(struct irq_data *data);
453
454 void (*irq_ack)(struct irq_data *data);
455 void (*irq_mask)(struct irq_data *data);
456 void (*irq_mask_ack)(struct irq_data *data);
457 void (*irq_unmask)(struct irq_data *data);
458 void (*irq_eoi)(struct irq_data *data);
459
460 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
461 int (*irq_retrigger)(struct irq_data *data);
462 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
463 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
464
465 void (*irq_bus_lock)(struct irq_data *data);
466 void (*irq_bus_sync_unlock)(struct irq_data *data);
467
468 void (*irq_cpu_online)(struct irq_data *data);
469 void (*irq_cpu_offline)(struct irq_data *data);
470
471 void (*irq_suspend)(struct irq_data *data);
472 void (*irq_resume)(struct irq_data *data);
473 void (*irq_pm_shutdown)(struct irq_data *data);
474
475 void (*irq_calc_mask)(struct irq_data *data);
476
477 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
478 int (*irq_request_resources)(struct irq_data *data);
479 void (*irq_release_resources)(struct irq_data *data);
480
481 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
482 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
483
484 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
485 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
486
487 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
488
489 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu);
490 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest);
491
492 unsigned long flags;
493 };
494
495 /*
496 * irq_chip specific flags
497 *
498 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
499 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
500 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
501 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
502 * when irq enabled
503 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
504 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
505 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
506 * IRQCHIP_SUPPORTS_LEVEL_MSI Chip can provide two doorbells for Level MSIs
507 */
508 enum {
509 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
510 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
511 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
512 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
513 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
514 IRQCHIP_ONESHOT_SAFE = (1 << 5),
515 IRQCHIP_EOI_THREADED = (1 << 6),
516 IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7),
517 };
518
519 #include <linux/irqdesc.h>
520
521 /*
522 * Pick up the arch-dependent methods:
523 */
524 #include <asm/hw_irq.h>
525
526 #ifndef NR_IRQS_LEGACY
527 # define NR_IRQS_LEGACY 0
528 #endif
529
530 #ifndef ARCH_IRQ_INIT_FLAGS
531 # define ARCH_IRQ_INIT_FLAGS 0
532 #endif
533
534 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
535
536 struct irqaction;
537 extern int setup_irq(unsigned int irq, struct irqaction *new);
538 extern void remove_irq(unsigned int irq, struct irqaction *act);
539 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
540 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
541
542 extern void irq_cpu_online(void);
543 extern void irq_cpu_offline(void);
544 extern int irq_set_affinity_locked(struct irq_data *data,
545 const struct cpumask *cpumask, bool force);
546 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
547
548 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION)
549 extern void irq_migrate_all_off_this_cpu(void);
550 extern int irq_affinity_online_cpu(unsigned int cpu);
551 #else
552 # define irq_affinity_online_cpu NULL
553 #endif
554
555 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
556 void __irq_move_irq(struct irq_data *data);
irq_move_irq(struct irq_data * data)557 static inline void irq_move_irq(struct irq_data *data)
558 {
559 if (unlikely(irqd_is_setaffinity_pending(data)))
560 __irq_move_irq(data);
561 }
562 void irq_move_masked_irq(struct irq_data *data);
563 void irq_force_complete_move(struct irq_desc *desc);
564 #else
irq_move_irq(struct irq_data * data)565 static inline void irq_move_irq(struct irq_data *data) { }
irq_move_masked_irq(struct irq_data * data)566 static inline void irq_move_masked_irq(struct irq_data *data) { }
irq_force_complete_move(struct irq_desc * desc)567 static inline void irq_force_complete_move(struct irq_desc *desc) { }
568 #endif
569
570 extern int no_irq_affinity;
571
572 #ifdef CONFIG_HARDIRQS_SW_RESEND
573 int irq_set_parent(int irq, int parent_irq);
574 #else
irq_set_parent(int irq,int parent_irq)575 static inline int irq_set_parent(int irq, int parent_irq)
576 {
577 return 0;
578 }
579 #endif
580
581 /*
582 * Built-in IRQ handlers for various IRQ types,
583 * callable via desc->handle_irq()
584 */
585 extern void handle_level_irq(struct irq_desc *desc);
586 extern void handle_fasteoi_irq(struct irq_desc *desc);
587 extern void handle_edge_irq(struct irq_desc *desc);
588 extern void handle_edge_eoi_irq(struct irq_desc *desc);
589 extern void handle_simple_irq(struct irq_desc *desc);
590 extern void handle_untracked_irq(struct irq_desc *desc);
591 extern void handle_percpu_irq(struct irq_desc *desc);
592 extern void handle_percpu_devid_irq(struct irq_desc *desc);
593 extern void handle_bad_irq(struct irq_desc *desc);
594 extern void handle_nested_irq(unsigned int irq);
595
596 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
597 extern int irq_chip_pm_get(struct irq_data *data);
598 extern int irq_chip_pm_put(struct irq_data *data);
599 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
600 extern void handle_fasteoi_ack_irq(struct irq_desc *desc);
601 extern void handle_fasteoi_mask_irq(struct irq_desc *desc);
602 extern void irq_chip_enable_parent(struct irq_data *data);
603 extern void irq_chip_disable_parent(struct irq_data *data);
604 extern void irq_chip_ack_parent(struct irq_data *data);
605 extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
606 extern void irq_chip_mask_parent(struct irq_data *data);
607 extern void irq_chip_unmask_parent(struct irq_data *data);
608 extern void irq_chip_eoi_parent(struct irq_data *data);
609 extern int irq_chip_set_affinity_parent(struct irq_data *data,
610 const struct cpumask *dest,
611 bool force);
612 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
613 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
614 void *vcpu_info);
615 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
616 #endif
617
618 /* Handling of unhandled and spurious interrupts: */
619 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret);
620
621
622 /* Enable/disable irq debugging output: */
623 extern int noirqdebug_setup(char *str);
624
625 /* Checks whether the interrupt can be requested by request_irq(): */
626 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
627
628 /* Dummy irq-chip implementations: */
629 extern struct irq_chip no_irq_chip;
630 extern struct irq_chip dummy_irq_chip;
631
632 extern void
633 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
634 irq_flow_handler_t handle, const char *name);
635
irq_set_chip_and_handler(unsigned int irq,struct irq_chip * chip,irq_flow_handler_t handle)636 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
637 irq_flow_handler_t handle)
638 {
639 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
640 }
641
642 extern int irq_set_percpu_devid(unsigned int irq);
643 extern int irq_set_percpu_devid_partition(unsigned int irq,
644 const struct cpumask *affinity);
645 extern int irq_get_percpu_devid_partition(unsigned int irq,
646 struct cpumask *affinity);
647
648 extern void
649 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
650 const char *name);
651
652 static inline void
irq_set_handler(unsigned int irq,irq_flow_handler_t handle)653 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
654 {
655 __irq_set_handler(irq, handle, 0, NULL);
656 }
657
658 /*
659 * Set a highlevel chained flow handler for a given IRQ.
660 * (a chained handler is automatically enabled and set to
661 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
662 */
663 static inline void
irq_set_chained_handler(unsigned int irq,irq_flow_handler_t handle)664 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
665 {
666 __irq_set_handler(irq, handle, 1, NULL);
667 }
668
669 /*
670 * Set a highlevel chained flow handler and its data for a given IRQ.
671 * (a chained handler is automatically enabled and set to
672 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
673 */
674 void
675 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
676 void *data);
677
678 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
679
irq_set_status_flags(unsigned int irq,unsigned long set)680 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
681 {
682 irq_modify_status(irq, 0, set);
683 }
684
irq_clear_status_flags(unsigned int irq,unsigned long clr)685 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
686 {
687 irq_modify_status(irq, clr, 0);
688 }
689
irq_set_noprobe(unsigned int irq)690 static inline void irq_set_noprobe(unsigned int irq)
691 {
692 irq_modify_status(irq, 0, IRQ_NOPROBE);
693 }
694
irq_set_probe(unsigned int irq)695 static inline void irq_set_probe(unsigned int irq)
696 {
697 irq_modify_status(irq, IRQ_NOPROBE, 0);
698 }
699
irq_set_nothread(unsigned int irq)700 static inline void irq_set_nothread(unsigned int irq)
701 {
702 irq_modify_status(irq, 0, IRQ_NOTHREAD);
703 }
704
irq_set_thread(unsigned int irq)705 static inline void irq_set_thread(unsigned int irq)
706 {
707 irq_modify_status(irq, IRQ_NOTHREAD, 0);
708 }
709
irq_set_nested_thread(unsigned int irq,bool nest)710 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
711 {
712 if (nest)
713 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
714 else
715 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
716 }
717
irq_set_percpu_devid_flags(unsigned int irq)718 static inline void irq_set_percpu_devid_flags(unsigned int irq)
719 {
720 irq_set_status_flags(irq,
721 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
722 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
723 }
724
725 /* Set/get chip/data for an IRQ: */
726 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
727 extern int irq_set_handler_data(unsigned int irq, void *data);
728 extern int irq_set_chip_data(unsigned int irq, void *data);
729 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
730 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
731 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
732 struct msi_desc *entry);
733 extern struct irq_data *irq_get_irq_data(unsigned int irq);
734
irq_get_chip(unsigned int irq)735 static inline struct irq_chip *irq_get_chip(unsigned int irq)
736 {
737 struct irq_data *d = irq_get_irq_data(irq);
738 return d ? d->chip : NULL;
739 }
740
irq_data_get_irq_chip(struct irq_data * d)741 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
742 {
743 return d->chip;
744 }
745
irq_get_chip_data(unsigned int irq)746 static inline void *irq_get_chip_data(unsigned int irq)
747 {
748 struct irq_data *d = irq_get_irq_data(irq);
749 return d ? d->chip_data : NULL;
750 }
751
irq_data_get_irq_chip_data(struct irq_data * d)752 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
753 {
754 return d->chip_data;
755 }
756
irq_get_handler_data(unsigned int irq)757 static inline void *irq_get_handler_data(unsigned int irq)
758 {
759 struct irq_data *d = irq_get_irq_data(irq);
760 return d ? d->common->handler_data : NULL;
761 }
762
irq_data_get_irq_handler_data(struct irq_data * d)763 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
764 {
765 return d->common->handler_data;
766 }
767
irq_get_msi_desc(unsigned int irq)768 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
769 {
770 struct irq_data *d = irq_get_irq_data(irq);
771 return d ? d->common->msi_desc : NULL;
772 }
773
irq_data_get_msi_desc(struct irq_data * d)774 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d)
775 {
776 return d->common->msi_desc;
777 }
778
irq_get_trigger_type(unsigned int irq)779 static inline u32 irq_get_trigger_type(unsigned int irq)
780 {
781 struct irq_data *d = irq_get_irq_data(irq);
782 return d ? irqd_get_trigger_type(d) : 0;
783 }
784
irq_common_data_get_node(struct irq_common_data * d)785 static inline int irq_common_data_get_node(struct irq_common_data *d)
786 {
787 #ifdef CONFIG_NUMA
788 return d->node;
789 #else
790 return 0;
791 #endif
792 }
793
irq_data_get_node(struct irq_data * d)794 static inline int irq_data_get_node(struct irq_data *d)
795 {
796 return irq_common_data_get_node(d->common);
797 }
798
irq_get_affinity_mask(int irq)799 static inline struct cpumask *irq_get_affinity_mask(int irq)
800 {
801 struct irq_data *d = irq_get_irq_data(irq);
802
803 return d ? d->common->affinity : NULL;
804 }
805
irq_data_get_affinity_mask(struct irq_data * d)806 static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
807 {
808 return d->common->affinity;
809 }
810
811 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
812 static inline
irq_data_get_effective_affinity_mask(struct irq_data * d)813 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
814 {
815 return d->common->effective_affinity;
816 }
irq_data_update_effective_affinity(struct irq_data * d,const struct cpumask * m)817 static inline void irq_data_update_effective_affinity(struct irq_data *d,
818 const struct cpumask *m)
819 {
820 cpumask_copy(d->common->effective_affinity, m);
821 }
822 #else
irq_data_update_effective_affinity(struct irq_data * d,const struct cpumask * m)823 static inline void irq_data_update_effective_affinity(struct irq_data *d,
824 const struct cpumask *m)
825 {
826 }
827 static inline
irq_data_get_effective_affinity_mask(struct irq_data * d)828 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
829 {
830 return d->common->affinity;
831 }
832 #endif
833
834 unsigned int arch_dynirq_lower_bound(unsigned int from);
835
836 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
837 struct module *owner, const struct cpumask *affinity);
838
839 int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from,
840 unsigned int cnt, int node, struct module *owner,
841 const struct cpumask *affinity);
842
843 /* use macros to avoid needing export.h for THIS_MODULE */
844 #define irq_alloc_descs(irq, from, cnt, node) \
845 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
846
847 #define irq_alloc_desc(node) \
848 irq_alloc_descs(-1, 0, 1, node)
849
850 #define irq_alloc_desc_at(at, node) \
851 irq_alloc_descs(at, at, 1, node)
852
853 #define irq_alloc_desc_from(from, node) \
854 irq_alloc_descs(-1, from, 1, node)
855
856 #define irq_alloc_descs_from(from, cnt, node) \
857 irq_alloc_descs(-1, from, cnt, node)
858
859 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \
860 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
861
862 #define devm_irq_alloc_desc(dev, node) \
863 devm_irq_alloc_descs(dev, -1, 0, 1, node)
864
865 #define devm_irq_alloc_desc_at(dev, at, node) \
866 devm_irq_alloc_descs(dev, at, at, 1, node)
867
868 #define devm_irq_alloc_desc_from(dev, from, node) \
869 devm_irq_alloc_descs(dev, -1, from, 1, node)
870
871 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \
872 devm_irq_alloc_descs(dev, -1, from, cnt, node)
873
874 void irq_free_descs(unsigned int irq, unsigned int cnt);
irq_free_desc(unsigned int irq)875 static inline void irq_free_desc(unsigned int irq)
876 {
877 irq_free_descs(irq, 1);
878 }
879
880 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
881 unsigned int irq_alloc_hwirqs(int cnt, int node);
irq_alloc_hwirq(int node)882 static inline unsigned int irq_alloc_hwirq(int node)
883 {
884 return irq_alloc_hwirqs(1, node);
885 }
886 void irq_free_hwirqs(unsigned int from, int cnt);
irq_free_hwirq(unsigned int irq)887 static inline void irq_free_hwirq(unsigned int irq)
888 {
889 return irq_free_hwirqs(irq, 1);
890 }
891 int arch_setup_hwirq(unsigned int irq, int node);
892 void arch_teardown_hwirq(unsigned int irq);
893 #endif
894
895 #ifdef CONFIG_GENERIC_IRQ_LEGACY
896 void irq_init_desc(unsigned int irq);
897 #endif
898
899 /**
900 * struct irq_chip_regs - register offsets for struct irq_gci
901 * @enable: Enable register offset to reg_base
902 * @disable: Disable register offset to reg_base
903 * @mask: Mask register offset to reg_base
904 * @ack: Ack register offset to reg_base
905 * @eoi: Eoi register offset to reg_base
906 * @type: Type configuration register offset to reg_base
907 * @polarity: Polarity configuration register offset to reg_base
908 */
909 struct irq_chip_regs {
910 unsigned long enable;
911 unsigned long disable;
912 unsigned long mask;
913 unsigned long ack;
914 unsigned long eoi;
915 unsigned long type;
916 unsigned long polarity;
917 };
918
919 /**
920 * struct irq_chip_type - Generic interrupt chip instance for a flow type
921 * @chip: The real interrupt chip which provides the callbacks
922 * @regs: Register offsets for this chip
923 * @handler: Flow handler associated with this chip
924 * @type: Chip can handle these flow types
925 * @mask_cache_priv: Cached mask register private to the chip type
926 * @mask_cache: Pointer to cached mask register
927 *
928 * A irq_generic_chip can have several instances of irq_chip_type when
929 * it requires different functions and register offsets for different
930 * flow types.
931 */
932 struct irq_chip_type {
933 struct irq_chip chip;
934 struct irq_chip_regs regs;
935 irq_flow_handler_t handler;
936 u32 type;
937 u32 mask_cache_priv;
938 u32 *mask_cache;
939 };
940
941 /**
942 * struct irq_chip_generic - Generic irq chip data structure
943 * @lock: Lock to protect register and cache data access
944 * @reg_base: Register base address (virtual)
945 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
946 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
947 * @suspend: Function called from core code on suspend once per
948 * chip; can be useful instead of irq_chip::suspend to
949 * handle chip details even when no interrupts are in use
950 * @resume: Function called from core code on resume once per chip;
951 * can be useful instead of irq_chip::suspend to handle
952 * chip details even when no interrupts are in use
953 * @irq_base: Interrupt base nr for this chip
954 * @irq_cnt: Number of interrupts handled by this chip
955 * @mask_cache: Cached mask register shared between all chip types
956 * @type_cache: Cached type register
957 * @polarity_cache: Cached polarity register
958 * @wake_enabled: Interrupt can wakeup from suspend
959 * @wake_active: Interrupt is marked as an wakeup from suspend source
960 * @num_ct: Number of available irq_chip_type instances (usually 1)
961 * @private: Private data for non generic chip callbacks
962 * @installed: bitfield to denote installed interrupts
963 * @unused: bitfield to denote unused interrupts
964 * @domain: irq domain pointer
965 * @list: List head for keeping track of instances
966 * @chip_types: Array of interrupt irq_chip_types
967 *
968 * Note, that irq_chip_generic can have multiple irq_chip_type
969 * implementations which can be associated to a particular irq line of
970 * an irq_chip_generic instance. That allows to share and protect
971 * state in an irq_chip_generic instance when we need to implement
972 * different flow mechanisms (level/edge) for it.
973 */
974 struct irq_chip_generic {
975 raw_spinlock_t lock;
976 void __iomem *reg_base;
977 u32 (*reg_readl)(void __iomem *addr);
978 void (*reg_writel)(u32 val, void __iomem *addr);
979 void (*suspend)(struct irq_chip_generic *gc);
980 void (*resume)(struct irq_chip_generic *gc);
981 unsigned int irq_base;
982 unsigned int irq_cnt;
983 u32 mask_cache;
984 u32 type_cache;
985 u32 polarity_cache;
986 u32 wake_enabled;
987 u32 wake_active;
988 unsigned int num_ct;
989 void *private;
990 unsigned long installed;
991 unsigned long unused;
992 struct irq_domain *domain;
993 struct list_head list;
994 struct irq_chip_type chip_types[0];
995 };
996
997 /**
998 * enum irq_gc_flags - Initialization flags for generic irq chips
999 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
1000 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
1001 * irq chips which need to call irq_set_wake() on
1002 * the parent irq. Usually GPIO implementations
1003 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
1004 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
1005 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
1006 */
1007 enum irq_gc_flags {
1008 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
1009 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
1010 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
1011 IRQ_GC_NO_MASK = 1 << 3,
1012 IRQ_GC_BE_IO = 1 << 4,
1013 };
1014
1015 /*
1016 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
1017 * @irqs_per_chip: Number of interrupts per chip
1018 * @num_chips: Number of chips
1019 * @irq_flags_to_set: IRQ* flags to set on irq setup
1020 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
1021 * @gc_flags: Generic chip specific setup flags
1022 * @gc: Array of pointers to generic interrupt chips
1023 */
1024 struct irq_domain_chip_generic {
1025 unsigned int irqs_per_chip;
1026 unsigned int num_chips;
1027 unsigned int irq_flags_to_clear;
1028 unsigned int irq_flags_to_set;
1029 enum irq_gc_flags gc_flags;
1030 struct irq_chip_generic *gc[0];
1031 };
1032
1033 /* Generic chip callback functions */
1034 void irq_gc_noop(struct irq_data *d);
1035 void irq_gc_mask_disable_reg(struct irq_data *d);
1036 void irq_gc_mask_set_bit(struct irq_data *d);
1037 void irq_gc_mask_clr_bit(struct irq_data *d);
1038 void irq_gc_unmask_enable_reg(struct irq_data *d);
1039 void irq_gc_ack_set_bit(struct irq_data *d);
1040 void irq_gc_ack_clr_bit(struct irq_data *d);
1041 void irq_gc_mask_disable_and_ack_set(struct irq_data *d);
1042 void irq_gc_eoi(struct irq_data *d);
1043 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
1044
1045 /* Setup functions for irq_chip_generic */
1046 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
1047 irq_hw_number_t hw_irq);
1048 struct irq_chip_generic *
1049 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
1050 void __iomem *reg_base, irq_flow_handler_t handler);
1051 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
1052 enum irq_gc_flags flags, unsigned int clr,
1053 unsigned int set);
1054 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
1055 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
1056 unsigned int clr, unsigned int set);
1057
1058 struct irq_chip_generic *
1059 devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct,
1060 unsigned int irq_base, void __iomem *reg_base,
1061 irq_flow_handler_t handler);
1062 int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc,
1063 u32 msk, enum irq_gc_flags flags,
1064 unsigned int clr, unsigned int set);
1065
1066 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
1067
1068 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
1069 int num_ct, const char *name,
1070 irq_flow_handler_t handler,
1071 unsigned int clr, unsigned int set,
1072 enum irq_gc_flags flags);
1073
1074 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \
1075 handler, clr, set, flags) \
1076 ({ \
1077 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \
1078 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\
1079 handler, clr, set, flags); \
1080 })
1081
irq_free_generic_chip(struct irq_chip_generic * gc)1082 static inline void irq_free_generic_chip(struct irq_chip_generic *gc)
1083 {
1084 kfree(gc);
1085 }
1086
irq_destroy_generic_chip(struct irq_chip_generic * gc,u32 msk,unsigned int clr,unsigned int set)1087 static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc,
1088 u32 msk, unsigned int clr,
1089 unsigned int set)
1090 {
1091 irq_remove_generic_chip(gc, msk, clr, set);
1092 irq_free_generic_chip(gc);
1093 }
1094
irq_data_get_chip_type(struct irq_data * d)1095 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
1096 {
1097 return container_of(d->chip, struct irq_chip_type, chip);
1098 }
1099
1100 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1101
1102 #ifdef CONFIG_SMP
irq_gc_lock(struct irq_chip_generic * gc)1103 static inline void irq_gc_lock(struct irq_chip_generic *gc)
1104 {
1105 raw_spin_lock(&gc->lock);
1106 }
1107
irq_gc_unlock(struct irq_chip_generic * gc)1108 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
1109 {
1110 raw_spin_unlock(&gc->lock);
1111 }
1112 #else
irq_gc_lock(struct irq_chip_generic * gc)1113 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
irq_gc_unlock(struct irq_chip_generic * gc)1114 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
1115 #endif
1116
1117 /*
1118 * The irqsave variants are for usage in non interrupt code. Do not use
1119 * them in irq_chip callbacks. Use irq_gc_lock() instead.
1120 */
1121 #define irq_gc_lock_irqsave(gc, flags) \
1122 raw_spin_lock_irqsave(&(gc)->lock, flags)
1123
1124 #define irq_gc_unlock_irqrestore(gc, flags) \
1125 raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1126
irq_reg_writel(struct irq_chip_generic * gc,u32 val,int reg_offset)1127 static inline void irq_reg_writel(struct irq_chip_generic *gc,
1128 u32 val, int reg_offset)
1129 {
1130 if (gc->reg_writel)
1131 gc->reg_writel(val, gc->reg_base + reg_offset);
1132 else
1133 writel(val, gc->reg_base + reg_offset);
1134 }
1135
irq_reg_readl(struct irq_chip_generic * gc,int reg_offset)1136 static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
1137 int reg_offset)
1138 {
1139 if (gc->reg_readl)
1140 return gc->reg_readl(gc->reg_base + reg_offset);
1141 else
1142 return readl(gc->reg_base + reg_offset);
1143 }
1144
1145 struct irq_matrix;
1146 struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits,
1147 unsigned int alloc_start,
1148 unsigned int alloc_end);
1149 void irq_matrix_online(struct irq_matrix *m);
1150 void irq_matrix_offline(struct irq_matrix *m);
1151 void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace);
1152 int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk);
1153 void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk);
1154 int irq_matrix_alloc_managed(struct irq_matrix *m, unsigned int cpu);
1155 void irq_matrix_reserve(struct irq_matrix *m);
1156 void irq_matrix_remove_reserved(struct irq_matrix *m);
1157 int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk,
1158 bool reserved, unsigned int *mapped_cpu);
1159 void irq_matrix_free(struct irq_matrix *m, unsigned int cpu,
1160 unsigned int bit, bool managed);
1161 void irq_matrix_assign(struct irq_matrix *m, unsigned int bit);
1162 unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown);
1163 unsigned int irq_matrix_allocated(struct irq_matrix *m);
1164 unsigned int irq_matrix_reserved(struct irq_matrix *m);
1165 void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind);
1166
1167 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */
1168 #define INVALID_HWIRQ (~0UL)
1169 irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu);
1170 int __ipi_send_single(struct irq_desc *desc, unsigned int cpu);
1171 int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest);
1172 int ipi_send_single(unsigned int virq, unsigned int cpu);
1173 int ipi_send_mask(unsigned int virq, const struct cpumask *dest);
1174
1175 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
1176 /*
1177 * Registers a generic IRQ handling function as the top-level IRQ handler in
1178 * the system, which is generally the first C code called from an assembly
1179 * architecture-specific interrupt handler.
1180 *
1181 * Returns 0 on success, or -EBUSY if an IRQ handler has already been
1182 * registered.
1183 */
1184 int __init set_handle_irq(void (*handle_irq)(struct pt_regs *));
1185
1186 /*
1187 * Allows interrupt handlers to find the irqchip that's been registered as the
1188 * top-level IRQ handler.
1189 */
1190 extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init;
1191 #endif
1192
1193 #endif /* _LINUX_IRQ_H */
1194
