1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77965 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * Copyright (C) 2016 Renesas Electronics Corp.
7 *
8 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
14
15 #include <linux/kernel.h>
16
17 #include "core.h"
18 #include "sh_pfc.h"
19
20 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
21 SH_PFC_PIN_CFG_PULL_UP | \
22 SH_PFC_PIN_CFG_PULL_DOWN)
23
24 #define CPU_ALL_PORT(fn, sfx) \
25 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
29 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
34 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
37 /*
38 * F_() : just information
39 * FM() : macro for FN_xxx / xxx_MARK
40 */
41
42 /* GPSR0 */
43 #define GPSR0_15 F_(D15, IP7_11_8)
44 #define GPSR0_14 F_(D14, IP7_7_4)
45 #define GPSR0_13 F_(D13, IP7_3_0)
46 #define GPSR0_12 F_(D12, IP6_31_28)
47 #define GPSR0_11 F_(D11, IP6_27_24)
48 #define GPSR0_10 F_(D10, IP6_23_20)
49 #define GPSR0_9 F_(D9, IP6_19_16)
50 #define GPSR0_8 F_(D8, IP6_15_12)
51 #define GPSR0_7 F_(D7, IP6_11_8)
52 #define GPSR0_6 F_(D6, IP6_7_4)
53 #define GPSR0_5 F_(D5, IP6_3_0)
54 #define GPSR0_4 F_(D4, IP5_31_28)
55 #define GPSR0_3 F_(D3, IP5_27_24)
56 #define GPSR0_2 F_(D2, IP5_23_20)
57 #define GPSR0_1 F_(D1, IP5_19_16)
58 #define GPSR0_0 F_(D0, IP5_15_12)
59
60 /* GPSR1 */
61 #define GPSR1_28 FM(CLKOUT)
62 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
63 #define GPSR1_26 F_(WE1_N, IP5_7_4)
64 #define GPSR1_25 F_(WE0_N, IP5_3_0)
65 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
66 #define GPSR1_23 F_(RD_N, IP4_27_24)
67 #define GPSR1_22 F_(BS_N, IP4_23_20)
68 #define GPSR1_21 F_(CS1_N, IP4_19_16)
69 #define GPSR1_20 F_(CS0_N, IP4_15_12)
70 #define GPSR1_19 F_(A19, IP4_11_8)
71 #define GPSR1_18 F_(A18, IP4_7_4)
72 #define GPSR1_17 F_(A17, IP4_3_0)
73 #define GPSR1_16 F_(A16, IP3_31_28)
74 #define GPSR1_15 F_(A15, IP3_27_24)
75 #define GPSR1_14 F_(A14, IP3_23_20)
76 #define GPSR1_13 F_(A13, IP3_19_16)
77 #define GPSR1_12 F_(A12, IP3_15_12)
78 #define GPSR1_11 F_(A11, IP3_11_8)
79 #define GPSR1_10 F_(A10, IP3_7_4)
80 #define GPSR1_9 F_(A9, IP3_3_0)
81 #define GPSR1_8 F_(A8, IP2_31_28)
82 #define GPSR1_7 F_(A7, IP2_27_24)
83 #define GPSR1_6 F_(A6, IP2_23_20)
84 #define GPSR1_5 F_(A5, IP2_19_16)
85 #define GPSR1_4 F_(A4, IP2_15_12)
86 #define GPSR1_3 F_(A3, IP2_11_8)
87 #define GPSR1_2 F_(A2, IP2_7_4)
88 #define GPSR1_1 F_(A1, IP2_3_0)
89 #define GPSR1_0 F_(A0, IP1_31_28)
90
91 /* GPSR2 */
92 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
93 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
94 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
95 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
96 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
97 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
98 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
99 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
100 #define GPSR2_6 F_(PWM0, IP1_19_16)
101 #define GPSR2_5 F_(IRQ5, IP1_15_12)
102 #define GPSR2_4 F_(IRQ4, IP1_11_8)
103 #define GPSR2_3 F_(IRQ3, IP1_7_4)
104 #define GPSR2_2 F_(IRQ2, IP1_3_0)
105 #define GPSR2_1 F_(IRQ1, IP0_31_28)
106 #define GPSR2_0 F_(IRQ0, IP0_27_24)
107
108 /* GPSR3 */
109 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
110 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
111 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
112 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
113 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
114 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
115 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
116 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
117 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
118 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
119 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
120 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
121 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
122 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
123 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
124 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
125
126 /* GPSR4 */
127 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
128 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
129 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
130 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
131 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
132 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
133 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
134 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
135 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
136 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
137 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
138 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
139 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
140 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
141 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
142 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
143 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
144 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
145
146 /* GPSR5 */
147 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
148 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
149 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
150 #define GPSR5_22 FM(MSIOF0_RXD)
151 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
152 #define GPSR5_20 FM(MSIOF0_TXD)
153 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
154 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
155 #define GPSR5_17 FM(MSIOF0_SCK)
156 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
157 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
158 #define GPSR5_14 F_(HTX0, IP13_19_16)
159 #define GPSR5_13 F_(HRX0, IP13_15_12)
160 #define GPSR5_12 F_(HSCK0, IP13_11_8)
161 #define GPSR5_11 F_(RX2_A, IP13_7_4)
162 #define GPSR5_10 F_(TX2_A, IP13_3_0)
163 #define GPSR5_9 F_(SCK2, IP12_31_28)
164 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
165 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
166 #define GPSR5_6 F_(TX1_A, IP12_19_16)
167 #define GPSR5_5 F_(RX1_A, IP12_15_12)
168 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
169 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
170 #define GPSR5_2 F_(TX0, IP12_3_0)
171 #define GPSR5_1 F_(RX0, IP11_31_28)
172 #define GPSR5_0 F_(SCK0, IP11_27_24)
173
174 /* GPSR6 */
175 #define GPSR6_31 F_(GP6_31, IP18_7_4)
176 #define GPSR6_30 F_(GP6_30, IP18_3_0)
177 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
178 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
179 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
180 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
181 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
182 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
183 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
184 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
185 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
186 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
187 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
188 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
189 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
190 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
191 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
192 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
193 #define GPSR6_13 FM(SSI_SDATA5)
194 #define GPSR6_12 FM(SSI_WS5)
195 #define GPSR6_11 FM(SSI_SCK5)
196 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
197 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
198 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
199 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
200 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
201 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
202 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
203 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
204 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
205 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
206 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
207
208 /* GPSR7 */
209 #define GPSR7_3 FM(GP7_03)
210 #define GPSR7_2 FM(HDMI0_CEC)
211 #define GPSR7_1 FM(AVS2)
212 #define GPSR7_0 FM(AVS1)
213
214
215 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
216 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243
244 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
245 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274
275 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310
311 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
312 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
333 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340
341 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
342 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
362 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
363 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
364 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
365 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
366 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
368 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
369
370 #define PINMUX_GPSR \
371 \
372 GPSR6_31 \
373 GPSR6_30 \
374 GPSR6_29 \
375 GPSR1_28 GPSR6_28 \
376 GPSR1_27 GPSR6_27 \
377 GPSR1_26 GPSR6_26 \
378 GPSR1_25 GPSR5_25 GPSR6_25 \
379 GPSR1_24 GPSR5_24 GPSR6_24 \
380 GPSR1_23 GPSR5_23 GPSR6_23 \
381 GPSR1_22 GPSR5_22 GPSR6_22 \
382 GPSR1_21 GPSR5_21 GPSR6_21 \
383 GPSR1_20 GPSR5_20 GPSR6_20 \
384 GPSR1_19 GPSR5_19 GPSR6_19 \
385 GPSR1_18 GPSR5_18 GPSR6_18 \
386 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
387 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
388 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
389 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
390 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
391 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
392 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
393 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
394 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
395 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
396 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
397 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
398 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
399 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
400 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
401 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
402 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
403 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
404
405 #define PINMUX_IPSR \
406 \
407 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
408 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
409 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
410 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
411 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
412 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
413 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
414 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
415 \
416 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
417 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
418 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
419 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
420 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
421 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
422 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
423 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
424 \
425 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
426 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
427 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
428 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
429 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
430 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
431 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
432 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
433 \
434 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
435 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
436 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
437 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
438 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
439 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
440 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
441 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
442 \
443 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
444 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
445 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
446 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
447 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
448 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
449 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
450 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
451
452 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
453 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
454 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
455 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
456 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
457 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
458 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
459 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
460 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
461 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
462 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
463 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
464 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
465 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
466 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
467 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
468 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
469 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
470 #define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
471
472 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
473 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
474 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
475 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
476 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
477 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
478 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
479 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
480 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
481 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
482 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
483 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
484 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
485 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
486 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
487 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
488 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
489 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
490 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
491 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
492 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
493 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
494 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
495
496 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
497 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
498 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
499 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
500 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
501 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
502 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
503 #define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
504 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
505 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
506 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
507 #define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
508 #define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
509 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
510
511 #define PINMUX_MOD_SELS \
512 \
513 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
514 MOD_SEL2_30 \
515 MOD_SEL1_29_28_27 MOD_SEL2_29 \
516 MOD_SEL0_28_27 MOD_SEL2_28_27 \
517 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
518 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
519 MOD_SEL0_23 MOD_SEL1_23_22_21 \
520 MOD_SEL0_22 MOD_SEL2_22 \
521 MOD_SEL0_21 MOD_SEL2_21 \
522 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
523 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
524 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
525 MOD_SEL2_17 \
526 MOD_SEL0_16 MOD_SEL1_16 \
527 MOD_SEL1_15_14 \
528 MOD_SEL0_14_13 \
529 MOD_SEL1_13 \
530 MOD_SEL0_12 MOD_SEL1_12 \
531 MOD_SEL0_11 MOD_SEL1_11 \
532 MOD_SEL0_10 MOD_SEL1_10 \
533 MOD_SEL0_9_8 MOD_SEL1_9 \
534 MOD_SEL0_7_6 \
535 MOD_SEL1_6 \
536 MOD_SEL0_5 MOD_SEL1_5 \
537 MOD_SEL0_4_3 MOD_SEL1_4 \
538 MOD_SEL1_3 \
539 MOD_SEL1_2 \
540 MOD_SEL1_1 \
541 MOD_SEL1_0 MOD_SEL2_0
542
543 /*
544 * These pins are not able to be muxed but have other properties
545 * that can be set, such as drive-strength or pull-up/pull-down enable.
546 */
547 #define PINMUX_STATIC \
548 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
549 FM(QSPI0_IO2) FM(QSPI0_IO3) \
550 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
551 FM(QSPI1_IO2) FM(QSPI1_IO3) \
552 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
553 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
554 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
555 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
556 FM(PRESETOUT) \
557 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
558 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
559
560 enum {
561 PINMUX_RESERVED = 0,
562
563 PINMUX_DATA_BEGIN,
564 GP_ALL(DATA),
565 PINMUX_DATA_END,
566
567 #define F_(x, y)
568 #define FM(x) FN_##x,
569 PINMUX_FUNCTION_BEGIN,
570 GP_ALL(FN),
571 PINMUX_GPSR
572 PINMUX_IPSR
573 PINMUX_MOD_SELS
574 PINMUX_FUNCTION_END,
575 #undef F_
576 #undef FM
577
578 #define F_(x, y)
579 #define FM(x) x##_MARK,
580 PINMUX_MARK_BEGIN,
581 PINMUX_GPSR
582 PINMUX_IPSR
583 PINMUX_MOD_SELS
584 PINMUX_STATIC
585 PINMUX_MARK_END,
586 #undef F_
587 #undef FM
588 };
589
590 static const u16 pinmux_data[] = {
591 PINMUX_DATA_GP_ALL(),
592
593 PINMUX_SINGLE(AVS1),
594 PINMUX_SINGLE(AVS2),
595 PINMUX_SINGLE(CLKOUT),
596 PINMUX_SINGLE(GP7_03),
597 PINMUX_SINGLE(HDMI0_CEC),
598 PINMUX_SINGLE(MSIOF0_RXD),
599 PINMUX_SINGLE(MSIOF0_SCK),
600 PINMUX_SINGLE(MSIOF0_TXD),
601 PINMUX_SINGLE(SSI_SCK5),
602 PINMUX_SINGLE(SSI_SDATA5),
603 PINMUX_SINGLE(SSI_WS5),
604
605 /* IPSR0 */
606 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
607 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
608
609 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
610 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
611 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
612
613 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
614 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
615 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
616
617 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
618 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
619 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
620 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
621
622 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
623 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
624 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
625
626 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
627 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
628 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
629
630 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
631 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
632 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
633 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
634 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
635 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
636 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
637
638 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
639 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
640 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
641 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
642 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
643 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
644 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
645
646 /* IPSR1 */
647 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
648 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
649 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
650 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
651 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
652 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
653
654 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
655 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
656 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
657 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
658 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
659 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
660
661 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
662 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
663 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
664 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
665 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
666 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
667
668 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
669 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
670 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
671 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
672 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
673 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
674 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
675
676 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
677 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
678 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
679 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
680
681 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
682 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
683 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
684 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
685
686 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
687 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
688 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
689
690 PINMUX_IPSR_GPSR(IP1_31_28, A0),
691 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
692 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
693 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
694 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
695 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
696
697 /* IPSR2 */
698 PINMUX_IPSR_GPSR(IP2_3_0, A1),
699 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
700 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
701 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
702 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
703 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
704
705 PINMUX_IPSR_GPSR(IP2_7_4, A2),
706 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
707 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
708 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
709 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
710 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
711
712 PINMUX_IPSR_GPSR(IP2_11_8, A3),
713 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
714 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
715 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
716 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
717 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
718
719 PINMUX_IPSR_GPSR(IP2_15_12, A4),
720 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
721 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
722 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
723 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
724 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
725
726 PINMUX_IPSR_GPSR(IP2_19_16, A5),
727 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
728 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
729 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
730 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
731 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
732 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
733
734 PINMUX_IPSR_GPSR(IP2_23_20, A6),
735 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
736 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
737 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
738 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
739 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
740 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
741
742 PINMUX_IPSR_GPSR(IP2_27_24, A7),
743 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
744 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
745 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
746 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
747 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
748 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
749
750 PINMUX_IPSR_GPSR(IP2_31_28, A8),
751 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
752 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
753 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
754 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
755 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
756 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
757
758 /* IPSR3 */
759 PINMUX_IPSR_GPSR(IP3_3_0, A9),
760 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
761 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
762 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
763
764 PINMUX_IPSR_GPSR(IP3_7_4, A10),
765 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
766 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
767 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
768
769 PINMUX_IPSR_GPSR(IP3_11_8, A11),
770 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
771 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
772 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
773 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
774 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
775 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
776 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
777 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
778
779 PINMUX_IPSR_GPSR(IP3_15_12, A12),
780 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
781 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
782 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
783 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
784 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
785
786 PINMUX_IPSR_GPSR(IP3_19_16, A13),
787 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
788 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
789 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
790 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
791 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
792
793 PINMUX_IPSR_GPSR(IP3_23_20, A14),
794 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
795 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
796 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
797 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
798 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
799
800 PINMUX_IPSR_GPSR(IP3_27_24, A15),
801 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
802 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
803 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
804 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
805 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
806
807 PINMUX_IPSR_GPSR(IP3_31_28, A16),
808 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
809 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
810 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
811
812 /* IPSR4 */
813 PINMUX_IPSR_GPSR(IP4_3_0, A17),
814 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
815 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
816 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
817
818 PINMUX_IPSR_GPSR(IP4_7_4, A18),
819 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
820 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
821 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
822
823 PINMUX_IPSR_GPSR(IP4_11_8, A19),
824 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
825 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
826 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
827
828 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
829 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
830
831 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
832 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
833 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
834
835 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
836 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
837 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
838 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
839 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
840 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
841 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
842 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
843
844 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
845 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
846 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
847 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
848 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
849 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
850
851 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
852 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
853 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
854 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
855 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
856 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
857
858 /* IPSR5 */
859 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
860 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
861 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
862 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
863 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
864 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
865 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
866
867 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
868 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
869 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
870 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
871 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
872 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
873 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
874 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
875
876 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
877 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
878 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
879 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
880
881 PINMUX_IPSR_GPSR(IP5_15_12, D0),
882 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
883 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
884 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
885 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
886
887 PINMUX_IPSR_GPSR(IP5_19_16, D1),
888 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
889 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
890 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
891 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
892
893 PINMUX_IPSR_GPSR(IP5_23_20, D2),
894 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
895 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
896 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
897
898 PINMUX_IPSR_GPSR(IP5_27_24, D3),
899 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
900 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
901 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
902
903 PINMUX_IPSR_GPSR(IP5_31_28, D4),
904 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
905 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
906 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
907
908 /* IPSR6 */
909 PINMUX_IPSR_GPSR(IP6_3_0, D5),
910 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
911 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
912 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
913
914 PINMUX_IPSR_GPSR(IP6_7_4, D6),
915 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
916 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
917 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
918
919 PINMUX_IPSR_GPSR(IP6_11_8, D7),
920 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
921 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
922 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
923
924 PINMUX_IPSR_GPSR(IP6_15_12, D8),
925 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
926 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
927 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
928 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
929 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
930
931 PINMUX_IPSR_GPSR(IP6_19_16, D9),
932 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
933 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
934 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
935 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
936
937 PINMUX_IPSR_GPSR(IP6_23_20, D10),
938 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
939 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
940 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
941 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
942 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
943 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
944
945 PINMUX_IPSR_GPSR(IP6_27_24, D11),
946 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
947 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
948 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
949 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
950 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
951 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
952
953 PINMUX_IPSR_GPSR(IP6_31_28, D12),
954 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
955 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
956 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
957 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
958 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
959
960 /* IPSR7 */
961 PINMUX_IPSR_GPSR(IP7_3_0, D13),
962 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
963 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
964 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
965 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
966 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
967
968 PINMUX_IPSR_GPSR(IP7_7_4, D14),
969 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
970 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
971 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
972 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
973 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
974 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
975
976 PINMUX_IPSR_GPSR(IP7_11_8, D15),
977 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
978 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
979 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
980 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
981 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
982 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
983
984 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
985 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
986 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
987
988 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
989 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
990 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
991
992 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
993 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
994 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
995 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
996
997 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
998 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
999 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1000 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1001
1002 /* IPSR8 */
1003 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1004 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1005 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1006 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1007
1008 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1009 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1010 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1011 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1012
1013 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1014 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1015 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1016
1017 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1018 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1019 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
1020 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1021 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1022
1023 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1024 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1025 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1026 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
1027 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1028 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1029
1030 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1031 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1032 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1033 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
1034 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1035 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1036
1037 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1038 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1039 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1040 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
1041 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1042 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1043
1044 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1045 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1046 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1047 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
1048 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1049 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1050
1051 /* IPSR9 */
1052 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1053 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1054
1055 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1056 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1057
1058 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1059 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1060
1061 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1062 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1063
1064 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1065 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1066
1067 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1068 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1069
1070 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1071 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1072 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1073
1074 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1075 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1076
1077 /* IPSR10 */
1078 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1079 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1080
1081 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1082 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1083
1084 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1085 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1086
1087 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1088 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1089
1090 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1091 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1092
1093 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1094 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1095 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1096
1097 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1098 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1099 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1100
1101 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1102 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1103 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1104
1105 /* IPSR11 */
1106 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1107 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1108 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1109
1110 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1111 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1112
1113 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1114 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
1115 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1116 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1117
1118 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1119 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
1120 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1121
1122 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1123 PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
1124 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1125
1126 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1127 PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
1128 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1129
1130 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1131 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1132 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1133 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1134 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1135 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1136 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1137 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1138 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1139 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1140
1141 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1142 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1143 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1144 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1145 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1146
1147 /* IPSR12 */
1148 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1149 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1150 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1151 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1152 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1153
1154 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1155 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1156 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1157 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1158 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1159 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1160 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1161 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1162
1163 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1164 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1165 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1167 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1168 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1169 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1170 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1171
1172 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1173 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1174 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1175 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1176 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1177
1178 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1179 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1180 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1181 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1182 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1183
1184 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1185 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1186 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1187 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1188 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1189 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1190 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1191
1192 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1193 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1194 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1195 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1196 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1197 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1198 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1199
1200 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1201 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1202 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1203 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1205 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1206 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1207
1208 /* IPSR13 */
1209 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1210 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1211 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1212 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1213 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1214 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1215
1216 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1217 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1218 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1219 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1220 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1221 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1222
1223 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1224 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1225 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1226 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1227 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1229 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1230 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1231
1232 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1233 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1234 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1235 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1236 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1237 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1238
1239 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1240 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1241 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1242 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1243 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1244 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1245
1246 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1247 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1248 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1249 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1250 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1251 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1252 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1253 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1254
1255 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1256 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1257 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1258 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1259 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1260 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1261 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1262
1263 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1264 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1265 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1266 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1267
1268 /* IPSR14 */
1269 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1270 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1271 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
1272 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1273 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1274 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1275 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1276 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1277
1278 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1279 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1280 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1281 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1282 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1283 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1284 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1285 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1286
1287 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1288 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1289 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1290
1291 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1292 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1293 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1294 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1295
1296 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1297 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1298 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1299
1300 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1301 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1302
1303 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1304 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1305
1306 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1307 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1308
1309 /* IPSR15 */
1310 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1311
1312 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1313 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1314
1315 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1316 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1317 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1318
1319 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1320 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1321 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1322 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1323
1324 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1325 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1326 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1328 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1330 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1331
1332 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1333 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1334 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1338 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1339
1340 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1341 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1342 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1346 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1347
1348 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1349 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1350 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1351 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1352 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1354 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1355
1356 /* IPSR16 */
1357 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1358 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1359
1360 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1361 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1362
1363 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1364 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1365 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1366
1367 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1368 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1369 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1370 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1371 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1372 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1373 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1374
1375 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1376 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1377 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1378 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1379 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1380 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1381 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1382
1383 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1384 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1385 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1386 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1387 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1388 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1389 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1391
1392 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1393 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1394 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1395 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1396 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1397 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1398 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1399
1400 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1401 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1402 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1403 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1404 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1405 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1406 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1407 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1408
1409 /* IPSR17 */
1410 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1411 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1412
1413 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1414 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1415 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1416 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1417 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1418
1419 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1420 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1421 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1422 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1423 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1424 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1425 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1426
1427 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1428 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1429 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1430 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1431 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1432 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1433
1434 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1435 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1436 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1437 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1438 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1439 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1440 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1441 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1442 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1443
1444 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1445 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1446 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1447 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1448 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1449 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1450 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1451 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1452 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1453
1454 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1455 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1456 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1457 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1458 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1459 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1460 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1461 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1462 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1463 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1464 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1465
1466 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1467 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1468 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1469 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1470 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1471 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1472 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1473 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1474 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1475
1476 /* IPSR18 */
1477 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1478 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1479 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1480 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1481 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1482 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1483 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1484 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1485 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1486
1487 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1488 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1489 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1490 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1491 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1492 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1493 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1494 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1495 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1496
1497 /* I2C */
1498 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1499 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1500 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
1501
1502 /*
1503 * Static pins can not be muxed between different functions but
1504 * still need mark entries in the pinmux list. Add each static
1505 * pin to the list without an associated function. The sh-pfc
1506 * core will do the right thing and skip trying to mux the pin
1507 * while still applying configuration to it.
1508 */
1509 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1510 PINMUX_STATIC
1511 #undef FM
1512 };
1513
1514 /*
1515 * R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1516 * Physical layout rows: A - AW, cols: 1 - 39.
1517 */
1518 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1519 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1520 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1521 #define PIN_NONE U16_MAX
1522
1523 static const struct sh_pfc_pin pinmux_pins[] = {
1524 PINMUX_GPIO_GP_ALL(),
1525
1526 /*
1527 * Pins not associated with a GPIO port.
1528 *
1529 * The pin positions are different between different r8a77965
1530 * packages, all that is needed for the pfc driver is a unique
1531 * number for each pin. To this end use the pin layout from
1532 * R-Car M3SiP to calculate a unique number for each pin.
1533 */
1534 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1576 };
1577
1578 /* - EtherAVB --------------------------------------------------------------- */
1579 static const unsigned int avb_link_pins[] = {
1580 /* AVB_LINK */
1581 RCAR_GP_PIN(2, 12),
1582 };
1583 static const unsigned int avb_link_mux[] = {
1584 AVB_LINK_MARK,
1585 };
1586 static const unsigned int avb_magic_pins[] = {
1587 /* AVB_MAGIC_ */
1588 RCAR_GP_PIN(2, 10),
1589 };
1590 static const unsigned int avb_magic_mux[] = {
1591 AVB_MAGIC_MARK,
1592 };
1593 static const unsigned int avb_phy_int_pins[] = {
1594 /* AVB_PHY_INT */
1595 RCAR_GP_PIN(2, 11),
1596 };
1597 static const unsigned int avb_phy_int_mux[] = {
1598 AVB_PHY_INT_MARK,
1599 };
1600 static const unsigned int avb_mdio_pins[] = {
1601 /* AVB_MDC, AVB_MDIO */
1602 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1603 };
1604 static const unsigned int avb_mdio_mux[] = {
1605 AVB_MDC_MARK, AVB_MDIO_MARK,
1606 };
1607 static const unsigned int avb_mii_pins[] = {
1608 /*
1609 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1610 * AVB_TD1, AVB_TD2, AVB_TD3,
1611 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1612 * AVB_RD1, AVB_RD2, AVB_RD3,
1613 * AVB_TXCREFCLK
1614 */
1615 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1616 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1617 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1618 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1619 PIN_NUMBER('A', 12),
1620
1621 };
1622 static const unsigned int avb_mii_mux[] = {
1623 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1624 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1625 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1626 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1627 AVB_TXCREFCLK_MARK,
1628 };
1629 static const unsigned int avb_avtp_pps_pins[] = {
1630 /* AVB_AVTP_PPS */
1631 RCAR_GP_PIN(2, 6),
1632 };
1633 static const unsigned int avb_avtp_pps_mux[] = {
1634 AVB_AVTP_PPS_MARK,
1635 };
1636 static const unsigned int avb_avtp_match_a_pins[] = {
1637 /* AVB_AVTP_MATCH_A */
1638 RCAR_GP_PIN(2, 13),
1639 };
1640 static const unsigned int avb_avtp_match_a_mux[] = {
1641 AVB_AVTP_MATCH_A_MARK,
1642 };
1643 static const unsigned int avb_avtp_capture_a_pins[] = {
1644 /* AVB_AVTP_CAPTURE_A */
1645 RCAR_GP_PIN(2, 14),
1646 };
1647 static const unsigned int avb_avtp_capture_a_mux[] = {
1648 AVB_AVTP_CAPTURE_A_MARK,
1649 };
1650 static const unsigned int avb_avtp_match_b_pins[] = {
1651 /* AVB_AVTP_MATCH_B */
1652 RCAR_GP_PIN(1, 8),
1653 };
1654 static const unsigned int avb_avtp_match_b_mux[] = {
1655 AVB_AVTP_MATCH_B_MARK,
1656 };
1657 static const unsigned int avb_avtp_capture_b_pins[] = {
1658 /* AVB_AVTP_CAPTURE_B */
1659 RCAR_GP_PIN(1, 11),
1660 };
1661 static const unsigned int avb_avtp_capture_b_mux[] = {
1662 AVB_AVTP_CAPTURE_B_MARK,
1663 };
1664
1665 /* - DU --------------------------------------------------------------------- */
1666 static const unsigned int du_rgb666_pins[] = {
1667 /* R[7:2], G[7:2], B[7:2] */
1668 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1669 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1670 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1671 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1672 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1673 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1674 };
1675
1676 static const unsigned int du_rgb666_mux[] = {
1677 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1678 DU_DR3_MARK, DU_DR2_MARK,
1679 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1680 DU_DG3_MARK, DU_DG2_MARK,
1681 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1682 DU_DB3_MARK, DU_DB2_MARK,
1683 };
1684
1685 static const unsigned int du_rgb888_pins[] = {
1686 /* R[7:0], G[7:0], B[7:0] */
1687 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1688 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1689 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1690 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1691 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1692 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1693 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1694 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1695 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1696 };
1697
1698 static const unsigned int du_rgb888_mux[] = {
1699 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1700 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1701 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1702 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1703 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1704 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1705 };
1706
1707 static const unsigned int du_clk_out_0_pins[] = {
1708 /* CLKOUT */
1709 RCAR_GP_PIN(1, 27),
1710 };
1711
1712 static const unsigned int du_clk_out_0_mux[] = {
1713 DU_DOTCLKOUT0_MARK
1714 };
1715
1716 static const unsigned int du_clk_out_1_pins[] = {
1717 /* CLKOUT */
1718 RCAR_GP_PIN(2, 3),
1719 };
1720
1721 static const unsigned int du_clk_out_1_mux[] = {
1722 DU_DOTCLKOUT1_MARK
1723 };
1724
1725 static const unsigned int du_sync_pins[] = {
1726 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1727 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1728 };
1729
1730 static const unsigned int du_sync_mux[] = {
1731 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
1732 };
1733
1734 static const unsigned int du_oddf_pins[] = {
1735 /* EXDISP/EXODDF/EXCDE */
1736 RCAR_GP_PIN(2, 2),
1737 };
1738
1739 static const unsigned int du_oddf_mux[] = {
1740 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1741 };
1742
1743 static const unsigned int du_cde_pins[] = {
1744 /* CDE */
1745 RCAR_GP_PIN(2, 0),
1746 };
1747
1748 static const unsigned int du_cde_mux[] = {
1749 DU_CDE_MARK,
1750 };
1751
1752 static const unsigned int du_disp_pins[] = {
1753 /* DISP */
1754 RCAR_GP_PIN(2, 1),
1755 };
1756
1757 static const unsigned int du_disp_mux[] = {
1758 DU_DISP_MARK,
1759 };
1760
1761 /* - HSCIF0 ----------------------------------------------------------------- */
1762 static const unsigned int hscif0_data_pins[] = {
1763 /* RX, TX */
1764 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1765 };
1766
1767 static const unsigned int hscif0_data_mux[] = {
1768 HRX0_MARK, HTX0_MARK,
1769 };
1770
1771 static const unsigned int hscif0_clk_pins[] = {
1772 /* SCK */
1773 RCAR_GP_PIN(5, 12),
1774 };
1775
1776 static const unsigned int hscif0_clk_mux[] = {
1777 HSCK0_MARK,
1778 };
1779
1780 static const unsigned int hscif0_ctrl_pins[] = {
1781 /* RTS, CTS */
1782 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
1783 };
1784
1785 static const unsigned int hscif0_ctrl_mux[] = {
1786 HRTS0_N_MARK, HCTS0_N_MARK,
1787 };
1788
1789 /* - HSCIF1 ----------------------------------------------------------------- */
1790 static const unsigned int hscif1_data_a_pins[] = {
1791 /* RX, TX */
1792 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1793 };
1794
1795 static const unsigned int hscif1_data_a_mux[] = {
1796 HRX1_A_MARK, HTX1_A_MARK,
1797 };
1798
1799 static const unsigned int hscif1_clk_a_pins[] = {
1800 /* SCK */
1801 RCAR_GP_PIN(6, 21),
1802 };
1803
1804 static const unsigned int hscif1_clk_a_mux[] = {
1805 HSCK1_A_MARK,
1806 };
1807
1808 static const unsigned int hscif1_ctrl_a_pins[] = {
1809 /* RTS, CTS */
1810 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
1811 };
1812
1813 static const unsigned int hscif1_ctrl_a_mux[] = {
1814 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
1815 };
1816
1817 static const unsigned int hscif1_data_b_pins[] = {
1818 /* RX, TX */
1819 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1820 };
1821
1822 static const unsigned int hscif1_data_b_mux[] = {
1823 HRX1_B_MARK, HTX1_B_MARK,
1824 };
1825
1826 static const unsigned int hscif1_clk_b_pins[] = {
1827 /* SCK */
1828 RCAR_GP_PIN(5, 0),
1829 };
1830
1831 static const unsigned int hscif1_clk_b_mux[] = {
1832 HSCK1_B_MARK,
1833 };
1834
1835 static const unsigned int hscif1_ctrl_b_pins[] = {
1836 /* RTS, CTS */
1837 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
1838 };
1839
1840 static const unsigned int hscif1_ctrl_b_mux[] = {
1841 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1842 };
1843
1844 /* - HSCIF2 ----------------------------------------------------------------- */
1845 static const unsigned int hscif2_data_a_pins[] = {
1846 /* RX, TX */
1847 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1848 };
1849
1850 static const unsigned int hscif2_data_a_mux[] = {
1851 HRX2_A_MARK, HTX2_A_MARK,
1852 };
1853
1854 static const unsigned int hscif2_clk_a_pins[] = {
1855 /* SCK */
1856 RCAR_GP_PIN(6, 10),
1857 };
1858
1859 static const unsigned int hscif2_clk_a_mux[] = {
1860 HSCK2_A_MARK,
1861 };
1862
1863 static const unsigned int hscif2_ctrl_a_pins[] = {
1864 /* RTS, CTS */
1865 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1866 };
1867
1868 static const unsigned int hscif2_ctrl_a_mux[] = {
1869 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
1870 };
1871
1872 static const unsigned int hscif2_data_b_pins[] = {
1873 /* RX, TX */
1874 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1875 };
1876
1877 static const unsigned int hscif2_data_b_mux[] = {
1878 HRX2_B_MARK, HTX2_B_MARK,
1879 };
1880
1881 static const unsigned int hscif2_clk_b_pins[] = {
1882 /* SCK */
1883 RCAR_GP_PIN(6, 21),
1884 };
1885
1886 static const unsigned int hscif2_clk_b_mux[] = {
1887 HSCK2_B_MARK,
1888 };
1889
1890 static const unsigned int hscif2_ctrl_b_pins[] = {
1891 /* RTS, CTS */
1892 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
1893 };
1894
1895 static const unsigned int hscif2_ctrl_b_mux[] = {
1896 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
1897 };
1898
1899 static const unsigned int hscif2_data_c_pins[] = {
1900 /* RX, TX */
1901 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
1902 };
1903
1904 static const unsigned int hscif2_data_c_mux[] = {
1905 HRX2_C_MARK, HTX2_C_MARK,
1906 };
1907
1908 static const unsigned int hscif2_clk_c_pins[] = {
1909 /* SCK */
1910 RCAR_GP_PIN(6, 24),
1911 };
1912
1913 static const unsigned int hscif2_clk_c_mux[] = {
1914 HSCK2_C_MARK,
1915 };
1916
1917 static const unsigned int hscif2_ctrl_c_pins[] = {
1918 /* RTS, CTS */
1919 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
1920 };
1921
1922 static const unsigned int hscif2_ctrl_c_mux[] = {
1923 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
1924 };
1925
1926 /* - HSCIF3 ----------------------------------------------------------------- */
1927 static const unsigned int hscif3_data_a_pins[] = {
1928 /* RX, TX */
1929 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1930 };
1931
1932 static const unsigned int hscif3_data_a_mux[] = {
1933 HRX3_A_MARK, HTX3_A_MARK,
1934 };
1935
1936 static const unsigned int hscif3_clk_pins[] = {
1937 /* SCK */
1938 RCAR_GP_PIN(1, 22),
1939 };
1940
1941 static const unsigned int hscif3_clk_mux[] = {
1942 HSCK3_MARK,
1943 };
1944
1945 static const unsigned int hscif3_ctrl_pins[] = {
1946 /* RTS, CTS */
1947 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1948 };
1949
1950 static const unsigned int hscif3_ctrl_mux[] = {
1951 HRTS3_N_MARK, HCTS3_N_MARK,
1952 };
1953
1954 static const unsigned int hscif3_data_b_pins[] = {
1955 /* RX, TX */
1956 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
1957 };
1958
1959 static const unsigned int hscif3_data_b_mux[] = {
1960 HRX3_B_MARK, HTX3_B_MARK,
1961 };
1962
1963 static const unsigned int hscif3_data_c_pins[] = {
1964 /* RX, TX */
1965 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1966 };
1967
1968 static const unsigned int hscif3_data_c_mux[] = {
1969 HRX3_C_MARK, HTX3_C_MARK,
1970 };
1971
1972 static const unsigned int hscif3_data_d_pins[] = {
1973 /* RX, TX */
1974 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1975 };
1976
1977 static const unsigned int hscif3_data_d_mux[] = {
1978 HRX3_D_MARK, HTX3_D_MARK,
1979 };
1980
1981 /* - HSCIF4 ----------------------------------------------------------------- */
1982 static const unsigned int hscif4_data_a_pins[] = {
1983 /* RX, TX */
1984 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
1985 };
1986
1987 static const unsigned int hscif4_data_a_mux[] = {
1988 HRX4_A_MARK, HTX4_A_MARK,
1989 };
1990
1991 static const unsigned int hscif4_clk_pins[] = {
1992 /* SCK */
1993 RCAR_GP_PIN(1, 11),
1994 };
1995
1996 static const unsigned int hscif4_clk_mux[] = {
1997 HSCK4_MARK,
1998 };
1999
2000 static const unsigned int hscif4_ctrl_pins[] = {
2001 /* RTS, CTS */
2002 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2003 };
2004
2005 static const unsigned int hscif4_ctrl_mux[] = {
2006 HRTS4_N_MARK, HCTS4_N_MARK,
2007 };
2008
2009 static const unsigned int hscif4_data_b_pins[] = {
2010 /* RX, TX */
2011 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2012 };
2013
2014 static const unsigned int hscif4_data_b_mux[] = {
2015 HRX4_B_MARK, HTX4_B_MARK,
2016 };
2017
2018 /* - I2C -------------------------------------------------------------------- */
2019 static const unsigned int i2c1_a_pins[] = {
2020 /* SDA, SCL */
2021 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2022 };
2023 static const unsigned int i2c1_a_mux[] = {
2024 SDA1_A_MARK, SCL1_A_MARK,
2025 };
2026 static const unsigned int i2c1_b_pins[] = {
2027 /* SDA, SCL */
2028 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2029 };
2030 static const unsigned int i2c1_b_mux[] = {
2031 SDA1_B_MARK, SCL1_B_MARK,
2032 };
2033 static const unsigned int i2c2_a_pins[] = {
2034 /* SDA, SCL */
2035 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2036 };
2037 static const unsigned int i2c2_a_mux[] = {
2038 SDA2_A_MARK, SCL2_A_MARK,
2039 };
2040 static const unsigned int i2c2_b_pins[] = {
2041 /* SDA, SCL */
2042 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2043 };
2044 static const unsigned int i2c2_b_mux[] = {
2045 SDA2_B_MARK, SCL2_B_MARK,
2046 };
2047 static const unsigned int i2c6_a_pins[] = {
2048 /* SDA, SCL */
2049 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2050 };
2051 static const unsigned int i2c6_a_mux[] = {
2052 SDA6_A_MARK, SCL6_A_MARK,
2053 };
2054 static const unsigned int i2c6_b_pins[] = {
2055 /* SDA, SCL */
2056 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2057 };
2058 static const unsigned int i2c6_b_mux[] = {
2059 SDA6_B_MARK, SCL6_B_MARK,
2060 };
2061 static const unsigned int i2c6_c_pins[] = {
2062 /* SDA, SCL */
2063 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2064 };
2065 static const unsigned int i2c6_c_mux[] = {
2066 SDA6_C_MARK, SCL6_C_MARK,
2067 };
2068
2069 /* - INTC-EX ---------------------------------------------------------------- */
2070 static const unsigned int intc_ex_irq0_pins[] = {
2071 /* IRQ0 */
2072 RCAR_GP_PIN(2, 0),
2073 };
2074 static const unsigned int intc_ex_irq0_mux[] = {
2075 IRQ0_MARK,
2076 };
2077 static const unsigned int intc_ex_irq1_pins[] = {
2078 /* IRQ1 */
2079 RCAR_GP_PIN(2, 1),
2080 };
2081 static const unsigned int intc_ex_irq1_mux[] = {
2082 IRQ1_MARK,
2083 };
2084 static const unsigned int intc_ex_irq2_pins[] = {
2085 /* IRQ2 */
2086 RCAR_GP_PIN(2, 2),
2087 };
2088 static const unsigned int intc_ex_irq2_mux[] = {
2089 IRQ2_MARK,
2090 };
2091 static const unsigned int intc_ex_irq3_pins[] = {
2092 /* IRQ3 */
2093 RCAR_GP_PIN(2, 3),
2094 };
2095 static const unsigned int intc_ex_irq3_mux[] = {
2096 IRQ3_MARK,
2097 };
2098 static const unsigned int intc_ex_irq4_pins[] = {
2099 /* IRQ4 */
2100 RCAR_GP_PIN(2, 4),
2101 };
2102 static const unsigned int intc_ex_irq4_mux[] = {
2103 IRQ4_MARK,
2104 };
2105 static const unsigned int intc_ex_irq5_pins[] = {
2106 /* IRQ5 */
2107 RCAR_GP_PIN(2, 5),
2108 };
2109 static const unsigned int intc_ex_irq5_mux[] = {
2110 IRQ5_MARK,
2111 };
2112
2113 /* - MSIOF0 ----------------------------------------------------------------- */
2114 static const unsigned int msiof0_clk_pins[] = {
2115 /* SCK */
2116 RCAR_GP_PIN(5, 17),
2117 };
2118 static const unsigned int msiof0_clk_mux[] = {
2119 MSIOF0_SCK_MARK,
2120 };
2121 static const unsigned int msiof0_sync_pins[] = {
2122 /* SYNC */
2123 RCAR_GP_PIN(5, 18),
2124 };
2125 static const unsigned int msiof0_sync_mux[] = {
2126 MSIOF0_SYNC_MARK,
2127 };
2128 static const unsigned int msiof0_ss1_pins[] = {
2129 /* SS1 */
2130 RCAR_GP_PIN(5, 19),
2131 };
2132 static const unsigned int msiof0_ss1_mux[] = {
2133 MSIOF0_SS1_MARK,
2134 };
2135 static const unsigned int msiof0_ss2_pins[] = {
2136 /* SS2 */
2137 RCAR_GP_PIN(5, 21),
2138 };
2139 static const unsigned int msiof0_ss2_mux[] = {
2140 MSIOF0_SS2_MARK,
2141 };
2142 static const unsigned int msiof0_txd_pins[] = {
2143 /* TXD */
2144 RCAR_GP_PIN(5, 20),
2145 };
2146 static const unsigned int msiof0_txd_mux[] = {
2147 MSIOF0_TXD_MARK,
2148 };
2149 static const unsigned int msiof0_rxd_pins[] = {
2150 /* RXD */
2151 RCAR_GP_PIN(5, 22),
2152 };
2153 static const unsigned int msiof0_rxd_mux[] = {
2154 MSIOF0_RXD_MARK,
2155 };
2156 /* - MSIOF1 ----------------------------------------------------------------- */
2157 static const unsigned int msiof1_clk_a_pins[] = {
2158 /* SCK */
2159 RCAR_GP_PIN(6, 8),
2160 };
2161 static const unsigned int msiof1_clk_a_mux[] = {
2162 MSIOF1_SCK_A_MARK,
2163 };
2164 static const unsigned int msiof1_sync_a_pins[] = {
2165 /* SYNC */
2166 RCAR_GP_PIN(6, 9),
2167 };
2168 static const unsigned int msiof1_sync_a_mux[] = {
2169 MSIOF1_SYNC_A_MARK,
2170 };
2171 static const unsigned int msiof1_ss1_a_pins[] = {
2172 /* SS1 */
2173 RCAR_GP_PIN(6, 5),
2174 };
2175 static const unsigned int msiof1_ss1_a_mux[] = {
2176 MSIOF1_SS1_A_MARK,
2177 };
2178 static const unsigned int msiof1_ss2_a_pins[] = {
2179 /* SS2 */
2180 RCAR_GP_PIN(6, 6),
2181 };
2182 static const unsigned int msiof1_ss2_a_mux[] = {
2183 MSIOF1_SS2_A_MARK,
2184 };
2185 static const unsigned int msiof1_txd_a_pins[] = {
2186 /* TXD */
2187 RCAR_GP_PIN(6, 7),
2188 };
2189 static const unsigned int msiof1_txd_a_mux[] = {
2190 MSIOF1_TXD_A_MARK,
2191 };
2192 static const unsigned int msiof1_rxd_a_pins[] = {
2193 /* RXD */
2194 RCAR_GP_PIN(6, 10),
2195 };
2196 static const unsigned int msiof1_rxd_a_mux[] = {
2197 MSIOF1_RXD_A_MARK,
2198 };
2199 static const unsigned int msiof1_clk_b_pins[] = {
2200 /* SCK */
2201 RCAR_GP_PIN(5, 9),
2202 };
2203 static const unsigned int msiof1_clk_b_mux[] = {
2204 MSIOF1_SCK_B_MARK,
2205 };
2206 static const unsigned int msiof1_sync_b_pins[] = {
2207 /* SYNC */
2208 RCAR_GP_PIN(5, 3),
2209 };
2210 static const unsigned int msiof1_sync_b_mux[] = {
2211 MSIOF1_SYNC_B_MARK,
2212 };
2213 static const unsigned int msiof1_ss1_b_pins[] = {
2214 /* SS1 */
2215 RCAR_GP_PIN(5, 4),
2216 };
2217 static const unsigned int msiof1_ss1_b_mux[] = {
2218 MSIOF1_SS1_B_MARK,
2219 };
2220 static const unsigned int msiof1_ss2_b_pins[] = {
2221 /* SS2 */
2222 RCAR_GP_PIN(5, 0),
2223 };
2224 static const unsigned int msiof1_ss2_b_mux[] = {
2225 MSIOF1_SS2_B_MARK,
2226 };
2227 static const unsigned int msiof1_txd_b_pins[] = {
2228 /* TXD */
2229 RCAR_GP_PIN(5, 8),
2230 };
2231 static const unsigned int msiof1_txd_b_mux[] = {
2232 MSIOF1_TXD_B_MARK,
2233 };
2234 static const unsigned int msiof1_rxd_b_pins[] = {
2235 /* RXD */
2236 RCAR_GP_PIN(5, 7),
2237 };
2238 static const unsigned int msiof1_rxd_b_mux[] = {
2239 MSIOF1_RXD_B_MARK,
2240 };
2241 static const unsigned int msiof1_clk_c_pins[] = {
2242 /* SCK */
2243 RCAR_GP_PIN(6, 17),
2244 };
2245 static const unsigned int msiof1_clk_c_mux[] = {
2246 MSIOF1_SCK_C_MARK,
2247 };
2248 static const unsigned int msiof1_sync_c_pins[] = {
2249 /* SYNC */
2250 RCAR_GP_PIN(6, 18),
2251 };
2252 static const unsigned int msiof1_sync_c_mux[] = {
2253 MSIOF1_SYNC_C_MARK,
2254 };
2255 static const unsigned int msiof1_ss1_c_pins[] = {
2256 /* SS1 */
2257 RCAR_GP_PIN(6, 21),
2258 };
2259 static const unsigned int msiof1_ss1_c_mux[] = {
2260 MSIOF1_SS1_C_MARK,
2261 };
2262 static const unsigned int msiof1_ss2_c_pins[] = {
2263 /* SS2 */
2264 RCAR_GP_PIN(6, 27),
2265 };
2266 static const unsigned int msiof1_ss2_c_mux[] = {
2267 MSIOF1_SS2_C_MARK,
2268 };
2269 static const unsigned int msiof1_txd_c_pins[] = {
2270 /* TXD */
2271 RCAR_GP_PIN(6, 20),
2272 };
2273 static const unsigned int msiof1_txd_c_mux[] = {
2274 MSIOF1_TXD_C_MARK,
2275 };
2276 static const unsigned int msiof1_rxd_c_pins[] = {
2277 /* RXD */
2278 RCAR_GP_PIN(6, 19),
2279 };
2280 static const unsigned int msiof1_rxd_c_mux[] = {
2281 MSIOF1_RXD_C_MARK,
2282 };
2283 static const unsigned int msiof1_clk_d_pins[] = {
2284 /* SCK */
2285 RCAR_GP_PIN(5, 12),
2286 };
2287 static const unsigned int msiof1_clk_d_mux[] = {
2288 MSIOF1_SCK_D_MARK,
2289 };
2290 static const unsigned int msiof1_sync_d_pins[] = {
2291 /* SYNC */
2292 RCAR_GP_PIN(5, 15),
2293 };
2294 static const unsigned int msiof1_sync_d_mux[] = {
2295 MSIOF1_SYNC_D_MARK,
2296 };
2297 static const unsigned int msiof1_ss1_d_pins[] = {
2298 /* SS1 */
2299 RCAR_GP_PIN(5, 16),
2300 };
2301 static const unsigned int msiof1_ss1_d_mux[] = {
2302 MSIOF1_SS1_D_MARK,
2303 };
2304 static const unsigned int msiof1_ss2_d_pins[] = {
2305 /* SS2 */
2306 RCAR_GP_PIN(5, 21),
2307 };
2308 static const unsigned int msiof1_ss2_d_mux[] = {
2309 MSIOF1_SS2_D_MARK,
2310 };
2311 static const unsigned int msiof1_txd_d_pins[] = {
2312 /* TXD */
2313 RCAR_GP_PIN(5, 14),
2314 };
2315 static const unsigned int msiof1_txd_d_mux[] = {
2316 MSIOF1_TXD_D_MARK,
2317 };
2318 static const unsigned int msiof1_rxd_d_pins[] = {
2319 /* RXD */
2320 RCAR_GP_PIN(5, 13),
2321 };
2322 static const unsigned int msiof1_rxd_d_mux[] = {
2323 MSIOF1_RXD_D_MARK,
2324 };
2325 static const unsigned int msiof1_clk_e_pins[] = {
2326 /* SCK */
2327 RCAR_GP_PIN(3, 0),
2328 };
2329 static const unsigned int msiof1_clk_e_mux[] = {
2330 MSIOF1_SCK_E_MARK,
2331 };
2332 static const unsigned int msiof1_sync_e_pins[] = {
2333 /* SYNC */
2334 RCAR_GP_PIN(3, 1),
2335 };
2336 static const unsigned int msiof1_sync_e_mux[] = {
2337 MSIOF1_SYNC_E_MARK,
2338 };
2339 static const unsigned int msiof1_ss1_e_pins[] = {
2340 /* SS1 */
2341 RCAR_GP_PIN(3, 4),
2342 };
2343 static const unsigned int msiof1_ss1_e_mux[] = {
2344 MSIOF1_SS1_E_MARK,
2345 };
2346 static const unsigned int msiof1_ss2_e_pins[] = {
2347 /* SS2 */
2348 RCAR_GP_PIN(3, 5),
2349 };
2350 static const unsigned int msiof1_ss2_e_mux[] = {
2351 MSIOF1_SS2_E_MARK,
2352 };
2353 static const unsigned int msiof1_txd_e_pins[] = {
2354 /* TXD */
2355 RCAR_GP_PIN(3, 3),
2356 };
2357 static const unsigned int msiof1_txd_e_mux[] = {
2358 MSIOF1_TXD_E_MARK,
2359 };
2360 static const unsigned int msiof1_rxd_e_pins[] = {
2361 /* RXD */
2362 RCAR_GP_PIN(3, 2),
2363 };
2364 static const unsigned int msiof1_rxd_e_mux[] = {
2365 MSIOF1_RXD_E_MARK,
2366 };
2367 static const unsigned int msiof1_clk_f_pins[] = {
2368 /* SCK */
2369 RCAR_GP_PIN(5, 23),
2370 };
2371 static const unsigned int msiof1_clk_f_mux[] = {
2372 MSIOF1_SCK_F_MARK,
2373 };
2374 static const unsigned int msiof1_sync_f_pins[] = {
2375 /* SYNC */
2376 RCAR_GP_PIN(5, 24),
2377 };
2378 static const unsigned int msiof1_sync_f_mux[] = {
2379 MSIOF1_SYNC_F_MARK,
2380 };
2381 static const unsigned int msiof1_ss1_f_pins[] = {
2382 /* SS1 */
2383 RCAR_GP_PIN(6, 1),
2384 };
2385 static const unsigned int msiof1_ss1_f_mux[] = {
2386 MSIOF1_SS1_F_MARK,
2387 };
2388 static const unsigned int msiof1_ss2_f_pins[] = {
2389 /* SS2 */
2390 RCAR_GP_PIN(6, 2),
2391 };
2392 static const unsigned int msiof1_ss2_f_mux[] = {
2393 MSIOF1_SS2_F_MARK,
2394 };
2395 static const unsigned int msiof1_txd_f_pins[] = {
2396 /* TXD */
2397 RCAR_GP_PIN(6, 0),
2398 };
2399 static const unsigned int msiof1_txd_f_mux[] = {
2400 MSIOF1_TXD_F_MARK,
2401 };
2402 static const unsigned int msiof1_rxd_f_pins[] = {
2403 /* RXD */
2404 RCAR_GP_PIN(5, 25),
2405 };
2406 static const unsigned int msiof1_rxd_f_mux[] = {
2407 MSIOF1_RXD_F_MARK,
2408 };
2409 static const unsigned int msiof1_clk_g_pins[] = {
2410 /* SCK */
2411 RCAR_GP_PIN(3, 6),
2412 };
2413 static const unsigned int msiof1_clk_g_mux[] = {
2414 MSIOF1_SCK_G_MARK,
2415 };
2416 static const unsigned int msiof1_sync_g_pins[] = {
2417 /* SYNC */
2418 RCAR_GP_PIN(3, 7),
2419 };
2420 static const unsigned int msiof1_sync_g_mux[] = {
2421 MSIOF1_SYNC_G_MARK,
2422 };
2423 static const unsigned int msiof1_ss1_g_pins[] = {
2424 /* SS1 */
2425 RCAR_GP_PIN(3, 10),
2426 };
2427 static const unsigned int msiof1_ss1_g_mux[] = {
2428 MSIOF1_SS1_G_MARK,
2429 };
2430 static const unsigned int msiof1_ss2_g_pins[] = {
2431 /* SS2 */
2432 RCAR_GP_PIN(3, 11),
2433 };
2434 static const unsigned int msiof1_ss2_g_mux[] = {
2435 MSIOF1_SS2_G_MARK,
2436 };
2437 static const unsigned int msiof1_txd_g_pins[] = {
2438 /* TXD */
2439 RCAR_GP_PIN(3, 9),
2440 };
2441 static const unsigned int msiof1_txd_g_mux[] = {
2442 MSIOF1_TXD_G_MARK,
2443 };
2444 static const unsigned int msiof1_rxd_g_pins[] = {
2445 /* RXD */
2446 RCAR_GP_PIN(3, 8),
2447 };
2448 static const unsigned int msiof1_rxd_g_mux[] = {
2449 MSIOF1_RXD_G_MARK,
2450 };
2451 /* - MSIOF2 ----------------------------------------------------------------- */
2452 static const unsigned int msiof2_clk_a_pins[] = {
2453 /* SCK */
2454 RCAR_GP_PIN(1, 9),
2455 };
2456 static const unsigned int msiof2_clk_a_mux[] = {
2457 MSIOF2_SCK_A_MARK,
2458 };
2459 static const unsigned int msiof2_sync_a_pins[] = {
2460 /* SYNC */
2461 RCAR_GP_PIN(1, 8),
2462 };
2463 static const unsigned int msiof2_sync_a_mux[] = {
2464 MSIOF2_SYNC_A_MARK,
2465 };
2466 static const unsigned int msiof2_ss1_a_pins[] = {
2467 /* SS1 */
2468 RCAR_GP_PIN(1, 6),
2469 };
2470 static const unsigned int msiof2_ss1_a_mux[] = {
2471 MSIOF2_SS1_A_MARK,
2472 };
2473 static const unsigned int msiof2_ss2_a_pins[] = {
2474 /* SS2 */
2475 RCAR_GP_PIN(1, 7),
2476 };
2477 static const unsigned int msiof2_ss2_a_mux[] = {
2478 MSIOF2_SS2_A_MARK,
2479 };
2480 static const unsigned int msiof2_txd_a_pins[] = {
2481 /* TXD */
2482 RCAR_GP_PIN(1, 11),
2483 };
2484 static const unsigned int msiof2_txd_a_mux[] = {
2485 MSIOF2_TXD_A_MARK,
2486 };
2487 static const unsigned int msiof2_rxd_a_pins[] = {
2488 /* RXD */
2489 RCAR_GP_PIN(1, 10),
2490 };
2491 static const unsigned int msiof2_rxd_a_mux[] = {
2492 MSIOF2_RXD_A_MARK,
2493 };
2494 static const unsigned int msiof2_clk_b_pins[] = {
2495 /* SCK */
2496 RCAR_GP_PIN(0, 4),
2497 };
2498 static const unsigned int msiof2_clk_b_mux[] = {
2499 MSIOF2_SCK_B_MARK,
2500 };
2501 static const unsigned int msiof2_sync_b_pins[] = {
2502 /* SYNC */
2503 RCAR_GP_PIN(0, 5),
2504 };
2505 static const unsigned int msiof2_sync_b_mux[] = {
2506 MSIOF2_SYNC_B_MARK,
2507 };
2508 static const unsigned int msiof2_ss1_b_pins[] = {
2509 /* SS1 */
2510 RCAR_GP_PIN(0, 0),
2511 };
2512 static const unsigned int msiof2_ss1_b_mux[] = {
2513 MSIOF2_SS1_B_MARK,
2514 };
2515 static const unsigned int msiof2_ss2_b_pins[] = {
2516 /* SS2 */
2517 RCAR_GP_PIN(0, 1),
2518 };
2519 static const unsigned int msiof2_ss2_b_mux[] = {
2520 MSIOF2_SS2_B_MARK,
2521 };
2522 static const unsigned int msiof2_txd_b_pins[] = {
2523 /* TXD */
2524 RCAR_GP_PIN(0, 7),
2525 };
2526 static const unsigned int msiof2_txd_b_mux[] = {
2527 MSIOF2_TXD_B_MARK,
2528 };
2529 static const unsigned int msiof2_rxd_b_pins[] = {
2530 /* RXD */
2531 RCAR_GP_PIN(0, 6),
2532 };
2533 static const unsigned int msiof2_rxd_b_mux[] = {
2534 MSIOF2_RXD_B_MARK,
2535 };
2536 static const unsigned int msiof2_clk_c_pins[] = {
2537 /* SCK */
2538 RCAR_GP_PIN(2, 12),
2539 };
2540 static const unsigned int msiof2_clk_c_mux[] = {
2541 MSIOF2_SCK_C_MARK,
2542 };
2543 static const unsigned int msiof2_sync_c_pins[] = {
2544 /* SYNC */
2545 RCAR_GP_PIN(2, 11),
2546 };
2547 static const unsigned int msiof2_sync_c_mux[] = {
2548 MSIOF2_SYNC_C_MARK,
2549 };
2550 static const unsigned int msiof2_ss1_c_pins[] = {
2551 /* SS1 */
2552 RCAR_GP_PIN(2, 10),
2553 };
2554 static const unsigned int msiof2_ss1_c_mux[] = {
2555 MSIOF2_SS1_C_MARK,
2556 };
2557 static const unsigned int msiof2_ss2_c_pins[] = {
2558 /* SS2 */
2559 RCAR_GP_PIN(2, 9),
2560 };
2561 static const unsigned int msiof2_ss2_c_mux[] = {
2562 MSIOF2_SS2_C_MARK,
2563 };
2564 static const unsigned int msiof2_txd_c_pins[] = {
2565 /* TXD */
2566 RCAR_GP_PIN(2, 14),
2567 };
2568 static const unsigned int msiof2_txd_c_mux[] = {
2569 MSIOF2_TXD_C_MARK,
2570 };
2571 static const unsigned int msiof2_rxd_c_pins[] = {
2572 /* RXD */
2573 RCAR_GP_PIN(2, 13),
2574 };
2575 static const unsigned int msiof2_rxd_c_mux[] = {
2576 MSIOF2_RXD_C_MARK,
2577 };
2578 static const unsigned int msiof2_clk_d_pins[] = {
2579 /* SCK */
2580 RCAR_GP_PIN(0, 8),
2581 };
2582 static const unsigned int msiof2_clk_d_mux[] = {
2583 MSIOF2_SCK_D_MARK,
2584 };
2585 static const unsigned int msiof2_sync_d_pins[] = {
2586 /* SYNC */
2587 RCAR_GP_PIN(0, 9),
2588 };
2589 static const unsigned int msiof2_sync_d_mux[] = {
2590 MSIOF2_SYNC_D_MARK,
2591 };
2592 static const unsigned int msiof2_ss1_d_pins[] = {
2593 /* SS1 */
2594 RCAR_GP_PIN(0, 12),
2595 };
2596 static const unsigned int msiof2_ss1_d_mux[] = {
2597 MSIOF2_SS1_D_MARK,
2598 };
2599 static const unsigned int msiof2_ss2_d_pins[] = {
2600 /* SS2 */
2601 RCAR_GP_PIN(0, 13),
2602 };
2603 static const unsigned int msiof2_ss2_d_mux[] = {
2604 MSIOF2_SS2_D_MARK,
2605 };
2606 static const unsigned int msiof2_txd_d_pins[] = {
2607 /* TXD */
2608 RCAR_GP_PIN(0, 11),
2609 };
2610 static const unsigned int msiof2_txd_d_mux[] = {
2611 MSIOF2_TXD_D_MARK,
2612 };
2613 static const unsigned int msiof2_rxd_d_pins[] = {
2614 /* RXD */
2615 RCAR_GP_PIN(0, 10),
2616 };
2617 static const unsigned int msiof2_rxd_d_mux[] = {
2618 MSIOF2_RXD_D_MARK,
2619 };
2620 /* - MSIOF3 ----------------------------------------------------------------- */
2621 static const unsigned int msiof3_clk_a_pins[] = {
2622 /* SCK */
2623 RCAR_GP_PIN(0, 0),
2624 };
2625 static const unsigned int msiof3_clk_a_mux[] = {
2626 MSIOF3_SCK_A_MARK,
2627 };
2628 static const unsigned int msiof3_sync_a_pins[] = {
2629 /* SYNC */
2630 RCAR_GP_PIN(0, 1),
2631 };
2632 static const unsigned int msiof3_sync_a_mux[] = {
2633 MSIOF3_SYNC_A_MARK,
2634 };
2635 static const unsigned int msiof3_ss1_a_pins[] = {
2636 /* SS1 */
2637 RCAR_GP_PIN(0, 14),
2638 };
2639 static const unsigned int msiof3_ss1_a_mux[] = {
2640 MSIOF3_SS1_A_MARK,
2641 };
2642 static const unsigned int msiof3_ss2_a_pins[] = {
2643 /* SS2 */
2644 RCAR_GP_PIN(0, 15),
2645 };
2646 static const unsigned int msiof3_ss2_a_mux[] = {
2647 MSIOF3_SS2_A_MARK,
2648 };
2649 static const unsigned int msiof3_txd_a_pins[] = {
2650 /* TXD */
2651 RCAR_GP_PIN(0, 3),
2652 };
2653 static const unsigned int msiof3_txd_a_mux[] = {
2654 MSIOF3_TXD_A_MARK,
2655 };
2656 static const unsigned int msiof3_rxd_a_pins[] = {
2657 /* RXD */
2658 RCAR_GP_PIN(0, 2),
2659 };
2660 static const unsigned int msiof3_rxd_a_mux[] = {
2661 MSIOF3_RXD_A_MARK,
2662 };
2663 static const unsigned int msiof3_clk_b_pins[] = {
2664 /* SCK */
2665 RCAR_GP_PIN(1, 2),
2666 };
2667 static const unsigned int msiof3_clk_b_mux[] = {
2668 MSIOF3_SCK_B_MARK,
2669 };
2670 static const unsigned int msiof3_sync_b_pins[] = {
2671 /* SYNC */
2672 RCAR_GP_PIN(1, 0),
2673 };
2674 static const unsigned int msiof3_sync_b_mux[] = {
2675 MSIOF3_SYNC_B_MARK,
2676 };
2677 static const unsigned int msiof3_ss1_b_pins[] = {
2678 /* SS1 */
2679 RCAR_GP_PIN(1, 4),
2680 };
2681 static const unsigned int msiof3_ss1_b_mux[] = {
2682 MSIOF3_SS1_B_MARK,
2683 };
2684 static const unsigned int msiof3_ss2_b_pins[] = {
2685 /* SS2 */
2686 RCAR_GP_PIN(1, 5),
2687 };
2688 static const unsigned int msiof3_ss2_b_mux[] = {
2689 MSIOF3_SS2_B_MARK,
2690 };
2691 static const unsigned int msiof3_txd_b_pins[] = {
2692 /* TXD */
2693 RCAR_GP_PIN(1, 1),
2694 };
2695 static const unsigned int msiof3_txd_b_mux[] = {
2696 MSIOF3_TXD_B_MARK,
2697 };
2698 static const unsigned int msiof3_rxd_b_pins[] = {
2699 /* RXD */
2700 RCAR_GP_PIN(1, 3),
2701 };
2702 static const unsigned int msiof3_rxd_b_mux[] = {
2703 MSIOF3_RXD_B_MARK,
2704 };
2705 static const unsigned int msiof3_clk_c_pins[] = {
2706 /* SCK */
2707 RCAR_GP_PIN(1, 12),
2708 };
2709 static const unsigned int msiof3_clk_c_mux[] = {
2710 MSIOF3_SCK_C_MARK,
2711 };
2712 static const unsigned int msiof3_sync_c_pins[] = {
2713 /* SYNC */
2714 RCAR_GP_PIN(1, 13),
2715 };
2716 static const unsigned int msiof3_sync_c_mux[] = {
2717 MSIOF3_SYNC_C_MARK,
2718 };
2719 static const unsigned int msiof3_txd_c_pins[] = {
2720 /* TXD */
2721 RCAR_GP_PIN(1, 15),
2722 };
2723 static const unsigned int msiof3_txd_c_mux[] = {
2724 MSIOF3_TXD_C_MARK,
2725 };
2726 static const unsigned int msiof3_rxd_c_pins[] = {
2727 /* RXD */
2728 RCAR_GP_PIN(1, 14),
2729 };
2730 static const unsigned int msiof3_rxd_c_mux[] = {
2731 MSIOF3_RXD_C_MARK,
2732 };
2733 static const unsigned int msiof3_clk_d_pins[] = {
2734 /* SCK */
2735 RCAR_GP_PIN(1, 22),
2736 };
2737 static const unsigned int msiof3_clk_d_mux[] = {
2738 MSIOF3_SCK_D_MARK,
2739 };
2740 static const unsigned int msiof3_sync_d_pins[] = {
2741 /* SYNC */
2742 RCAR_GP_PIN(1, 23),
2743 };
2744 static const unsigned int msiof3_sync_d_mux[] = {
2745 MSIOF3_SYNC_D_MARK,
2746 };
2747 static const unsigned int msiof3_ss1_d_pins[] = {
2748 /* SS1 */
2749 RCAR_GP_PIN(1, 26),
2750 };
2751 static const unsigned int msiof3_ss1_d_mux[] = {
2752 MSIOF3_SS1_D_MARK,
2753 };
2754 static const unsigned int msiof3_txd_d_pins[] = {
2755 /* TXD */
2756 RCAR_GP_PIN(1, 25),
2757 };
2758 static const unsigned int msiof3_txd_d_mux[] = {
2759 MSIOF3_TXD_D_MARK,
2760 };
2761 static const unsigned int msiof3_rxd_d_pins[] = {
2762 /* RXD */
2763 RCAR_GP_PIN(1, 24),
2764 };
2765 static const unsigned int msiof3_rxd_d_mux[] = {
2766 MSIOF3_RXD_D_MARK,
2767 };
2768 static const unsigned int msiof3_clk_e_pins[] = {
2769 /* SCK */
2770 RCAR_GP_PIN(2, 3),
2771 };
2772 static const unsigned int msiof3_clk_e_mux[] = {
2773 MSIOF3_SCK_E_MARK,
2774 };
2775 static const unsigned int msiof3_sync_e_pins[] = {
2776 /* SYNC */
2777 RCAR_GP_PIN(2, 2),
2778 };
2779 static const unsigned int msiof3_sync_e_mux[] = {
2780 MSIOF3_SYNC_E_MARK,
2781 };
2782 static const unsigned int msiof3_ss1_e_pins[] = {
2783 /* SS1 */
2784 RCAR_GP_PIN(2, 1),
2785 };
2786 static const unsigned int msiof3_ss1_e_mux[] = {
2787 MSIOF3_SS1_E_MARK,
2788 };
2789 static const unsigned int msiof3_ss2_e_pins[] = {
2790 /* SS2 */
2791 RCAR_GP_PIN(2, 0),
2792 };
2793 static const unsigned int msiof3_ss2_e_mux[] = {
2794 MSIOF3_SS2_E_MARK,
2795 };
2796 static const unsigned int msiof3_txd_e_pins[] = {
2797 /* TXD */
2798 RCAR_GP_PIN(2, 5),
2799 };
2800 static const unsigned int msiof3_txd_e_mux[] = {
2801 MSIOF3_TXD_E_MARK,
2802 };
2803 static const unsigned int msiof3_rxd_e_pins[] = {
2804 /* RXD */
2805 RCAR_GP_PIN(2, 4),
2806 };
2807 static const unsigned int msiof3_rxd_e_mux[] = {
2808 MSIOF3_RXD_E_MARK,
2809 };
2810
2811 /* - PWM0 --------------------------------------------------------------------*/
2812 static const unsigned int pwm0_pins[] = {
2813 /* PWM */
2814 RCAR_GP_PIN(2, 6),
2815 };
2816 static const unsigned int pwm0_mux[] = {
2817 PWM0_MARK,
2818 };
2819 /* - PWM1 --------------------------------------------------------------------*/
2820 static const unsigned int pwm1_a_pins[] = {
2821 /* PWM */
2822 RCAR_GP_PIN(2, 7),
2823 };
2824 static const unsigned int pwm1_a_mux[] = {
2825 PWM1_A_MARK,
2826 };
2827 static const unsigned int pwm1_b_pins[] = {
2828 /* PWM */
2829 RCAR_GP_PIN(1, 8),
2830 };
2831 static const unsigned int pwm1_b_mux[] = {
2832 PWM1_B_MARK,
2833 };
2834 /* - PWM2 --------------------------------------------------------------------*/
2835 static const unsigned int pwm2_a_pins[] = {
2836 /* PWM */
2837 RCAR_GP_PIN(2, 8),
2838 };
2839 static const unsigned int pwm2_a_mux[] = {
2840 PWM2_A_MARK,
2841 };
2842 static const unsigned int pwm2_b_pins[] = {
2843 /* PWM */
2844 RCAR_GP_PIN(1, 11),
2845 };
2846 static const unsigned int pwm2_b_mux[] = {
2847 PWM2_B_MARK,
2848 };
2849 /* - PWM3 --------------------------------------------------------------------*/
2850 static const unsigned int pwm3_a_pins[] = {
2851 /* PWM */
2852 RCAR_GP_PIN(1, 0),
2853 };
2854 static const unsigned int pwm3_a_mux[] = {
2855 PWM3_A_MARK,
2856 };
2857 static const unsigned int pwm3_b_pins[] = {
2858 /* PWM */
2859 RCAR_GP_PIN(2, 2),
2860 };
2861 static const unsigned int pwm3_b_mux[] = {
2862 PWM3_B_MARK,
2863 };
2864 /* - PWM4 --------------------------------------------------------------------*/
2865 static const unsigned int pwm4_a_pins[] = {
2866 /* PWM */
2867 RCAR_GP_PIN(1, 1),
2868 };
2869 static const unsigned int pwm4_a_mux[] = {
2870 PWM4_A_MARK,
2871 };
2872 static const unsigned int pwm4_b_pins[] = {
2873 /* PWM */
2874 RCAR_GP_PIN(2, 3),
2875 };
2876 static const unsigned int pwm4_b_mux[] = {
2877 PWM4_B_MARK,
2878 };
2879 /* - PWM5 --------------------------------------------------------------------*/
2880 static const unsigned int pwm5_a_pins[] = {
2881 /* PWM */
2882 RCAR_GP_PIN(1, 2),
2883 };
2884 static const unsigned int pwm5_a_mux[] = {
2885 PWM5_A_MARK,
2886 };
2887 static const unsigned int pwm5_b_pins[] = {
2888 /* PWM */
2889 RCAR_GP_PIN(2, 4),
2890 };
2891 static const unsigned int pwm5_b_mux[] = {
2892 PWM5_B_MARK,
2893 };
2894 /* - PWM6 --------------------------------------------------------------------*/
2895 static const unsigned int pwm6_a_pins[] = {
2896 /* PWM */
2897 RCAR_GP_PIN(1, 3),
2898 };
2899 static const unsigned int pwm6_a_mux[] = {
2900 PWM6_A_MARK,
2901 };
2902 static const unsigned int pwm6_b_pins[] = {
2903 /* PWM */
2904 RCAR_GP_PIN(2, 5),
2905 };
2906 static const unsigned int pwm6_b_mux[] = {
2907 PWM6_B_MARK,
2908 };
2909
2910 /* - SCIF0 ------------------------------------------------------------------ */
2911 static const unsigned int scif0_data_pins[] = {
2912 /* RX, TX */
2913 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2914 };
2915 static const unsigned int scif0_data_mux[] = {
2916 RX0_MARK, TX0_MARK,
2917 };
2918 static const unsigned int scif0_clk_pins[] = {
2919 /* SCK */
2920 RCAR_GP_PIN(5, 0),
2921 };
2922 static const unsigned int scif0_clk_mux[] = {
2923 SCK0_MARK,
2924 };
2925 static const unsigned int scif0_ctrl_pins[] = {
2926 /* RTS, CTS */
2927 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2928 };
2929 static const unsigned int scif0_ctrl_mux[] = {
2930 RTS0_N_MARK, CTS0_N_MARK,
2931 };
2932 /* - SCIF1 ------------------------------------------------------------------ */
2933 static const unsigned int scif1_data_a_pins[] = {
2934 /* RX, TX */
2935 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2936 };
2937 static const unsigned int scif1_data_a_mux[] = {
2938 RX1_A_MARK, TX1_A_MARK,
2939 };
2940 static const unsigned int scif1_clk_pins[] = {
2941 /* SCK */
2942 RCAR_GP_PIN(6, 21),
2943 };
2944 static const unsigned int scif1_clk_mux[] = {
2945 SCK1_MARK,
2946 };
2947 static const unsigned int scif1_ctrl_pins[] = {
2948 /* RTS, CTS */
2949 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2950 };
2951 static const unsigned int scif1_ctrl_mux[] = {
2952 RTS1_N_MARK, CTS1_N_MARK,
2953 };
2954 static const unsigned int scif1_data_b_pins[] = {
2955 /* RX, TX */
2956 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2957 };
2958 static const unsigned int scif1_data_b_mux[] = {
2959 RX1_B_MARK, TX1_B_MARK,
2960 };
2961 /* - SCIF2 ------------------------------------------------------------------ */
2962 static const unsigned int scif2_data_a_pins[] = {
2963 /* RX, TX */
2964 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2965 };
2966 static const unsigned int scif2_data_a_mux[] = {
2967 RX2_A_MARK, TX2_A_MARK,
2968 };
2969 static const unsigned int scif2_clk_pins[] = {
2970 /* SCK */
2971 RCAR_GP_PIN(5, 9),
2972 };
2973 static const unsigned int scif2_clk_mux[] = {
2974 SCK2_MARK,
2975 };
2976 static const unsigned int scif2_data_b_pins[] = {
2977 /* RX, TX */
2978 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2979 };
2980 static const unsigned int scif2_data_b_mux[] = {
2981 RX2_B_MARK, TX2_B_MARK,
2982 };
2983 /* - SCIF3 ------------------------------------------------------------------ */
2984 static const unsigned int scif3_data_a_pins[] = {
2985 /* RX, TX */
2986 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2987 };
2988 static const unsigned int scif3_data_a_mux[] = {
2989 RX3_A_MARK, TX3_A_MARK,
2990 };
2991 static const unsigned int scif3_clk_pins[] = {
2992 /* SCK */
2993 RCAR_GP_PIN(1, 22),
2994 };
2995 static const unsigned int scif3_clk_mux[] = {
2996 SCK3_MARK,
2997 };
2998 static const unsigned int scif3_ctrl_pins[] = {
2999 /* RTS, CTS */
3000 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3001 };
3002 static const unsigned int scif3_ctrl_mux[] = {
3003 RTS3_N_MARK, CTS3_N_MARK,
3004 };
3005 static const unsigned int scif3_data_b_pins[] = {
3006 /* RX, TX */
3007 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3008 };
3009 static const unsigned int scif3_data_b_mux[] = {
3010 RX3_B_MARK, TX3_B_MARK,
3011 };
3012 /* - SCIF4 ------------------------------------------------------------------ */
3013 static const unsigned int scif4_data_a_pins[] = {
3014 /* RX, TX */
3015 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3016 };
3017 static const unsigned int scif4_data_a_mux[] = {
3018 RX4_A_MARK, TX4_A_MARK,
3019 };
3020 static const unsigned int scif4_clk_a_pins[] = {
3021 /* SCK */
3022 RCAR_GP_PIN(2, 10),
3023 };
3024 static const unsigned int scif4_clk_a_mux[] = {
3025 SCK4_A_MARK,
3026 };
3027 static const unsigned int scif4_ctrl_a_pins[] = {
3028 /* RTS, CTS */
3029 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3030 };
3031 static const unsigned int scif4_ctrl_a_mux[] = {
3032 RTS4_N_A_MARK, CTS4_N_A_MARK,
3033 };
3034 static const unsigned int scif4_data_b_pins[] = {
3035 /* RX, TX */
3036 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3037 };
3038 static const unsigned int scif4_data_b_mux[] = {
3039 RX4_B_MARK, TX4_B_MARK,
3040 };
3041 static const unsigned int scif4_clk_b_pins[] = {
3042 /* SCK */
3043 RCAR_GP_PIN(1, 5),
3044 };
3045 static const unsigned int scif4_clk_b_mux[] = {
3046 SCK4_B_MARK,
3047 };
3048 static const unsigned int scif4_ctrl_b_pins[] = {
3049 /* RTS, CTS */
3050 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3051 };
3052 static const unsigned int scif4_ctrl_b_mux[] = {
3053 RTS4_N_B_MARK, CTS4_N_B_MARK,
3054 };
3055 static const unsigned int scif4_data_c_pins[] = {
3056 /* RX, TX */
3057 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3058 };
3059 static const unsigned int scif4_data_c_mux[] = {
3060 RX4_C_MARK, TX4_C_MARK,
3061 };
3062 static const unsigned int scif4_clk_c_pins[] = {
3063 /* SCK */
3064 RCAR_GP_PIN(0, 8),
3065 };
3066 static const unsigned int scif4_clk_c_mux[] = {
3067 SCK4_C_MARK,
3068 };
3069 static const unsigned int scif4_ctrl_c_pins[] = {
3070 /* RTS, CTS */
3071 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3072 };
3073 static const unsigned int scif4_ctrl_c_mux[] = {
3074 RTS4_N_C_MARK, CTS4_N_C_MARK,
3075 };
3076 /* - SCIF5 ------------------------------------------------------------------ */
3077 static const unsigned int scif5_data_a_pins[] = {
3078 /* RX, TX */
3079 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3080 };
3081 static const unsigned int scif5_data_a_mux[] = {
3082 RX5_A_MARK, TX5_A_MARK,
3083 };
3084 static const unsigned int scif5_clk_a_pins[] = {
3085 /* SCK */
3086 RCAR_GP_PIN(6, 21),
3087 };
3088 static const unsigned int scif5_clk_a_mux[] = {
3089 SCK5_A_MARK,
3090 };
3091 static const unsigned int scif5_data_b_pins[] = {
3092 /* RX, TX */
3093 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3094 };
3095 static const unsigned int scif5_data_b_mux[] = {
3096 RX5_B_MARK, TX5_B_MARK,
3097 };
3098 static const unsigned int scif5_clk_b_pins[] = {
3099 /* SCK */
3100 RCAR_GP_PIN(5, 0),
3101 };
3102 static const unsigned int scif5_clk_b_mux[] = {
3103 SCK5_B_MARK,
3104 };
3105 /* - SCIF Clock ------------------------------------------------------------- */
3106 static const unsigned int scif_clk_a_pins[] = {
3107 /* SCIF_CLK */
3108 RCAR_GP_PIN(6, 23),
3109 };
3110 static const unsigned int scif_clk_a_mux[] = {
3111 SCIF_CLK_A_MARK,
3112 };
3113 static const unsigned int scif_clk_b_pins[] = {
3114 /* SCIF_CLK */
3115 RCAR_GP_PIN(5, 9),
3116 };
3117 static const unsigned int scif_clk_b_mux[] = {
3118 SCIF_CLK_B_MARK,
3119 };
3120
3121 /* - SDHI0 ------------------------------------------------------------------ */
3122 static const unsigned int sdhi0_data1_pins[] = {
3123 /* D0 */
3124 RCAR_GP_PIN(3, 2),
3125 };
3126
3127 static const unsigned int sdhi0_data1_mux[] = {
3128 SD0_DAT0_MARK,
3129 };
3130
3131 static const unsigned int sdhi0_data4_pins[] = {
3132 /* D[0:3] */
3133 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3134 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3135 };
3136
3137 static const unsigned int sdhi0_data4_mux[] = {
3138 SD0_DAT0_MARK, SD0_DAT1_MARK,
3139 SD0_DAT2_MARK, SD0_DAT3_MARK,
3140 };
3141
3142 static const unsigned int sdhi0_ctrl_pins[] = {
3143 /* CLK, CMD */
3144 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3145 };
3146
3147 static const unsigned int sdhi0_ctrl_mux[] = {
3148 SD0_CLK_MARK, SD0_CMD_MARK,
3149 };
3150
3151 static const unsigned int sdhi0_cd_pins[] = {
3152 /* CD */
3153 RCAR_GP_PIN(3, 12),
3154 };
3155
3156 static const unsigned int sdhi0_cd_mux[] = {
3157 SD0_CD_MARK,
3158 };
3159
3160 static const unsigned int sdhi0_wp_pins[] = {
3161 /* WP */
3162 RCAR_GP_PIN(3, 13),
3163 };
3164
3165 static const unsigned int sdhi0_wp_mux[] = {
3166 SD0_WP_MARK,
3167 };
3168
3169 /* - SDHI1 ------------------------------------------------------------------ */
3170 static const unsigned int sdhi1_data1_pins[] = {
3171 /* D0 */
3172 RCAR_GP_PIN(3, 8),
3173 };
3174
3175 static const unsigned int sdhi1_data1_mux[] = {
3176 SD1_DAT0_MARK,
3177 };
3178
3179 static const unsigned int sdhi1_data4_pins[] = {
3180 /* D[0:3] */
3181 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3182 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3183 };
3184
3185 static const unsigned int sdhi1_data4_mux[] = {
3186 SD1_DAT0_MARK, SD1_DAT1_MARK,
3187 SD1_DAT2_MARK, SD1_DAT3_MARK,
3188 };
3189
3190 static const unsigned int sdhi1_ctrl_pins[] = {
3191 /* CLK, CMD */
3192 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3193 };
3194
3195 static const unsigned int sdhi1_ctrl_mux[] = {
3196 SD1_CLK_MARK, SD1_CMD_MARK,
3197 };
3198
3199 static const unsigned int sdhi1_cd_pins[] = {
3200 /* CD */
3201 RCAR_GP_PIN(3, 14),
3202 };
3203
3204 static const unsigned int sdhi1_cd_mux[] = {
3205 SD1_CD_MARK,
3206 };
3207
3208 static const unsigned int sdhi1_wp_pins[] = {
3209 /* WP */
3210 RCAR_GP_PIN(3, 15),
3211 };
3212
3213 static const unsigned int sdhi1_wp_mux[] = {
3214 SD1_WP_MARK,
3215 };
3216
3217 /* - SDHI2 ------------------------------------------------------------------ */
3218 static const unsigned int sdhi2_data1_pins[] = {
3219 /* D0 */
3220 RCAR_GP_PIN(4, 2),
3221 };
3222
3223 static const unsigned int sdhi2_data1_mux[] = {
3224 SD2_DAT0_MARK,
3225 };
3226
3227 static const unsigned int sdhi2_data4_pins[] = {
3228 /* D[0:3] */
3229 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3230 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3231 };
3232
3233 static const unsigned int sdhi2_data4_mux[] = {
3234 SD2_DAT0_MARK, SD2_DAT1_MARK,
3235 SD2_DAT2_MARK, SD2_DAT3_MARK,
3236 };
3237
3238 static const unsigned int sdhi2_data8_pins[] = {
3239 /* D[0:7] */
3240 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3241 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3242 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3243 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3244 };
3245
3246 static const unsigned int sdhi2_data8_mux[] = {
3247 SD2_DAT0_MARK, SD2_DAT1_MARK,
3248 SD2_DAT2_MARK, SD2_DAT3_MARK,
3249 SD2_DAT4_MARK, SD2_DAT5_MARK,
3250 SD2_DAT6_MARK, SD2_DAT7_MARK,
3251 };
3252
3253 static const unsigned int sdhi2_ctrl_pins[] = {
3254 /* CLK, CMD */
3255 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3256 };
3257
3258 static const unsigned int sdhi2_ctrl_mux[] = {
3259 SD2_CLK_MARK, SD2_CMD_MARK,
3260 };
3261
3262 static const unsigned int sdhi2_cd_a_pins[] = {
3263 /* CD */
3264 RCAR_GP_PIN(4, 13),
3265 };
3266
3267 static const unsigned int sdhi2_cd_a_mux[] = {
3268 SD2_CD_A_MARK,
3269 };
3270
3271 static const unsigned int sdhi2_cd_b_pins[] = {
3272 /* CD */
3273 RCAR_GP_PIN(5, 10),
3274 };
3275
3276 static const unsigned int sdhi2_cd_b_mux[] = {
3277 SD2_CD_B_MARK,
3278 };
3279
3280 static const unsigned int sdhi2_wp_a_pins[] = {
3281 /* WP */
3282 RCAR_GP_PIN(4, 14),
3283 };
3284
3285 static const unsigned int sdhi2_wp_a_mux[] = {
3286 SD2_WP_A_MARK,
3287 };
3288
3289 static const unsigned int sdhi2_wp_b_pins[] = {
3290 /* WP */
3291 RCAR_GP_PIN(5, 11),
3292 };
3293
3294 static const unsigned int sdhi2_wp_b_mux[] = {
3295 SD2_WP_B_MARK,
3296 };
3297
3298 static const unsigned int sdhi2_ds_pins[] = {
3299 /* DS */
3300 RCAR_GP_PIN(4, 6),
3301 };
3302
3303 static const unsigned int sdhi2_ds_mux[] = {
3304 SD2_DS_MARK,
3305 };
3306
3307 /* - SDHI3 ------------------------------------------------------------------ */
3308 static const unsigned int sdhi3_data1_pins[] = {
3309 /* D0 */
3310 RCAR_GP_PIN(4, 9),
3311 };
3312
3313 static const unsigned int sdhi3_data1_mux[] = {
3314 SD3_DAT0_MARK,
3315 };
3316
3317 static const unsigned int sdhi3_data4_pins[] = {
3318 /* D[0:3] */
3319 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3320 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3321 };
3322
3323 static const unsigned int sdhi3_data4_mux[] = {
3324 SD3_DAT0_MARK, SD3_DAT1_MARK,
3325 SD3_DAT2_MARK, SD3_DAT3_MARK,
3326 };
3327
3328 static const unsigned int sdhi3_data8_pins[] = {
3329 /* D[0:7] */
3330 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3331 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3332 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3333 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3334 };
3335
3336 static const unsigned int sdhi3_data8_mux[] = {
3337 SD3_DAT0_MARK, SD3_DAT1_MARK,
3338 SD3_DAT2_MARK, SD3_DAT3_MARK,
3339 SD3_DAT4_MARK, SD3_DAT5_MARK,
3340 SD3_DAT6_MARK, SD3_DAT7_MARK,
3341 };
3342
3343 static const unsigned int sdhi3_ctrl_pins[] = {
3344 /* CLK, CMD */
3345 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3346 };
3347
3348 static const unsigned int sdhi3_ctrl_mux[] = {
3349 SD3_CLK_MARK, SD3_CMD_MARK,
3350 };
3351
3352 static const unsigned int sdhi3_cd_pins[] = {
3353 /* CD */
3354 RCAR_GP_PIN(4, 15),
3355 };
3356
3357 static const unsigned int sdhi3_cd_mux[] = {
3358 SD3_CD_MARK,
3359 };
3360
3361 static const unsigned int sdhi3_wp_pins[] = {
3362 /* WP */
3363 RCAR_GP_PIN(4, 16),
3364 };
3365
3366 static const unsigned int sdhi3_wp_mux[] = {
3367 SD3_WP_MARK,
3368 };
3369
3370 static const unsigned int sdhi3_ds_pins[] = {
3371 /* DS */
3372 RCAR_GP_PIN(4, 17),
3373 };
3374
3375 static const unsigned int sdhi3_ds_mux[] = {
3376 SD3_DS_MARK,
3377 };
3378
3379 /* - USB0 ------------------------------------------------------------------- */
3380 static const unsigned int usb0_pins[] = {
3381 /* PWEN, OVC */
3382 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3383 };
3384
3385 static const unsigned int usb0_mux[] = {
3386 USB0_PWEN_MARK, USB0_OVC_MARK,
3387 };
3388
3389 /* - USB1 ------------------------------------------------------------------- */
3390 static const unsigned int usb1_pins[] = {
3391 /* PWEN, OVC */
3392 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3393 };
3394
3395 static const unsigned int usb1_mux[] = {
3396 USB1_PWEN_MARK, USB1_OVC_MARK,
3397 };
3398
3399 /* - USB30 ------------------------------------------------------------------ */
3400 static const unsigned int usb30_pins[] = {
3401 /* PWEN, OVC */
3402 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3403 };
3404
3405 static const unsigned int usb30_mux[] = {
3406 USB30_PWEN_MARK, USB30_OVC_MARK,
3407 };
3408
3409 static const struct sh_pfc_pin_group pinmux_groups[] = {
3410 SH_PFC_PIN_GROUP(avb_link),
3411 SH_PFC_PIN_GROUP(avb_magic),
3412 SH_PFC_PIN_GROUP(avb_phy_int),
3413 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
3414 SH_PFC_PIN_GROUP(avb_mdio),
3415 SH_PFC_PIN_GROUP(avb_mii),
3416 SH_PFC_PIN_GROUP(avb_avtp_pps),
3417 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3418 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3419 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3420 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3421 SH_PFC_PIN_GROUP(du_rgb666),
3422 SH_PFC_PIN_GROUP(du_rgb888),
3423 SH_PFC_PIN_GROUP(du_clk_out_0),
3424 SH_PFC_PIN_GROUP(du_clk_out_1),
3425 SH_PFC_PIN_GROUP(du_sync),
3426 SH_PFC_PIN_GROUP(du_oddf),
3427 SH_PFC_PIN_GROUP(du_cde),
3428 SH_PFC_PIN_GROUP(du_disp),
3429 SH_PFC_PIN_GROUP(hscif0_data),
3430 SH_PFC_PIN_GROUP(hscif0_clk),
3431 SH_PFC_PIN_GROUP(hscif0_ctrl),
3432 SH_PFC_PIN_GROUP(hscif1_data_a),
3433 SH_PFC_PIN_GROUP(hscif1_clk_a),
3434 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3435 SH_PFC_PIN_GROUP(hscif1_data_b),
3436 SH_PFC_PIN_GROUP(hscif1_clk_b),
3437 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3438 SH_PFC_PIN_GROUP(hscif2_data_a),
3439 SH_PFC_PIN_GROUP(hscif2_clk_a),
3440 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3441 SH_PFC_PIN_GROUP(hscif2_data_b),
3442 SH_PFC_PIN_GROUP(hscif2_clk_b),
3443 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3444 SH_PFC_PIN_GROUP(hscif2_data_c),
3445 SH_PFC_PIN_GROUP(hscif2_clk_c),
3446 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
3447 SH_PFC_PIN_GROUP(hscif3_data_a),
3448 SH_PFC_PIN_GROUP(hscif3_clk),
3449 SH_PFC_PIN_GROUP(hscif3_ctrl),
3450 SH_PFC_PIN_GROUP(hscif3_data_b),
3451 SH_PFC_PIN_GROUP(hscif3_data_c),
3452 SH_PFC_PIN_GROUP(hscif3_data_d),
3453 SH_PFC_PIN_GROUP(hscif4_data_a),
3454 SH_PFC_PIN_GROUP(hscif4_clk),
3455 SH_PFC_PIN_GROUP(hscif4_ctrl),
3456 SH_PFC_PIN_GROUP(hscif4_data_b),
3457 SH_PFC_PIN_GROUP(i2c1_a),
3458 SH_PFC_PIN_GROUP(i2c1_b),
3459 SH_PFC_PIN_GROUP(i2c2_a),
3460 SH_PFC_PIN_GROUP(i2c2_b),
3461 SH_PFC_PIN_GROUP(i2c6_a),
3462 SH_PFC_PIN_GROUP(i2c6_b),
3463 SH_PFC_PIN_GROUP(i2c6_c),
3464 SH_PFC_PIN_GROUP(intc_ex_irq0),
3465 SH_PFC_PIN_GROUP(intc_ex_irq1),
3466 SH_PFC_PIN_GROUP(intc_ex_irq2),
3467 SH_PFC_PIN_GROUP(intc_ex_irq3),
3468 SH_PFC_PIN_GROUP(intc_ex_irq4),
3469 SH_PFC_PIN_GROUP(intc_ex_irq5),
3470 SH_PFC_PIN_GROUP(msiof0_clk),
3471 SH_PFC_PIN_GROUP(msiof0_sync),
3472 SH_PFC_PIN_GROUP(msiof0_ss1),
3473 SH_PFC_PIN_GROUP(msiof0_ss2),
3474 SH_PFC_PIN_GROUP(msiof0_txd),
3475 SH_PFC_PIN_GROUP(msiof0_rxd),
3476 SH_PFC_PIN_GROUP(msiof1_clk_a),
3477 SH_PFC_PIN_GROUP(msiof1_sync_a),
3478 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3479 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3480 SH_PFC_PIN_GROUP(msiof1_txd_a),
3481 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3482 SH_PFC_PIN_GROUP(msiof1_clk_b),
3483 SH_PFC_PIN_GROUP(msiof1_sync_b),
3484 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3485 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3486 SH_PFC_PIN_GROUP(msiof1_txd_b),
3487 SH_PFC_PIN_GROUP(msiof1_rxd_b),
3488 SH_PFC_PIN_GROUP(msiof1_clk_c),
3489 SH_PFC_PIN_GROUP(msiof1_sync_c),
3490 SH_PFC_PIN_GROUP(msiof1_ss1_c),
3491 SH_PFC_PIN_GROUP(msiof1_ss2_c),
3492 SH_PFC_PIN_GROUP(msiof1_txd_c),
3493 SH_PFC_PIN_GROUP(msiof1_rxd_c),
3494 SH_PFC_PIN_GROUP(msiof1_clk_d),
3495 SH_PFC_PIN_GROUP(msiof1_sync_d),
3496 SH_PFC_PIN_GROUP(msiof1_ss1_d),
3497 SH_PFC_PIN_GROUP(msiof1_ss2_d),
3498 SH_PFC_PIN_GROUP(msiof1_txd_d),
3499 SH_PFC_PIN_GROUP(msiof1_rxd_d),
3500 SH_PFC_PIN_GROUP(msiof1_clk_e),
3501 SH_PFC_PIN_GROUP(msiof1_sync_e),
3502 SH_PFC_PIN_GROUP(msiof1_ss1_e),
3503 SH_PFC_PIN_GROUP(msiof1_ss2_e),
3504 SH_PFC_PIN_GROUP(msiof1_txd_e),
3505 SH_PFC_PIN_GROUP(msiof1_rxd_e),
3506 SH_PFC_PIN_GROUP(msiof1_clk_f),
3507 SH_PFC_PIN_GROUP(msiof1_sync_f),
3508 SH_PFC_PIN_GROUP(msiof1_ss1_f),
3509 SH_PFC_PIN_GROUP(msiof1_ss2_f),
3510 SH_PFC_PIN_GROUP(msiof1_txd_f),
3511 SH_PFC_PIN_GROUP(msiof1_rxd_f),
3512 SH_PFC_PIN_GROUP(msiof1_clk_g),
3513 SH_PFC_PIN_GROUP(msiof1_sync_g),
3514 SH_PFC_PIN_GROUP(msiof1_ss1_g),
3515 SH_PFC_PIN_GROUP(msiof1_ss2_g),
3516 SH_PFC_PIN_GROUP(msiof1_txd_g),
3517 SH_PFC_PIN_GROUP(msiof1_rxd_g),
3518 SH_PFC_PIN_GROUP(msiof2_clk_a),
3519 SH_PFC_PIN_GROUP(msiof2_sync_a),
3520 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3521 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3522 SH_PFC_PIN_GROUP(msiof2_txd_a),
3523 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3524 SH_PFC_PIN_GROUP(msiof2_clk_b),
3525 SH_PFC_PIN_GROUP(msiof2_sync_b),
3526 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3527 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3528 SH_PFC_PIN_GROUP(msiof2_txd_b),
3529 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3530 SH_PFC_PIN_GROUP(msiof2_clk_c),
3531 SH_PFC_PIN_GROUP(msiof2_sync_c),
3532 SH_PFC_PIN_GROUP(msiof2_ss1_c),
3533 SH_PFC_PIN_GROUP(msiof2_ss2_c),
3534 SH_PFC_PIN_GROUP(msiof2_txd_c),
3535 SH_PFC_PIN_GROUP(msiof2_rxd_c),
3536 SH_PFC_PIN_GROUP(msiof2_clk_d),
3537 SH_PFC_PIN_GROUP(msiof2_sync_d),
3538 SH_PFC_PIN_GROUP(msiof2_ss1_d),
3539 SH_PFC_PIN_GROUP(msiof2_ss2_d),
3540 SH_PFC_PIN_GROUP(msiof2_txd_d),
3541 SH_PFC_PIN_GROUP(msiof2_rxd_d),
3542 SH_PFC_PIN_GROUP(msiof3_clk_a),
3543 SH_PFC_PIN_GROUP(msiof3_sync_a),
3544 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3545 SH_PFC_PIN_GROUP(msiof3_ss2_a),
3546 SH_PFC_PIN_GROUP(msiof3_txd_a),
3547 SH_PFC_PIN_GROUP(msiof3_rxd_a),
3548 SH_PFC_PIN_GROUP(msiof3_clk_b),
3549 SH_PFC_PIN_GROUP(msiof3_sync_b),
3550 SH_PFC_PIN_GROUP(msiof3_ss1_b),
3551 SH_PFC_PIN_GROUP(msiof3_ss2_b),
3552 SH_PFC_PIN_GROUP(msiof3_txd_b),
3553 SH_PFC_PIN_GROUP(msiof3_rxd_b),
3554 SH_PFC_PIN_GROUP(msiof3_clk_c),
3555 SH_PFC_PIN_GROUP(msiof3_sync_c),
3556 SH_PFC_PIN_GROUP(msiof3_txd_c),
3557 SH_PFC_PIN_GROUP(msiof3_rxd_c),
3558 SH_PFC_PIN_GROUP(msiof3_clk_d),
3559 SH_PFC_PIN_GROUP(msiof3_sync_d),
3560 SH_PFC_PIN_GROUP(msiof3_ss1_d),
3561 SH_PFC_PIN_GROUP(msiof3_txd_d),
3562 SH_PFC_PIN_GROUP(msiof3_rxd_d),
3563 SH_PFC_PIN_GROUP(msiof3_clk_e),
3564 SH_PFC_PIN_GROUP(msiof3_sync_e),
3565 SH_PFC_PIN_GROUP(msiof3_ss1_e),
3566 SH_PFC_PIN_GROUP(msiof3_ss2_e),
3567 SH_PFC_PIN_GROUP(msiof3_txd_e),
3568 SH_PFC_PIN_GROUP(msiof3_rxd_e),
3569 SH_PFC_PIN_GROUP(pwm0),
3570 SH_PFC_PIN_GROUP(pwm1_a),
3571 SH_PFC_PIN_GROUP(pwm1_b),
3572 SH_PFC_PIN_GROUP(pwm2_a),
3573 SH_PFC_PIN_GROUP(pwm2_b),
3574 SH_PFC_PIN_GROUP(pwm3_a),
3575 SH_PFC_PIN_GROUP(pwm3_b),
3576 SH_PFC_PIN_GROUP(pwm4_a),
3577 SH_PFC_PIN_GROUP(pwm4_b),
3578 SH_PFC_PIN_GROUP(pwm5_a),
3579 SH_PFC_PIN_GROUP(pwm5_b),
3580 SH_PFC_PIN_GROUP(pwm6_a),
3581 SH_PFC_PIN_GROUP(pwm6_b),
3582 SH_PFC_PIN_GROUP(scif0_data),
3583 SH_PFC_PIN_GROUP(scif0_clk),
3584 SH_PFC_PIN_GROUP(scif0_ctrl),
3585 SH_PFC_PIN_GROUP(scif1_data_a),
3586 SH_PFC_PIN_GROUP(scif1_clk),
3587 SH_PFC_PIN_GROUP(scif1_ctrl),
3588 SH_PFC_PIN_GROUP(scif1_data_b),
3589 SH_PFC_PIN_GROUP(scif2_data_a),
3590 SH_PFC_PIN_GROUP(scif2_clk),
3591 SH_PFC_PIN_GROUP(scif2_data_b),
3592 SH_PFC_PIN_GROUP(scif3_data_a),
3593 SH_PFC_PIN_GROUP(scif3_clk),
3594 SH_PFC_PIN_GROUP(scif3_ctrl),
3595 SH_PFC_PIN_GROUP(scif3_data_b),
3596 SH_PFC_PIN_GROUP(scif4_data_a),
3597 SH_PFC_PIN_GROUP(scif4_clk_a),
3598 SH_PFC_PIN_GROUP(scif4_ctrl_a),
3599 SH_PFC_PIN_GROUP(scif4_data_b),
3600 SH_PFC_PIN_GROUP(scif4_clk_b),
3601 SH_PFC_PIN_GROUP(scif4_ctrl_b),
3602 SH_PFC_PIN_GROUP(scif4_data_c),
3603 SH_PFC_PIN_GROUP(scif4_clk_c),
3604 SH_PFC_PIN_GROUP(scif4_ctrl_c),
3605 SH_PFC_PIN_GROUP(scif5_data_a),
3606 SH_PFC_PIN_GROUP(scif5_clk_a),
3607 SH_PFC_PIN_GROUP(scif5_data_b),
3608 SH_PFC_PIN_GROUP(scif5_clk_b),
3609 SH_PFC_PIN_GROUP(scif_clk_a),
3610 SH_PFC_PIN_GROUP(scif_clk_b),
3611 SH_PFC_PIN_GROUP(sdhi0_data1),
3612 SH_PFC_PIN_GROUP(sdhi0_data4),
3613 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3614 SH_PFC_PIN_GROUP(sdhi0_cd),
3615 SH_PFC_PIN_GROUP(sdhi0_wp),
3616 SH_PFC_PIN_GROUP(sdhi1_data1),
3617 SH_PFC_PIN_GROUP(sdhi1_data4),
3618 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3619 SH_PFC_PIN_GROUP(sdhi1_cd),
3620 SH_PFC_PIN_GROUP(sdhi1_wp),
3621 SH_PFC_PIN_GROUP(sdhi2_data1),
3622 SH_PFC_PIN_GROUP(sdhi2_data4),
3623 SH_PFC_PIN_GROUP(sdhi2_data8),
3624 SH_PFC_PIN_GROUP(sdhi2_ctrl),
3625 SH_PFC_PIN_GROUP(sdhi2_cd_a),
3626 SH_PFC_PIN_GROUP(sdhi2_wp_a),
3627 SH_PFC_PIN_GROUP(sdhi2_cd_b),
3628 SH_PFC_PIN_GROUP(sdhi2_wp_b),
3629 SH_PFC_PIN_GROUP(sdhi2_ds),
3630 SH_PFC_PIN_GROUP(sdhi3_data1),
3631 SH_PFC_PIN_GROUP(sdhi3_data4),
3632 SH_PFC_PIN_GROUP(sdhi3_data8),
3633 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3634 SH_PFC_PIN_GROUP(sdhi3_cd),
3635 SH_PFC_PIN_GROUP(sdhi3_wp),
3636 SH_PFC_PIN_GROUP(sdhi3_ds),
3637 SH_PFC_PIN_GROUP(usb0),
3638 SH_PFC_PIN_GROUP(usb1),
3639 SH_PFC_PIN_GROUP(usb30),
3640 };
3641
3642 static const char * const avb_groups[] = {
3643 "avb_link",
3644 "avb_magic",
3645 "avb_phy_int",
3646 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
3647 "avb_mdio",
3648 "avb_mii",
3649 "avb_avtp_pps",
3650 "avb_avtp_match_a",
3651 "avb_avtp_capture_a",
3652 "avb_avtp_match_b",
3653 "avb_avtp_capture_b",
3654 };
3655
3656 static const char * const du_groups[] = {
3657 "du_rgb666",
3658 "du_rgb888",
3659 "du_clk_out_0",
3660 "du_clk_out_1",
3661 "du_sync",
3662 "du_oddf",
3663 "du_cde",
3664 "du_disp",
3665 };
3666
3667 static const char * const hscif0_groups[] = {
3668 "hscif0_data",
3669 "hscif0_clk",
3670 "hscif0_ctrl",
3671 };
3672
3673 static const char * const hscif1_groups[] = {
3674 "hscif1_data_a",
3675 "hscif1_clk_a",
3676 "hscif1_ctrl_a",
3677 "hscif1_data_b",
3678 "hscif1_clk_b",
3679 "hscif1_ctrl_b",
3680 };
3681
3682 static const char * const hscif2_groups[] = {
3683 "hscif2_data_a",
3684 "hscif2_clk_a",
3685 "hscif2_ctrl_a",
3686 "hscif2_data_b",
3687 "hscif2_clk_b",
3688 "hscif2_ctrl_b",
3689 "hscif2_data_c",
3690 "hscif2_clk_c",
3691 "hscif2_ctrl_c",
3692 };
3693
3694 static const char * const hscif3_groups[] = {
3695 "hscif3_data_a",
3696 "hscif3_clk",
3697 "hscif3_ctrl",
3698 "hscif3_data_b",
3699 "hscif3_data_c",
3700 "hscif3_data_d",
3701 };
3702
3703 static const char * const hscif4_groups[] = {
3704 "hscif4_data_a",
3705 "hscif4_clk",
3706 "hscif4_ctrl",
3707 "hscif4_data_b",
3708 };
3709
3710 static const char * const i2c1_groups[] = {
3711 "i2c1_a",
3712 "i2c1_b",
3713 };
3714
3715 static const char * const i2c2_groups[] = {
3716 "i2c2_a",
3717 "i2c2_b",
3718 };
3719
3720 static const char * const i2c6_groups[] = {
3721 "i2c6_a",
3722 "i2c6_b",
3723 "i2c6_c",
3724 };
3725
3726 static const char * const intc_ex_groups[] = {
3727 "intc_ex_irq0",
3728 "intc_ex_irq1",
3729 "intc_ex_irq2",
3730 "intc_ex_irq3",
3731 "intc_ex_irq4",
3732 "intc_ex_irq5",
3733 };
3734
3735 static const char * const msiof0_groups[] = {
3736 "msiof0_clk",
3737 "msiof0_sync",
3738 "msiof0_ss1",
3739 "msiof0_ss2",
3740 "msiof0_txd",
3741 "msiof0_rxd",
3742 };
3743
3744 static const char * const msiof1_groups[] = {
3745 "msiof1_clk_a",
3746 "msiof1_sync_a",
3747 "msiof1_ss1_a",
3748 "msiof1_ss2_a",
3749 "msiof1_txd_a",
3750 "msiof1_rxd_a",
3751 "msiof1_clk_b",
3752 "msiof1_sync_b",
3753 "msiof1_ss1_b",
3754 "msiof1_ss2_b",
3755 "msiof1_txd_b",
3756 "msiof1_rxd_b",
3757 "msiof1_clk_c",
3758 "msiof1_sync_c",
3759 "msiof1_ss1_c",
3760 "msiof1_ss2_c",
3761 "msiof1_txd_c",
3762 "msiof1_rxd_c",
3763 "msiof1_clk_d",
3764 "msiof1_sync_d",
3765 "msiof1_ss1_d",
3766 "msiof1_ss2_d",
3767 "msiof1_txd_d",
3768 "msiof1_rxd_d",
3769 "msiof1_clk_e",
3770 "msiof1_sync_e",
3771 "msiof1_ss1_e",
3772 "msiof1_ss2_e",
3773 "msiof1_txd_e",
3774 "msiof1_rxd_e",
3775 "msiof1_clk_f",
3776 "msiof1_sync_f",
3777 "msiof1_ss1_f",
3778 "msiof1_ss2_f",
3779 "msiof1_txd_f",
3780 "msiof1_rxd_f",
3781 "msiof1_clk_g",
3782 "msiof1_sync_g",
3783 "msiof1_ss1_g",
3784 "msiof1_ss2_g",
3785 "msiof1_txd_g",
3786 "msiof1_rxd_g",
3787 };
3788
3789 static const char * const msiof2_groups[] = {
3790 "msiof2_clk_a",
3791 "msiof2_sync_a",
3792 "msiof2_ss1_a",
3793 "msiof2_ss2_a",
3794 "msiof2_txd_a",
3795 "msiof2_rxd_a",
3796 "msiof2_clk_b",
3797 "msiof2_sync_b",
3798 "msiof2_ss1_b",
3799 "msiof2_ss2_b",
3800 "msiof2_txd_b",
3801 "msiof2_rxd_b",
3802 "msiof2_clk_c",
3803 "msiof2_sync_c",
3804 "msiof2_ss1_c",
3805 "msiof2_ss2_c",
3806 "msiof2_txd_c",
3807 "msiof2_rxd_c",
3808 "msiof2_clk_d",
3809 "msiof2_sync_d",
3810 "msiof2_ss1_d",
3811 "msiof2_ss2_d",
3812 "msiof2_txd_d",
3813 "msiof2_rxd_d",
3814 };
3815
3816 static const char * const msiof3_groups[] = {
3817 "msiof3_clk_a",
3818 "msiof3_sync_a",
3819 "msiof3_ss1_a",
3820 "msiof3_ss2_a",
3821 "msiof3_txd_a",
3822 "msiof3_rxd_a",
3823 "msiof3_clk_b",
3824 "msiof3_sync_b",
3825 "msiof3_ss1_b",
3826 "msiof3_ss2_b",
3827 "msiof3_txd_b",
3828 "msiof3_rxd_b",
3829 "msiof3_clk_c",
3830 "msiof3_sync_c",
3831 "msiof3_txd_c",
3832 "msiof3_rxd_c",
3833 "msiof3_clk_d",
3834 "msiof3_sync_d",
3835 "msiof3_ss1_d",
3836 "msiof3_txd_d",
3837 "msiof3_rxd_d",
3838 "msiof3_clk_e",
3839 "msiof3_sync_e",
3840 "msiof3_ss1_e",
3841 "msiof3_ss2_e",
3842 "msiof3_txd_e",
3843 "msiof3_rxd_e",
3844 };
3845
3846 static const char * const pwm0_groups[] = {
3847 "pwm0",
3848 };
3849
3850 static const char * const pwm1_groups[] = {
3851 "pwm1_a",
3852 "pwm1_b",
3853 };
3854
3855 static const char * const pwm2_groups[] = {
3856 "pwm2_a",
3857 "pwm2_b",
3858 };
3859
3860 static const char * const pwm3_groups[] = {
3861 "pwm3_a",
3862 "pwm3_b",
3863 };
3864
3865 static const char * const pwm4_groups[] = {
3866 "pwm4_a",
3867 "pwm4_b",
3868 };
3869
3870 static const char * const pwm5_groups[] = {
3871 "pwm5_a",
3872 "pwm5_b",
3873 };
3874
3875 static const char * const pwm6_groups[] = {
3876 "pwm6_a",
3877 "pwm6_b",
3878 };
3879
3880 static const char * const scif0_groups[] = {
3881 "scif0_data",
3882 "scif0_clk",
3883 "scif0_ctrl",
3884 };
3885
3886 static const char * const scif1_groups[] = {
3887 "scif1_data_a",
3888 "scif1_clk",
3889 "scif1_ctrl",
3890 "scif1_data_b",
3891 };
3892 static const char * const scif2_groups[] = {
3893 "scif2_data_a",
3894 "scif2_clk",
3895 "scif2_data_b",
3896 };
3897
3898 static const char * const scif3_groups[] = {
3899 "scif3_data_a",
3900 "scif3_clk",
3901 "scif3_ctrl",
3902 "scif3_data_b",
3903 };
3904
3905 static const char * const scif4_groups[] = {
3906 "scif4_data_a",
3907 "scif4_clk_a",
3908 "scif4_ctrl_a",
3909 "scif4_data_b",
3910 "scif4_clk_b",
3911 "scif4_ctrl_b",
3912 "scif4_data_c",
3913 "scif4_clk_c",
3914 "scif4_ctrl_c",
3915 };
3916
3917 static const char * const scif5_groups[] = {
3918 "scif5_data_a",
3919 "scif5_clk_a",
3920 "scif5_data_b",
3921 "scif5_clk_b",
3922 };
3923
3924 static const char * const scif_clk_groups[] = {
3925 "scif_clk_a",
3926 "scif_clk_b",
3927 };
3928
3929 static const char * const sdhi0_groups[] = {
3930 "sdhi0_data1",
3931 "sdhi0_data4",
3932 "sdhi0_ctrl",
3933 "sdhi0_cd",
3934 "sdhi0_wp",
3935 };
3936
3937 static const char * const sdhi1_groups[] = {
3938 "sdhi1_data1",
3939 "sdhi1_data4",
3940 "sdhi1_ctrl",
3941 "sdhi1_cd",
3942 "sdhi1_wp",
3943 };
3944
3945 static const char * const sdhi2_groups[] = {
3946 "sdhi2_data1",
3947 "sdhi2_data4",
3948 "sdhi2_data8",
3949 "sdhi2_ctrl",
3950 "sdhi2_cd_a",
3951 "sdhi2_wp_a",
3952 "sdhi2_cd_b",
3953 "sdhi2_wp_b",
3954 "sdhi2_ds",
3955 };
3956
3957 static const char * const sdhi3_groups[] = {
3958 "sdhi3_data1",
3959 "sdhi3_data4",
3960 "sdhi3_data8",
3961 "sdhi3_ctrl",
3962 "sdhi3_cd",
3963 "sdhi3_wp",
3964 "sdhi3_ds",
3965 };
3966
3967 static const char * const usb0_groups[] = {
3968 "usb0",
3969 };
3970
3971 static const char * const usb1_groups[] = {
3972 "usb1",
3973 };
3974
3975 static const char * const usb30_groups[] = {
3976 "usb30",
3977 };
3978
3979 static const struct sh_pfc_function pinmux_functions[] = {
3980 SH_PFC_FUNCTION(avb),
3981 SH_PFC_FUNCTION(du),
3982 SH_PFC_FUNCTION(hscif0),
3983 SH_PFC_FUNCTION(hscif1),
3984 SH_PFC_FUNCTION(hscif2),
3985 SH_PFC_FUNCTION(hscif3),
3986 SH_PFC_FUNCTION(hscif4),
3987 SH_PFC_FUNCTION(i2c1),
3988 SH_PFC_FUNCTION(i2c2),
3989 SH_PFC_FUNCTION(i2c6),
3990 SH_PFC_FUNCTION(intc_ex),
3991 SH_PFC_FUNCTION(msiof0),
3992 SH_PFC_FUNCTION(msiof1),
3993 SH_PFC_FUNCTION(msiof2),
3994 SH_PFC_FUNCTION(msiof3),
3995 SH_PFC_FUNCTION(pwm0),
3996 SH_PFC_FUNCTION(pwm1),
3997 SH_PFC_FUNCTION(pwm2),
3998 SH_PFC_FUNCTION(pwm3),
3999 SH_PFC_FUNCTION(pwm4),
4000 SH_PFC_FUNCTION(pwm5),
4001 SH_PFC_FUNCTION(pwm6),
4002 SH_PFC_FUNCTION(scif0),
4003 SH_PFC_FUNCTION(scif1),
4004 SH_PFC_FUNCTION(scif2),
4005 SH_PFC_FUNCTION(scif3),
4006 SH_PFC_FUNCTION(scif4),
4007 SH_PFC_FUNCTION(scif5),
4008 SH_PFC_FUNCTION(scif_clk),
4009 SH_PFC_FUNCTION(sdhi0),
4010 SH_PFC_FUNCTION(sdhi1),
4011 SH_PFC_FUNCTION(sdhi2),
4012 SH_PFC_FUNCTION(sdhi3),
4013 SH_PFC_FUNCTION(usb0),
4014 SH_PFC_FUNCTION(usb1),
4015 SH_PFC_FUNCTION(usb30),
4016 };
4017
4018 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4019 #define F_(x, y) FN_##y
4020 #define FM(x) FN_##x
4021 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4022 0, 0,
4023 0, 0,
4024 0, 0,
4025 0, 0,
4026 0, 0,
4027 0, 0,
4028 0, 0,
4029 0, 0,
4030 0, 0,
4031 0, 0,
4032 0, 0,
4033 0, 0,
4034 0, 0,
4035 0, 0,
4036 0, 0,
4037 0, 0,
4038 GP_0_15_FN, GPSR0_15,
4039 GP_0_14_FN, GPSR0_14,
4040 GP_0_13_FN, GPSR0_13,
4041 GP_0_12_FN, GPSR0_12,
4042 GP_0_11_FN, GPSR0_11,
4043 GP_0_10_FN, GPSR0_10,
4044 GP_0_9_FN, GPSR0_9,
4045 GP_0_8_FN, GPSR0_8,
4046 GP_0_7_FN, GPSR0_7,
4047 GP_0_6_FN, GPSR0_6,
4048 GP_0_5_FN, GPSR0_5,
4049 GP_0_4_FN, GPSR0_4,
4050 GP_0_3_FN, GPSR0_3,
4051 GP_0_2_FN, GPSR0_2,
4052 GP_0_1_FN, GPSR0_1,
4053 GP_0_0_FN, GPSR0_0, }
4054 },
4055 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4056 0, 0,
4057 0, 0,
4058 0, 0,
4059 GP_1_28_FN, GPSR1_28,
4060 GP_1_27_FN, GPSR1_27,
4061 GP_1_26_FN, GPSR1_26,
4062 GP_1_25_FN, GPSR1_25,
4063 GP_1_24_FN, GPSR1_24,
4064 GP_1_23_FN, GPSR1_23,
4065 GP_1_22_FN, GPSR1_22,
4066 GP_1_21_FN, GPSR1_21,
4067 GP_1_20_FN, GPSR1_20,
4068 GP_1_19_FN, GPSR1_19,
4069 GP_1_18_FN, GPSR1_18,
4070 GP_1_17_FN, GPSR1_17,
4071 GP_1_16_FN, GPSR1_16,
4072 GP_1_15_FN, GPSR1_15,
4073 GP_1_14_FN, GPSR1_14,
4074 GP_1_13_FN, GPSR1_13,
4075 GP_1_12_FN, GPSR1_12,
4076 GP_1_11_FN, GPSR1_11,
4077 GP_1_10_FN, GPSR1_10,
4078 GP_1_9_FN, GPSR1_9,
4079 GP_1_8_FN, GPSR1_8,
4080 GP_1_7_FN, GPSR1_7,
4081 GP_1_6_FN, GPSR1_6,
4082 GP_1_5_FN, GPSR1_5,
4083 GP_1_4_FN, GPSR1_4,
4084 GP_1_3_FN, GPSR1_3,
4085 GP_1_2_FN, GPSR1_2,
4086 GP_1_1_FN, GPSR1_1,
4087 GP_1_0_FN, GPSR1_0, }
4088 },
4089 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4090 0, 0,
4091 0, 0,
4092 0, 0,
4093 0, 0,
4094 0, 0,
4095 0, 0,
4096 0, 0,
4097 0, 0,
4098 0, 0,
4099 0, 0,
4100 0, 0,
4101 0, 0,
4102 0, 0,
4103 0, 0,
4104 0, 0,
4105 0, 0,
4106 0, 0,
4107 GP_2_14_FN, GPSR2_14,
4108 GP_2_13_FN, GPSR2_13,
4109 GP_2_12_FN, GPSR2_12,
4110 GP_2_11_FN, GPSR2_11,
4111 GP_2_10_FN, GPSR2_10,
4112 GP_2_9_FN, GPSR2_9,
4113 GP_2_8_FN, GPSR2_8,
4114 GP_2_7_FN, GPSR2_7,
4115 GP_2_6_FN, GPSR2_6,
4116 GP_2_5_FN, GPSR2_5,
4117 GP_2_4_FN, GPSR2_4,
4118 GP_2_3_FN, GPSR2_3,
4119 GP_2_2_FN, GPSR2_2,
4120 GP_2_1_FN, GPSR2_1,
4121 GP_2_0_FN, GPSR2_0, }
4122 },
4123 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4124 0, 0,
4125 0, 0,
4126 0, 0,
4127 0, 0,
4128 0, 0,
4129 0, 0,
4130 0, 0,
4131 0, 0,
4132 0, 0,
4133 0, 0,
4134 0, 0,
4135 0, 0,
4136 0, 0,
4137 0, 0,
4138 0, 0,
4139 0, 0,
4140 GP_3_15_FN, GPSR3_15,
4141 GP_3_14_FN, GPSR3_14,
4142 GP_3_13_FN, GPSR3_13,
4143 GP_3_12_FN, GPSR3_12,
4144 GP_3_11_FN, GPSR3_11,
4145 GP_3_10_FN, GPSR3_10,
4146 GP_3_9_FN, GPSR3_9,
4147 GP_3_8_FN, GPSR3_8,
4148 GP_3_7_FN, GPSR3_7,
4149 GP_3_6_FN, GPSR3_6,
4150 GP_3_5_FN, GPSR3_5,
4151 GP_3_4_FN, GPSR3_4,
4152 GP_3_3_FN, GPSR3_3,
4153 GP_3_2_FN, GPSR3_2,
4154 GP_3_1_FN, GPSR3_1,
4155 GP_3_0_FN, GPSR3_0, }
4156 },
4157 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4158 0, 0,
4159 0, 0,
4160 0, 0,
4161 0, 0,
4162 0, 0,
4163 0, 0,
4164 0, 0,
4165 0, 0,
4166 0, 0,
4167 0, 0,
4168 0, 0,
4169 0, 0,
4170 0, 0,
4171 0, 0,
4172 GP_4_17_FN, GPSR4_17,
4173 GP_4_16_FN, GPSR4_16,
4174 GP_4_15_FN, GPSR4_15,
4175 GP_4_14_FN, GPSR4_14,
4176 GP_4_13_FN, GPSR4_13,
4177 GP_4_12_FN, GPSR4_12,
4178 GP_4_11_FN, GPSR4_11,
4179 GP_4_10_FN, GPSR4_10,
4180 GP_4_9_FN, GPSR4_9,
4181 GP_4_8_FN, GPSR4_8,
4182 GP_4_7_FN, GPSR4_7,
4183 GP_4_6_FN, GPSR4_6,
4184 GP_4_5_FN, GPSR4_5,
4185 GP_4_4_FN, GPSR4_4,
4186 GP_4_3_FN, GPSR4_3,
4187 GP_4_2_FN, GPSR4_2,
4188 GP_4_1_FN, GPSR4_1,
4189 GP_4_0_FN, GPSR4_0, }
4190 },
4191 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4192 0, 0,
4193 0, 0,
4194 0, 0,
4195 0, 0,
4196 0, 0,
4197 0, 0,
4198 GP_5_25_FN, GPSR5_25,
4199 GP_5_24_FN, GPSR5_24,
4200 GP_5_23_FN, GPSR5_23,
4201 GP_5_22_FN, GPSR5_22,
4202 GP_5_21_FN, GPSR5_21,
4203 GP_5_20_FN, GPSR5_20,
4204 GP_5_19_FN, GPSR5_19,
4205 GP_5_18_FN, GPSR5_18,
4206 GP_5_17_FN, GPSR5_17,
4207 GP_5_16_FN, GPSR5_16,
4208 GP_5_15_FN, GPSR5_15,
4209 GP_5_14_FN, GPSR5_14,
4210 GP_5_13_FN, GPSR5_13,
4211 GP_5_12_FN, GPSR5_12,
4212 GP_5_11_FN, GPSR5_11,
4213 GP_5_10_FN, GPSR5_10,
4214 GP_5_9_FN, GPSR5_9,
4215 GP_5_8_FN, GPSR5_8,
4216 GP_5_7_FN, GPSR5_7,
4217 GP_5_6_FN, GPSR5_6,
4218 GP_5_5_FN, GPSR5_5,
4219 GP_5_4_FN, GPSR5_4,
4220 GP_5_3_FN, GPSR5_3,
4221 GP_5_2_FN, GPSR5_2,
4222 GP_5_1_FN, GPSR5_1,
4223 GP_5_0_FN, GPSR5_0, }
4224 },
4225 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4226 GP_6_31_FN, GPSR6_31,
4227 GP_6_30_FN, GPSR6_30,
4228 GP_6_29_FN, GPSR6_29,
4229 GP_6_28_FN, GPSR6_28,
4230 GP_6_27_FN, GPSR6_27,
4231 GP_6_26_FN, GPSR6_26,
4232 GP_6_25_FN, GPSR6_25,
4233 GP_6_24_FN, GPSR6_24,
4234 GP_6_23_FN, GPSR6_23,
4235 GP_6_22_FN, GPSR6_22,
4236 GP_6_21_FN, GPSR6_21,
4237 GP_6_20_FN, GPSR6_20,
4238 GP_6_19_FN, GPSR6_19,
4239 GP_6_18_FN, GPSR6_18,
4240 GP_6_17_FN, GPSR6_17,
4241 GP_6_16_FN, GPSR6_16,
4242 GP_6_15_FN, GPSR6_15,
4243 GP_6_14_FN, GPSR6_14,
4244 GP_6_13_FN, GPSR6_13,
4245 GP_6_12_FN, GPSR6_12,
4246 GP_6_11_FN, GPSR6_11,
4247 GP_6_10_FN, GPSR6_10,
4248 GP_6_9_FN, GPSR6_9,
4249 GP_6_8_FN, GPSR6_8,
4250 GP_6_7_FN, GPSR6_7,
4251 GP_6_6_FN, GPSR6_6,
4252 GP_6_5_FN, GPSR6_5,
4253 GP_6_4_FN, GPSR6_4,
4254 GP_6_3_FN, GPSR6_3,
4255 GP_6_2_FN, GPSR6_2,
4256 GP_6_1_FN, GPSR6_1,
4257 GP_6_0_FN, GPSR6_0, }
4258 },
4259 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4260 0, 0,
4261 0, 0,
4262 0, 0,
4263 0, 0,
4264 0, 0,
4265 0, 0,
4266 0, 0,
4267 0, 0,
4268 0, 0,
4269 0, 0,
4270 0, 0,
4271 0, 0,
4272 0, 0,
4273 0, 0,
4274 0, 0,
4275 0, 0,
4276 0, 0,
4277 0, 0,
4278 0, 0,
4279 0, 0,
4280 0, 0,
4281 0, 0,
4282 0, 0,
4283 0, 0,
4284 0, 0,
4285 0, 0,
4286 0, 0,
4287 0, 0,
4288 GP_7_3_FN, GPSR7_3,
4289 GP_7_2_FN, GPSR7_2,
4290 GP_7_1_FN, GPSR7_1,
4291 GP_7_0_FN, GPSR7_0, }
4292 },
4293 #undef F_
4294 #undef FM
4295
4296 #define F_(x, y) x,
4297 #define FM(x) FN_##x,
4298 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4299 IP0_31_28
4300 IP0_27_24
4301 IP0_23_20
4302 IP0_19_16
4303 IP0_15_12
4304 IP0_11_8
4305 IP0_7_4
4306 IP0_3_0 }
4307 },
4308 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4309 IP1_31_28
4310 IP1_27_24
4311 IP1_23_20
4312 IP1_19_16
4313 IP1_15_12
4314 IP1_11_8
4315 IP1_7_4
4316 IP1_3_0 }
4317 },
4318 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4319 IP2_31_28
4320 IP2_27_24
4321 IP2_23_20
4322 IP2_19_16
4323 IP2_15_12
4324 IP2_11_8
4325 IP2_7_4
4326 IP2_3_0 }
4327 },
4328 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4329 IP3_31_28
4330 IP3_27_24
4331 IP3_23_20
4332 IP3_19_16
4333 IP3_15_12
4334 IP3_11_8
4335 IP3_7_4
4336 IP3_3_0 }
4337 },
4338 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4339 IP4_31_28
4340 IP4_27_24
4341 IP4_23_20
4342 IP4_19_16
4343 IP4_15_12
4344 IP4_11_8
4345 IP4_7_4
4346 IP4_3_0 }
4347 },
4348 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4349 IP5_31_28
4350 IP5_27_24
4351 IP5_23_20
4352 IP5_19_16
4353 IP5_15_12
4354 IP5_11_8
4355 IP5_7_4
4356 IP5_3_0 }
4357 },
4358 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4359 IP6_31_28
4360 IP6_27_24
4361 IP6_23_20
4362 IP6_19_16
4363 IP6_15_12
4364 IP6_11_8
4365 IP6_7_4
4366 IP6_3_0 }
4367 },
4368 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4369 IP7_31_28
4370 IP7_27_24
4371 IP7_23_20
4372 IP7_19_16
4373 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4374 IP7_11_8
4375 IP7_7_4
4376 IP7_3_0 }
4377 },
4378 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4379 IP8_31_28
4380 IP8_27_24
4381 IP8_23_20
4382 IP8_19_16
4383 IP8_15_12
4384 IP8_11_8
4385 IP8_7_4
4386 IP8_3_0 }
4387 },
4388 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4389 IP9_31_28
4390 IP9_27_24
4391 IP9_23_20
4392 IP9_19_16
4393 IP9_15_12
4394 IP9_11_8
4395 IP9_7_4
4396 IP9_3_0 }
4397 },
4398 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
4399 IP10_31_28
4400 IP10_27_24
4401 IP10_23_20
4402 IP10_19_16
4403 IP10_15_12
4404 IP10_11_8
4405 IP10_7_4
4406 IP10_3_0 }
4407 },
4408 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
4409 IP11_31_28
4410 IP11_27_24
4411 IP11_23_20
4412 IP11_19_16
4413 IP11_15_12
4414 IP11_11_8
4415 IP11_7_4
4416 IP11_3_0 }
4417 },
4418 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
4419 IP12_31_28
4420 IP12_27_24
4421 IP12_23_20
4422 IP12_19_16
4423 IP12_15_12
4424 IP12_11_8
4425 IP12_7_4
4426 IP12_3_0 }
4427 },
4428 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
4429 IP13_31_28
4430 IP13_27_24
4431 IP13_23_20
4432 IP13_19_16
4433 IP13_15_12
4434 IP13_11_8
4435 IP13_7_4
4436 IP13_3_0 }
4437 },
4438 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
4439 IP14_31_28
4440 IP14_27_24
4441 IP14_23_20
4442 IP14_19_16
4443 IP14_15_12
4444 IP14_11_8
4445 IP14_7_4
4446 IP14_3_0 }
4447 },
4448 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
4449 IP15_31_28
4450 IP15_27_24
4451 IP15_23_20
4452 IP15_19_16
4453 IP15_15_12
4454 IP15_11_8
4455 IP15_7_4
4456 IP15_3_0 }
4457 },
4458 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
4459 IP16_31_28
4460 IP16_27_24
4461 IP16_23_20
4462 IP16_19_16
4463 IP16_15_12
4464 IP16_11_8
4465 IP16_7_4
4466 IP16_3_0 }
4467 },
4468 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
4469 IP17_31_28
4470 IP17_27_24
4471 IP17_23_20
4472 IP17_19_16
4473 IP17_15_12
4474 IP17_11_8
4475 IP17_7_4
4476 IP17_3_0 }
4477 },
4478 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
4479 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4480 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4481 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4482 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4483 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4484 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4485 IP18_7_4
4486 IP18_3_0 }
4487 },
4488 #undef F_
4489 #undef FM
4490
4491 #define F_(x, y) x,
4492 #define FM(x) FN_##x,
4493 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4494 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
4495 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
4496 MOD_SEL0_31_30_29
4497 MOD_SEL0_28_27
4498 MOD_SEL0_26_25_24
4499 MOD_SEL0_23
4500 MOD_SEL0_22
4501 MOD_SEL0_21
4502 MOD_SEL0_20
4503 MOD_SEL0_19
4504 MOD_SEL0_18_17
4505 MOD_SEL0_16
4506 0, 0, /* RESERVED 15 */
4507 MOD_SEL0_14_13
4508 MOD_SEL0_12
4509 MOD_SEL0_11
4510 MOD_SEL0_10
4511 MOD_SEL0_9_8
4512 MOD_SEL0_7_6
4513 MOD_SEL0_5
4514 MOD_SEL0_4_3
4515 /* RESERVED 2, 1, 0 */
4516 0, 0, 0, 0, 0, 0, 0, 0 }
4517 },
4518 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4519 2, 3, 1, 2, 3, 1, 1, 2, 1,
4520 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
4521 MOD_SEL1_31_30
4522 MOD_SEL1_29_28_27
4523 MOD_SEL1_26
4524 MOD_SEL1_25_24
4525 MOD_SEL1_23_22_21
4526 MOD_SEL1_20
4527 MOD_SEL1_19
4528 MOD_SEL1_18_17
4529 MOD_SEL1_16
4530 MOD_SEL1_15_14
4531 MOD_SEL1_13
4532 MOD_SEL1_12
4533 MOD_SEL1_11
4534 MOD_SEL1_10
4535 MOD_SEL1_9
4536 0, 0, 0, 0, /* RESERVED 8, 7 */
4537 MOD_SEL1_6
4538 MOD_SEL1_5
4539 MOD_SEL1_4
4540 MOD_SEL1_3
4541 MOD_SEL1_2
4542 MOD_SEL1_1
4543 MOD_SEL1_0 }
4544 },
4545 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
4546 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
4547 4, 4, 4, 3, 1) {
4548 MOD_SEL2_31
4549 MOD_SEL2_30
4550 MOD_SEL2_29
4551 MOD_SEL2_28_27
4552 MOD_SEL2_26
4553 MOD_SEL2_25_24_23
4554 MOD_SEL2_22
4555 MOD_SEL2_21
4556 MOD_SEL2_20
4557 MOD_SEL2_19
4558 MOD_SEL2_18
4559 MOD_SEL2_17
4560 /* RESERVED 16 */
4561 0, 0,
4562 /* RESERVED 15, 14, 13, 12 */
4563 0, 0, 0, 0, 0, 0, 0, 0,
4564 0, 0, 0, 0, 0, 0, 0, 0,
4565 /* RESERVED 11, 10, 9, 8 */
4566 0, 0, 0, 0, 0, 0, 0, 0,
4567 0, 0, 0, 0, 0, 0, 0, 0,
4568 /* RESERVED 7, 6, 5, 4 */
4569 0, 0, 0, 0, 0, 0, 0, 0,
4570 0, 0, 0, 0, 0, 0, 0, 0,
4571 /* RESERVED 3, 2, 1 */
4572 0, 0, 0, 0, 0, 0, 0, 0,
4573 MOD_SEL2_0 }
4574 },
4575 { },
4576 };
4577
4578 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
4579 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
4580 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
4581 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
4582 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
4583 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
4584 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
4585 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
4586 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
4587 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
4588 } },
4589 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
4590 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
4591 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
4592 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
4593 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
4594 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
4595 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
4596 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
4597 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
4598 } },
4599 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
4600 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
4601 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
4602 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
4603 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
4604 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
4605 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
4606 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
4607 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
4608 } },
4609 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
4610 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
4611 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
4612 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
4613 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
4614 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
4615 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
4616 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
4617 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
4618 } },
4619 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
4620 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
4621 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
4622 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
4623 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
4624 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
4625 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
4626 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
4627 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
4628 } },
4629 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
4630 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
4631 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
4632 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
4633 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
4634 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
4635 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
4636 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
4637 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
4638 } },
4639 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
4640 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
4641 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
4642 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
4643 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
4644 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
4645 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
4646 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
4647 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
4648 } },
4649 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
4650 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
4651 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
4652 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
4653 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
4654 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
4655 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
4656 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
4657 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
4658 } },
4659 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
4660 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
4661 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
4662 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
4663 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
4664 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
4665 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
4666 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
4667 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
4668 } },
4669 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
4670 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
4671 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
4672 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
4673 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
4674 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
4675 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
4676 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
4677 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
4678 } },
4679 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
4680 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
4681 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
4682 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
4683 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
4684 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
4685 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
4686 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
4687 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
4688 } },
4689 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
4690 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
4691 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
4692 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
4693 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
4694 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
4695 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
4696 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
4697 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
4698 } },
4699 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
4700 { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN3 */
4701 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
4702 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
4703 } },
4704 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
4705 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
4706 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
4707 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
4708 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
4709 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
4710 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
4711 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
4712 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
4713 } },
4714 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
4715 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
4716 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
4717 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
4718 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
4719 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
4720 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
4721 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
4722 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
4723 } },
4724 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
4725 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
4726 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
4727 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
4728 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
4729 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
4730 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
4731 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
4732 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
4733 } },
4734 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
4735 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
4736 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
4737 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
4738 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
4739 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
4740 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
4741 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
4742 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
4743 } },
4744 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
4745 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
4746 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
4747 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
4748 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
4749 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
4750 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
4751 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
4752 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
4753 } },
4754 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
4755 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
4756 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
4757 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
4758 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
4759 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
4760 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
4761 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
4762 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
4763 } },
4764 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
4765 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
4766 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
4767 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
4768 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
4769 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
4770 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
4771 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
4772 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
4773 } },
4774 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
4775 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
4776 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
4777 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
4778 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
4779 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
4780 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
4781 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
4782 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
4783 } },
4784 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
4785 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
4786 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
4787 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
4788 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
4789 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
4790 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
4791 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
4792 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
4793 } },
4794 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
4795 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
4796 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
4797 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
4798 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
4799 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
4800 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
4801 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
4802 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
4803 } },
4804 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
4805 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
4806 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
4807 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
4808 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
4809 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
4810 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
4811 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
4812 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
4813 } },
4814 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
4815 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
4816 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
4817 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
4818 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
4819 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
4820 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
4821 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
4822 } },
4823 { },
4824 };
4825
4826 enum ioctrl_regs {
4827 POCCTRL,
4828 };
4829
4830 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
4831 [POCCTRL] = { 0xe6060380, },
4832 { /* sentinel */ },
4833 };
4834
r8a77965_pin_to_pocctrl(struct sh_pfc * pfc,unsigned int pin,u32 * pocctrl)4835 static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
4836 {
4837 int bit = -EINVAL;
4838
4839 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
4840
4841 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
4842 bit = pin & 0x1f;
4843
4844 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
4845 bit = (pin & 0x1f) + 12;
4846
4847 return bit;
4848 }
4849
4850 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
4851 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
4852 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
4853 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
4854 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
4855 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
4856 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
4857 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
4858 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
4859 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
4860 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
4861 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
4862 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
4863 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
4864 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
4865 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
4866 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
4867 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
4868 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
4869 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
4870 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
4871 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
4872 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
4873 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
4874 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
4875 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
4876 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
4877 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
4878 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
4879 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
4880 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
4881 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
4882 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
4883 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
4884 } },
4885 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
4886 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
4887 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
4888 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
4889 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
4890 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
4891 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
4892 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
4893 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
4894 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
4895 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
4896 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
4897 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
4898 [12] = RCAR_GP_PIN(1, 0), /* A0 */
4899 [13] = RCAR_GP_PIN(1, 1), /* A1 */
4900 [14] = RCAR_GP_PIN(1, 2), /* A2 */
4901 [15] = RCAR_GP_PIN(1, 3), /* A3 */
4902 [16] = RCAR_GP_PIN(1, 4), /* A4 */
4903 [17] = RCAR_GP_PIN(1, 5), /* A5 */
4904 [18] = RCAR_GP_PIN(1, 6), /* A6 */
4905 [19] = RCAR_GP_PIN(1, 7), /* A7 */
4906 [20] = RCAR_GP_PIN(1, 8), /* A8 */
4907 [21] = RCAR_GP_PIN(1, 9), /* A9 */
4908 [22] = RCAR_GP_PIN(1, 10), /* A10 */
4909 [23] = RCAR_GP_PIN(1, 11), /* A11 */
4910 [24] = RCAR_GP_PIN(1, 12), /* A12 */
4911 [25] = RCAR_GP_PIN(1, 13), /* A13 */
4912 [26] = RCAR_GP_PIN(1, 14), /* A14 */
4913 [27] = RCAR_GP_PIN(1, 15), /* A15 */
4914 [28] = RCAR_GP_PIN(1, 16), /* A16 */
4915 [29] = RCAR_GP_PIN(1, 17), /* A17 */
4916 [30] = RCAR_GP_PIN(1, 18), /* A18 */
4917 [31] = RCAR_GP_PIN(1, 19), /* A19 */
4918 } },
4919 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
4920 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
4921 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
4922 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
4923 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
4924 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
4925 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
4926 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
4927 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
4928 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
4929 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
4930 [10] = RCAR_GP_PIN(0, 0), /* D0 */
4931 [11] = RCAR_GP_PIN(0, 1), /* D1 */
4932 [12] = RCAR_GP_PIN(0, 2), /* D2 */
4933 [13] = RCAR_GP_PIN(0, 3), /* D3 */
4934 [14] = RCAR_GP_PIN(0, 4), /* D4 */
4935 [15] = RCAR_GP_PIN(0, 5), /* D5 */
4936 [16] = RCAR_GP_PIN(0, 6), /* D6 */
4937 [17] = RCAR_GP_PIN(0, 7), /* D7 */
4938 [18] = RCAR_GP_PIN(0, 8), /* D8 */
4939 [19] = RCAR_GP_PIN(0, 9), /* D9 */
4940 [20] = RCAR_GP_PIN(0, 10), /* D10 */
4941 [21] = RCAR_GP_PIN(0, 11), /* D11 */
4942 [22] = RCAR_GP_PIN(0, 12), /* D12 */
4943 [23] = RCAR_GP_PIN(0, 13), /* D13 */
4944 [24] = RCAR_GP_PIN(0, 14), /* D14 */
4945 [25] = RCAR_GP_PIN(0, 15), /* D15 */
4946 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
4947 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
4948 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
4949 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
4950 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
4951 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
4952 } },
4953 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
4954 [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
4955 [ 1] = PIN_NONE,
4956 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
4957 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
4958 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
4959 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
4960 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
4961 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
4962 [ 8] = PIN_NONE,
4963 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
4964 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
4965 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
4966 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
4967 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
4968 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
4969 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
4970 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
4971 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
4972 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
4973 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
4974 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
4975 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
4976 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
4977 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
4978 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
4979 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
4980 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
4981 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
4982 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
4983 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
4984 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
4985 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
4986 } },
4987 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
4988 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
4989 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
4990 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
4991 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
4992 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
4993 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
4994 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
4995 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
4996 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
4997 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
4998 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
4999 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
5000 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
5001 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
5002 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
5003 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
5004 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
5005 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
5006 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
5007 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
5008 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
5009 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
5010 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
5011 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
5012 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
5013 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
5014 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
5015 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
5016 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
5017 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
5018 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
5019 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
5020 } },
5021 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5022 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
5023 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
5024 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
5025 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
5026 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
5027 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
5028 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
5029 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
5030 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
5031 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
5032 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
5033 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
5034 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
5035 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
5036 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
5037 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
5038 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
5039 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
5040 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
5041 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
5042 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
5043 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
5044 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
5045 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
5046 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
5047 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
5048 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
5049 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
5050 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
5051 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
5052 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
5053 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
5054 } },
5055 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5056 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
5057 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
5058 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
5059 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
5060 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
5061 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
5062 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
5063 [ 7] = PIN_NONE,
5064 [ 8] = PIN_NONE,
5065 [ 9] = PIN_NONE,
5066 [10] = PIN_NONE,
5067 [11] = PIN_NONE,
5068 [12] = PIN_NONE,
5069 [13] = PIN_NONE,
5070 [14] = PIN_NONE,
5071 [15] = PIN_NONE,
5072 [16] = PIN_NONE,
5073 [17] = PIN_NONE,
5074 [18] = PIN_NONE,
5075 [19] = PIN_NONE,
5076 [20] = PIN_NONE,
5077 [21] = PIN_NONE,
5078 [22] = PIN_NONE,
5079 [23] = PIN_NONE,
5080 [24] = PIN_NONE,
5081 [25] = PIN_NONE,
5082 [26] = PIN_NONE,
5083 [27] = PIN_NONE,
5084 [28] = PIN_NONE,
5085 [29] = PIN_NONE,
5086 [30] = PIN_NONE,
5087 [31] = PIN_NONE,
5088 } },
5089 { /* sentinel */ },
5090 };
5091
r8a77965_pinmux_get_bias(struct sh_pfc * pfc,unsigned int pin)5092 static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
5093 unsigned int pin)
5094 {
5095 const struct pinmux_bias_reg *reg;
5096 unsigned int bit;
5097
5098 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5099 if (!reg)
5100 return PIN_CONFIG_BIAS_DISABLE;
5101
5102 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
5103 return PIN_CONFIG_BIAS_DISABLE;
5104 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
5105 return PIN_CONFIG_BIAS_PULL_UP;
5106 else
5107 return PIN_CONFIG_BIAS_PULL_DOWN;
5108 }
5109
r8a77965_pinmux_set_bias(struct sh_pfc * pfc,unsigned int pin,unsigned int bias)5110 static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5111 unsigned int bias)
5112 {
5113 const struct pinmux_bias_reg *reg;
5114 u32 enable, updown;
5115 unsigned int bit;
5116
5117 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5118 if (!reg)
5119 return;
5120
5121 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
5122 if (bias != PIN_CONFIG_BIAS_DISABLE)
5123 enable |= BIT(bit);
5124
5125 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
5126 if (bias == PIN_CONFIG_BIAS_PULL_UP)
5127 updown |= BIT(bit);
5128
5129 sh_pfc_write(pfc, reg->pud, updown);
5130 sh_pfc_write(pfc, reg->puen, enable);
5131 }
5132
5133 static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
5134 .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
5135 .get_bias = r8a77965_pinmux_get_bias,
5136 .set_bias = r8a77965_pinmux_set_bias,
5137 };
5138
5139 const struct sh_pfc_soc_info r8a77965_pinmux_info = {
5140 .name = "r8a77965_pfc",
5141 .ops = &r8a77965_pinmux_ops,
5142 .unlock_reg = 0xe6060000, /* PMMR */
5143
5144 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5145
5146 .pins = pinmux_pins,
5147 .nr_pins = ARRAY_SIZE(pinmux_pins),
5148 .groups = pinmux_groups,
5149 .nr_groups = ARRAY_SIZE(pinmux_groups),
5150 .functions = pinmux_functions,
5151 .nr_functions = ARRAY_SIZE(pinmux_functions),
5152
5153 .cfg_regs = pinmux_config_regs,
5154 .drive_regs = pinmux_drive_regs,
5155 .bias_regs = pinmux_bias_regs,
5156 .ioctrl_regs = pinmux_ioctrl_regs,
5157
5158 .pinmux_data = pinmux_data,
5159 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5160 };
5161
