1 /*
2 * (c) Copyright 2002-2010, Ralink Technology, Inc.
3 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
4 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
5 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2
9 * as published by the Free Software Foundation
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include "mt76x0.h"
18 #include "eeprom.h"
19 #include "trace.h"
20 #include "mcu.h"
21 #include "usb.h"
22
23 #include "initvals.h"
24
25 static void
mt76x0_set_wlan_state(struct mt76x0_dev * dev,u32 val,bool enable)26 mt76x0_set_wlan_state(struct mt76x0_dev *dev, u32 val, bool enable)
27 {
28 int i;
29
30 /* Note: we don't turn off WLAN_CLK because that makes the device
31 * not respond properly on the probe path.
32 * In case anyone (PSM?) wants to use this function we can
33 * bring the clock stuff back and fixup the probe path.
34 */
35
36 if (enable)
37 val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
38 MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
39 else
40 val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN);
41
42 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
43 udelay(20);
44
45 if (!enable)
46 return;
47
48 for (i = 200; i; i--) {
49 val = mt76_rr(dev, MT_CMB_CTRL);
50
51 if (val & MT_CMB_CTRL_XTAL_RDY && val & MT_CMB_CTRL_PLL_LD)
52 break;
53
54 udelay(20);
55 }
56
57 /* Note: vendor driver tries to disable/enable wlan here and retry
58 * but the code which does it is so buggy it must have never
59 * triggered, so don't bother.
60 */
61 if (!i)
62 dev_err(dev->mt76.dev, "Error: PLL and XTAL check failed!\n");
63 }
64
mt76x0_chip_onoff(struct mt76x0_dev * dev,bool enable,bool reset)65 void mt76x0_chip_onoff(struct mt76x0_dev *dev, bool enable, bool reset)
66 {
67 u32 val;
68
69 mutex_lock(&dev->hw_atomic_mutex);
70
71 val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
72
73 if (reset) {
74 val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN;
75 val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
76
77 if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
78 val |= (MT_WLAN_FUN_CTRL_WLAN_RESET |
79 MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
80 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
81 udelay(20);
82
83 val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET |
84 MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
85 }
86 }
87
88 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
89 udelay(20);
90
91 mt76x0_set_wlan_state(dev, val, enable);
92
93 mutex_unlock(&dev->hw_atomic_mutex);
94 }
95
mt76x0_reset_csr_bbp(struct mt76x0_dev * dev)96 static void mt76x0_reset_csr_bbp(struct mt76x0_dev *dev)
97 {
98 u32 val;
99
100 val = mt76_rr(dev, MT_PBF_SYS_CTRL);
101 val &= ~0x2000;
102 mt76_wr(dev, MT_PBF_SYS_CTRL, val);
103
104 mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR |
105 MT_MAC_SYS_CTRL_RESET_BBP);
106
107 msleep(200);
108 }
109
mt76x0_init_usb_dma(struct mt76x0_dev * dev)110 static void mt76x0_init_usb_dma(struct mt76x0_dev *dev)
111 {
112 u32 val;
113
114 val = mt76_rr(dev, MT_USB_DMA_CFG);
115
116 val |= FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_TOUT, MT_USB_AGGR_TIMEOUT) |
117 FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_LMT, MT_USB_AGGR_SIZE_LIMIT) |
118 MT_USB_DMA_CFG_RX_BULK_EN |
119 MT_USB_DMA_CFG_TX_BULK_EN;
120 if (dev->in_max_packet == 512)
121 val |= MT_USB_DMA_CFG_RX_BULK_AGG_EN;
122 mt76_wr(dev, MT_USB_DMA_CFG, val);
123
124 val = mt76_rr(dev, MT_COM_REG0);
125 if (val & 1)
126 dev_dbg(dev->mt76.dev, "MCU not ready\n");
127
128 val = mt76_rr(dev, MT_USB_DMA_CFG);
129
130 val |= MT_USB_DMA_CFG_RX_DROP_OR_PADDING;
131 mt76_wr(dev, MT_USB_DMA_CFG, val);
132 val &= ~MT_USB_DMA_CFG_RX_DROP_OR_PADDING;
133 mt76_wr(dev, MT_USB_DMA_CFG, val);
134 }
135
136 #define RANDOM_WRITE(dev, tab) \
137 mt76x0_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN, tab, ARRAY_SIZE(tab));
138
mt76x0_init_bbp(struct mt76x0_dev * dev)139 static int mt76x0_init_bbp(struct mt76x0_dev *dev)
140 {
141 int ret, i;
142
143 ret = mt76x0_wait_bbp_ready(dev);
144 if (ret)
145 return ret;
146
147 RANDOM_WRITE(dev, mt76x0_bbp_init_tab);
148
149 for (i = 0; i < ARRAY_SIZE(mt76x0_bbp_switch_tab); i++) {
150 const struct mt76x0_bbp_switch_item *item = &mt76x0_bbp_switch_tab[i];
151 const struct mt76_reg_pair *pair = &item->reg_pair;
152
153 if (((RF_G_BAND | RF_BW_20) & item->bw_band) == (RF_G_BAND | RF_BW_20))
154 mt76_wr(dev, pair->reg, pair->value);
155 }
156
157 RANDOM_WRITE(dev, mt76x0_dcoc_tab);
158
159 return 0;
160 }
161
162 static void
mt76_init_beacon_offsets(struct mt76x0_dev * dev)163 mt76_init_beacon_offsets(struct mt76x0_dev *dev)
164 {
165 u16 base = MT_BEACON_BASE;
166 u32 regs[4] = {};
167 int i;
168
169 for (i = 0; i < 16; i++) {
170 u16 addr = dev->beacon_offsets[i];
171
172 regs[i / 4] |= ((addr - base) / 64) << (8 * (i % 4));
173 }
174
175 for (i = 0; i < 4; i++)
176 mt76_wr(dev, MT_BCN_OFFSET(i), regs[i]);
177 }
178
mt76x0_init_mac_registers(struct mt76x0_dev * dev)179 static void mt76x0_init_mac_registers(struct mt76x0_dev *dev)
180 {
181 u32 reg;
182
183 RANDOM_WRITE(dev, common_mac_reg_table);
184
185 mt76_init_beacon_offsets(dev);
186
187 /* Enable PBF and MAC clock SYS_CTRL[11:10] = 0x3 */
188 RANDOM_WRITE(dev, mt76x0_mac_reg_table);
189
190 /* Release BBP and MAC reset MAC_SYS_CTRL[1:0] = 0x0 */
191 reg = mt76_rr(dev, MT_MAC_SYS_CTRL);
192 reg &= ~0x3;
193 mt76_wr(dev, MT_MAC_SYS_CTRL, reg);
194
195 if (is_mt7610e(dev)) {
196 /* Disable COEX_EN */
197 reg = mt76_rr(dev, MT_COEXCFG0);
198 reg &= 0xFFFFFFFE;
199 mt76_wr(dev, MT_COEXCFG0, reg);
200 }
201
202 /* Set 0x141C[15:12]=0xF */
203 reg = mt76_rr(dev, MT_EXT_CCA_CFG);
204 reg |= 0x0000F000;
205 mt76_wr(dev, MT_EXT_CCA_CFG, reg);
206
207 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
208
209 /*
210 TxRing 9 is for Mgmt frame.
211 TxRing 8 is for In-band command frame.
212 WMM_RG0_TXQMA: This register setting is for FCE to define the rule of TxRing 9.
213 WMM_RG1_TXQMA: This register setting is for FCE to define the rule of TxRing 8.
214 */
215 reg = mt76_rr(dev, MT_WMM_CTRL);
216 reg &= ~0x000003FF;
217 reg |= 0x00000201;
218 mt76_wr(dev, MT_WMM_CTRL, reg);
219
220 /* TODO: Probably not needed */
221 mt76_wr(dev, 0x7028, 0);
222 mt76_wr(dev, 0x7010, 0);
223 mt76_wr(dev, 0x7024, 0);
224 msleep(10);
225 }
226
mt76x0_init_wcid_mem(struct mt76x0_dev * dev)227 static int mt76x0_init_wcid_mem(struct mt76x0_dev *dev)
228 {
229 u32 *vals;
230 int i, ret;
231
232 vals = kmalloc(sizeof(*vals) * N_WCIDS * 2, GFP_KERNEL);
233 if (!vals)
234 return -ENOMEM;
235
236 for (i = 0; i < N_WCIDS; i++) {
237 vals[i * 2] = 0xffffffff;
238 vals[i * 2 + 1] = 0x00ffffff;
239 }
240
241 ret = mt76x0_burst_write_regs(dev, MT_WCID_ADDR_BASE,
242 vals, N_WCIDS * 2);
243 kfree(vals);
244
245 return ret;
246 }
247
mt76x0_init_key_mem(struct mt76x0_dev * dev)248 static int mt76x0_init_key_mem(struct mt76x0_dev *dev)
249 {
250 u32 vals[4] = {};
251
252 return mt76x0_burst_write_regs(dev, MT_SKEY_MODE_BASE_0,
253 vals, ARRAY_SIZE(vals));
254 }
255
mt76x0_init_wcid_attr_mem(struct mt76x0_dev * dev)256 static int mt76x0_init_wcid_attr_mem(struct mt76x0_dev *dev)
257 {
258 u32 *vals;
259 int i, ret;
260
261 vals = kmalloc(sizeof(*vals) * N_WCIDS * 2, GFP_KERNEL);
262 if (!vals)
263 return -ENOMEM;
264
265 for (i = 0; i < N_WCIDS * 2; i++)
266 vals[i] = 1;
267
268 ret = mt76x0_burst_write_regs(dev, MT_WCID_ATTR_BASE,
269 vals, N_WCIDS * 2);
270 kfree(vals);
271
272 return ret;
273 }
274
mt76x0_reset_counters(struct mt76x0_dev * dev)275 static void mt76x0_reset_counters(struct mt76x0_dev *dev)
276 {
277 mt76_rr(dev, MT_RX_STA_CNT0);
278 mt76_rr(dev, MT_RX_STA_CNT1);
279 mt76_rr(dev, MT_RX_STA_CNT2);
280 mt76_rr(dev, MT_TX_STA_CNT0);
281 mt76_rr(dev, MT_TX_STA_CNT1);
282 mt76_rr(dev, MT_TX_STA_CNT2);
283 }
284
mt76x0_mac_start(struct mt76x0_dev * dev)285 int mt76x0_mac_start(struct mt76x0_dev *dev)
286 {
287 mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
288
289 if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
290 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 200000))
291 return -ETIMEDOUT;
292
293 dev->rxfilter = MT_RX_FILTR_CFG_CRC_ERR |
294 MT_RX_FILTR_CFG_PHY_ERR | MT_RX_FILTR_CFG_PROMISC |
295 MT_RX_FILTR_CFG_VER_ERR | MT_RX_FILTR_CFG_DUP |
296 MT_RX_FILTR_CFG_CFACK | MT_RX_FILTR_CFG_CFEND |
297 MT_RX_FILTR_CFG_ACK | MT_RX_FILTR_CFG_CTS |
298 MT_RX_FILTR_CFG_RTS | MT_RX_FILTR_CFG_PSPOLL |
299 MT_RX_FILTR_CFG_BA | MT_RX_FILTR_CFG_CTRL_RSV;
300 mt76_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
301
302 mt76_wr(dev, MT_MAC_SYS_CTRL,
303 MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX);
304
305 if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
306 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 50))
307 return -ETIMEDOUT;
308
309 return 0;
310 }
311
mt76x0_mac_stop_hw(struct mt76x0_dev * dev)312 static void mt76x0_mac_stop_hw(struct mt76x0_dev *dev)
313 {
314 int i, ok;
315
316 if (test_bit(MT76_REMOVED, &dev->mt76.state))
317 return;
318
319 mt76_clear(dev, MT_BEACON_TIME_CFG, MT_BEACON_TIME_CFG_TIMER_EN |
320 MT_BEACON_TIME_CFG_SYNC_MODE | MT_BEACON_TIME_CFG_TBTT_EN |
321 MT_BEACON_TIME_CFG_BEACON_TX);
322
323 if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_TX_BUSY, 0, 1000))
324 dev_warn(dev->mt76.dev, "Warning: TX DMA did not stop!\n");
325
326 /* Page count on TxQ */
327 i = 200;
328 while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) ||
329 (mt76_rr(dev, 0x0a30) & 0x000000ff) ||
330 (mt76_rr(dev, 0x0a34) & 0x00ff00ff)))
331 msleep(10);
332
333 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000))
334 dev_warn(dev->mt76.dev, "Warning: MAC TX did not stop!\n");
335
336 mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX |
337 MT_MAC_SYS_CTRL_ENABLE_TX);
338
339 /* Page count on RxQ */
340 ok = 0;
341 i = 200;
342 while (i--) {
343 if (!(mt76_rr(dev, MT_RXQ_STA) & 0x00ff0000) &&
344 !mt76_rr(dev, 0x0a30) &&
345 !mt76_rr(dev, 0x0a34)) {
346 if (ok++ > 5)
347 break;
348 continue;
349 }
350 msleep(1);
351 }
352
353 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000))
354 dev_warn(dev->mt76.dev, "Warning: MAC RX did not stop!\n");
355
356 if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_RX_BUSY, 0, 1000))
357 dev_warn(dev->mt76.dev, "Warning: RX DMA did not stop!\n");
358 }
359
mt76x0_mac_stop(struct mt76x0_dev * dev)360 void mt76x0_mac_stop(struct mt76x0_dev *dev)
361 {
362 mt76x0_mac_stop_hw(dev);
363 flush_delayed_work(&dev->stat_work);
364 cancel_delayed_work_sync(&dev->stat_work);
365 }
366
mt76x0_stop_hardware(struct mt76x0_dev * dev)367 static void mt76x0_stop_hardware(struct mt76x0_dev *dev)
368 {
369 mt76x0_chip_onoff(dev, false, false);
370 }
371
mt76x0_init_hardware(struct mt76x0_dev * dev)372 int mt76x0_init_hardware(struct mt76x0_dev *dev)
373 {
374 static const u16 beacon_offsets[16] = {
375 /* 512 byte per beacon */
376 0xc000, 0xc200, 0xc400, 0xc600,
377 0xc800, 0xca00, 0xcc00, 0xce00,
378 0xd000, 0xd200, 0xd400, 0xd600,
379 0xd800, 0xda00, 0xdc00, 0xde00
380 };
381 int ret;
382
383 dev->beacon_offsets = beacon_offsets;
384
385 mt76x0_chip_onoff(dev, true, true);
386
387 ret = mt76x0_wait_asic_ready(dev);
388 if (ret)
389 goto err;
390 ret = mt76x0_mcu_init(dev);
391 if (ret)
392 goto err;
393
394 if (!mt76_poll_msec(dev, MT_WPDMA_GLO_CFG,
395 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
396 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 100)) {
397 ret = -EIO;
398 goto err;
399 }
400
401 /* Wait for ASIC ready after FW load. */
402 ret = mt76x0_wait_asic_ready(dev);
403 if (ret)
404 goto err;
405
406 mt76x0_reset_csr_bbp(dev);
407 mt76x0_init_usb_dma(dev);
408
409 mt76_wr(dev, MT_HEADER_TRANS_CTRL_REG, 0x0);
410 mt76_wr(dev, MT_TSO_CTRL, 0x0);
411
412 ret = mt76x0_mcu_cmd_init(dev);
413 if (ret)
414 goto err;
415 ret = mt76x0_dma_init(dev);
416 if (ret)
417 goto err_mcu;
418
419 mt76x0_init_mac_registers(dev);
420
421 if (!mt76_poll_msec(dev, MT_MAC_STATUS,
422 MT_MAC_STATUS_TX | MT_MAC_STATUS_RX, 0, 1000)) {
423 ret = -EIO;
424 goto err_rx;
425 }
426
427 ret = mt76x0_init_bbp(dev);
428 if (ret)
429 goto err_rx;
430
431 ret = mt76x0_init_wcid_mem(dev);
432 if (ret)
433 goto err_rx;
434 ret = mt76x0_init_key_mem(dev);
435 if (ret)
436 goto err_rx;
437 ret = mt76x0_init_wcid_attr_mem(dev);
438 if (ret)
439 goto err_rx;
440
441 mt76_clear(dev, MT_BEACON_TIME_CFG, (MT_BEACON_TIME_CFG_TIMER_EN |
442 MT_BEACON_TIME_CFG_SYNC_MODE |
443 MT_BEACON_TIME_CFG_TBTT_EN |
444 MT_BEACON_TIME_CFG_BEACON_TX));
445
446 mt76x0_reset_counters(dev);
447
448 mt76_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e);
449
450 mt76_wr(dev, MT_TXOP_CTRL_CFG,
451 FIELD_PREP(MT_TXOP_TRUN_EN, 0x3f) |
452 FIELD_PREP(MT_TXOP_EXT_CCA_DLY, 0x58));
453
454 ret = mt76x0_eeprom_init(dev);
455 if (ret)
456 goto err_rx;
457
458 mt76x0_phy_init(dev);
459 return 0;
460
461 err_rx:
462 mt76x0_dma_cleanup(dev);
463 err_mcu:
464 mt76x0_mcu_cmd_deinit(dev);
465 err:
466 mt76x0_chip_onoff(dev, false, false);
467 return ret;
468 }
469
mt76x0_cleanup(struct mt76x0_dev * dev)470 void mt76x0_cleanup(struct mt76x0_dev *dev)
471 {
472 if (!test_and_clear_bit(MT76_STATE_INITIALIZED, &dev->mt76.state))
473 return;
474
475 mt76x0_stop_hardware(dev);
476 mt76x0_dma_cleanup(dev);
477 mt76x0_mcu_cmd_deinit(dev);
478 }
479
mt76x0_alloc_device(struct device * pdev)480 struct mt76x0_dev *mt76x0_alloc_device(struct device *pdev)
481 {
482 struct ieee80211_hw *hw;
483 struct mt76x0_dev *dev;
484
485 hw = ieee80211_alloc_hw(sizeof(*dev), &mt76x0_ops);
486 if (!hw)
487 return NULL;
488
489 dev = hw->priv;
490 dev->mt76.dev = pdev;
491 dev->mt76.hw = hw;
492 mutex_init(&dev->usb_ctrl_mtx);
493 mutex_init(&dev->reg_atomic_mutex);
494 mutex_init(&dev->hw_atomic_mutex);
495 mutex_init(&dev->mutex);
496 spin_lock_init(&dev->tx_lock);
497 spin_lock_init(&dev->rx_lock);
498 spin_lock_init(&dev->mt76.lock);
499 spin_lock_init(&dev->mac_lock);
500 spin_lock_init(&dev->con_mon_lock);
501 atomic_set(&dev->avg_ampdu_len, 1);
502 skb_queue_head_init(&dev->tx_skb_done);
503
504 dev->stat_wq = alloc_workqueue("mt76x0", WQ_UNBOUND, 0);
505 if (!dev->stat_wq) {
506 ieee80211_free_hw(hw);
507 return NULL;
508 }
509
510 return dev;
511 }
512
513 #define CHAN2G(_idx, _freq) { \
514 .band = NL80211_BAND_2GHZ, \
515 .center_freq = (_freq), \
516 .hw_value = (_idx), \
517 .max_power = 30, \
518 }
519
520 static const struct ieee80211_channel mt76_channels_2ghz[] = {
521 CHAN2G(1, 2412),
522 CHAN2G(2, 2417),
523 CHAN2G(3, 2422),
524 CHAN2G(4, 2427),
525 CHAN2G(5, 2432),
526 CHAN2G(6, 2437),
527 CHAN2G(7, 2442),
528 CHAN2G(8, 2447),
529 CHAN2G(9, 2452),
530 CHAN2G(10, 2457),
531 CHAN2G(11, 2462),
532 CHAN2G(12, 2467),
533 CHAN2G(13, 2472),
534 CHAN2G(14, 2484),
535 };
536
537 #define CHAN5G(_idx, _freq) { \
538 .band = NL80211_BAND_5GHZ, \
539 .center_freq = (_freq), \
540 .hw_value = (_idx), \
541 .max_power = 30, \
542 }
543
544 static const struct ieee80211_channel mt76_channels_5ghz[] = {
545 CHAN5G(36, 5180),
546 CHAN5G(40, 5200),
547 CHAN5G(44, 5220),
548 CHAN5G(46, 5230),
549 CHAN5G(48, 5240),
550 CHAN5G(52, 5260),
551 CHAN5G(56, 5280),
552 CHAN5G(60, 5300),
553 CHAN5G(64, 5320),
554
555 CHAN5G(100, 5500),
556 CHAN5G(104, 5520),
557 CHAN5G(108, 5540),
558 CHAN5G(112, 5560),
559 CHAN5G(116, 5580),
560 CHAN5G(120, 5600),
561 CHAN5G(124, 5620),
562 CHAN5G(128, 5640),
563 CHAN5G(132, 5660),
564 CHAN5G(136, 5680),
565 CHAN5G(140, 5700),
566 };
567
568 #define CCK_RATE(_idx, _rate) { \
569 .bitrate = _rate, \
570 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \
571 .hw_value = (MT_PHY_TYPE_CCK << 8) | _idx, \
572 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (8 + _idx), \
573 }
574
575 #define OFDM_RATE(_idx, _rate) { \
576 .bitrate = _rate, \
577 .hw_value = (MT_PHY_TYPE_OFDM << 8) | _idx, \
578 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | _idx, \
579 }
580
581 static struct ieee80211_rate mt76_rates[] = {
582 CCK_RATE(0, 10),
583 CCK_RATE(1, 20),
584 CCK_RATE(2, 55),
585 CCK_RATE(3, 110),
586 OFDM_RATE(0, 60),
587 OFDM_RATE(1, 90),
588 OFDM_RATE(2, 120),
589 OFDM_RATE(3, 180),
590 OFDM_RATE(4, 240),
591 OFDM_RATE(5, 360),
592 OFDM_RATE(6, 480),
593 OFDM_RATE(7, 540),
594 };
595
596 static int
mt76_init_sband(struct mt76x0_dev * dev,struct ieee80211_supported_band * sband,const struct ieee80211_channel * chan,int n_chan,struct ieee80211_rate * rates,int n_rates)597 mt76_init_sband(struct mt76x0_dev *dev, struct ieee80211_supported_band *sband,
598 const struct ieee80211_channel *chan, int n_chan,
599 struct ieee80211_rate *rates, int n_rates)
600 {
601 struct ieee80211_sta_ht_cap *ht_cap;
602 void *chanlist;
603 int size;
604
605 size = n_chan * sizeof(*chan);
606 chanlist = devm_kmemdup(dev->mt76.dev, chan, size, GFP_KERNEL);
607 if (!chanlist)
608 return -ENOMEM;
609
610 sband->channels = chanlist;
611 sband->n_channels = n_chan;
612 sband->bitrates = rates;
613 sband->n_bitrates = n_rates;
614
615 ht_cap = &sband->ht_cap;
616 ht_cap->ht_supported = true;
617 ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
618 IEEE80211_HT_CAP_GRN_FLD |
619 IEEE80211_HT_CAP_SGI_20 |
620 IEEE80211_HT_CAP_SGI_40 |
621 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
622
623 ht_cap->mcs.rx_mask[0] = 0xff;
624 ht_cap->mcs.rx_mask[4] = 0x1;
625 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
626 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
627 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_2;
628
629 return 0;
630 }
631
632 static int
mt76_init_sband_2g(struct mt76x0_dev * dev)633 mt76_init_sband_2g(struct mt76x0_dev *dev)
634 {
635 dev->mt76.hw->wiphy->bands[NL80211_BAND_2GHZ] = &dev->mt76.sband_2g.sband;
636
637 WARN_ON(dev->ee->reg.start - 1 + dev->ee->reg.num >
638 ARRAY_SIZE(mt76_channels_2ghz));
639
640
641 return mt76_init_sband(dev, &dev->mt76.sband_2g.sband,
642 mt76_channels_2ghz, ARRAY_SIZE(mt76_channels_2ghz),
643 mt76_rates, ARRAY_SIZE(mt76_rates));
644 }
645
646 static int
mt76_init_sband_5g(struct mt76x0_dev * dev)647 mt76_init_sband_5g(struct mt76x0_dev *dev)
648 {
649 dev->mt76.hw->wiphy->bands[NL80211_BAND_5GHZ] = &dev->mt76.sband_5g.sband;
650
651 return mt76_init_sband(dev, &dev->mt76.sband_5g.sband,
652 mt76_channels_5ghz, ARRAY_SIZE(mt76_channels_5ghz),
653 mt76_rates + 4, ARRAY_SIZE(mt76_rates) - 4);
654 }
655
656
mt76x0_register_device(struct mt76x0_dev * dev)657 int mt76x0_register_device(struct mt76x0_dev *dev)
658 {
659 struct ieee80211_hw *hw = dev->mt76.hw;
660 struct wiphy *wiphy = hw->wiphy;
661 int ret;
662
663 /* Reserve WCID 0 for mcast - thanks to this APs WCID will go to
664 * entry no. 1 like it does in the vendor driver.
665 */
666 dev->wcid_mask[0] |= 1;
667
668 /* init fake wcid for monitor interfaces */
669 dev->mon_wcid = devm_kmalloc(dev->mt76.dev, sizeof(*dev->mon_wcid),
670 GFP_KERNEL);
671 if (!dev->mon_wcid)
672 return -ENOMEM;
673 dev->mon_wcid->idx = 0xff;
674 dev->mon_wcid->hw_key_idx = -1;
675
676 SET_IEEE80211_DEV(hw, dev->mt76.dev);
677
678 hw->queues = 4;
679 ieee80211_hw_set(hw, SIGNAL_DBM);
680 ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
681 ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
682 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
683 ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
684 hw->max_rates = 1;
685 hw->max_report_rates = 7;
686 hw->max_rate_tries = 1;
687
688 hw->sta_data_size = sizeof(struct mt76_sta);
689 hw->vif_data_size = sizeof(struct mt76_vif);
690
691 SET_IEEE80211_PERM_ADDR(hw, dev->macaddr);
692
693 wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR;
694 wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
695
696 if (dev->ee->has_2ghz) {
697 ret = mt76_init_sband_2g(dev);
698 if (ret)
699 return ret;
700 }
701
702 if (dev->ee->has_5ghz) {
703 ret = mt76_init_sband_5g(dev);
704 if (ret)
705 return ret;
706 }
707
708 dev->mt76.chandef.chan = &dev->mt76.sband_2g.sband.channels[0];
709
710 INIT_DELAYED_WORK(&dev->mac_work, mt76x0_mac_work);
711 INIT_DELAYED_WORK(&dev->stat_work, mt76x0_tx_stat);
712
713 ret = ieee80211_register_hw(hw);
714 if (ret)
715 return ret;
716
717 mt76x0_init_debugfs(dev);
718
719 return 0;
720 }
721
