1 /****************************************************************************** 2 * This software may be used and distributed according to the terms of 3 * the GNU General Public License (GPL), incorporated herein by reference. 4 * Drivers based on or derived from this code fall under the GPL and must 5 * retain the authorship, copyright and license notice. This file is not 6 * a complete program and may only be used when the entire operating 7 * system is licensed under the GPL. 8 * See the file COPYING in this distribution for more information. 9 * 10 * vxge-reg.h: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O Virtualized 11 * Server Adapter. 12 * Copyright(c) 2002-2010 Exar Corp. 13 ******************************************************************************/ 14 #ifndef VXGE_REG_H 15 #define VXGE_REG_H 16 17 /* 18 * vxge_mBIT(loc) - set bit at offset 19 */ 20 #define vxge_mBIT(loc) (0x8000000000000000ULL >> (loc)) 21 22 /* 23 * vxge_vBIT(val, loc, sz) - set bits at offset 24 */ 25 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) 26 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) 27 28 /* 29 * vxge_bVALn(bits, loc, n) - Get the value of n bits at location 30 */ 31 #define vxge_bVALn(bits, loc, n) \ 32 ((((u64)bits) >> (64-(loc+n))) & ((0x1ULL << n) - 1)) 33 34 #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(bits) \ 35 vxge_bVALn(bits, 0, 16) 36 #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(bits) \ 37 vxge_bVALn(bits, 48, 8) 38 #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(bits) \ 39 vxge_bVALn(bits, 56, 8) 40 41 #define VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(bits) \ 42 vxge_bVALn(bits, 3, 5) 43 #define VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(bits) \ 44 vxge_bVALn(bits, 5, 3) 45 #define VXGE_HW_PF_SW_RESET_COMMAND 0xA5 46 47 #define VXGE_HW_TITAN_PCICFGMGMT_REG_SPACES 17 48 #define VXGE_HW_TITAN_SRPCIM_REG_SPACES 17 49 #define VXGE_HW_TITAN_VPMGMT_REG_SPACES 17 50 #define VXGE_HW_TITAN_VPATH_REG_SPACES 17 51 52 #define VXGE_HW_FW_API_GET_EPROM_REV 31 53 54 #define VXGE_EPROM_IMG_MAJOR(val) (u32) vxge_bVALn(val, 48, 4) 55 #define VXGE_EPROM_IMG_MINOR(val) (u32) vxge_bVALn(val, 52, 4) 56 #define VXGE_EPROM_IMG_FIX(val) (u32) vxge_bVALn(val, 56, 4) 57 #define VXGE_EPROM_IMG_BUILD(val) (u32) vxge_bVALn(val, 60, 4) 58 59 #define VXGE_HW_GET_EPROM_IMAGE_INDEX(val) vxge_bVALn(val, 16, 8) 60 #define VXGE_HW_GET_EPROM_IMAGE_VALID(val) vxge_bVALn(val, 31, 1) 61 #define VXGE_HW_GET_EPROM_IMAGE_TYPE(val) vxge_bVALn(val, 40, 8) 62 #define VXGE_HW_GET_EPROM_IMAGE_REV(val) vxge_bVALn(val, 48, 16) 63 #define VXGE_HW_RTS_ACCESS_STEER_ROM_IMAGE_INDEX(val) vxge_vBIT(val, 16, 8) 64 65 #define VXGE_HW_FW_API_GET_FUNC_MODE 29 66 #define VXGE_HW_GET_FUNC_MODE_VAL(val) (val & 0xFF) 67 68 #define VXGE_HW_FW_UPGRADE_MEMO 13 69 #define VXGE_HW_FW_UPGRADE_ACTION 16 70 #define VXGE_HW_FW_UPGRADE_OFFSET_START 2 71 #define VXGE_HW_FW_UPGRADE_OFFSET_SEND 3 72 #define VXGE_HW_FW_UPGRADE_OFFSET_COMMIT 4 73 #define VXGE_HW_FW_UPGRADE_OFFSET_READ 5 74 75 #define VXGE_HW_FW_UPGRADE_BLK_SIZE 16 76 #define VXGE_HW_UPGRADE_GET_RET_ERR_CODE(val) (val & 0xff) 77 #define VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(val) ((val >> 8) & 0xff) 78 79 #define VXGE_HW_ASIC_MODE_RESERVED 0 80 #define VXGE_HW_ASIC_MODE_NO_IOV 1 81 #define VXGE_HW_ASIC_MODE_SR_IOV 2 82 #define VXGE_HW_ASIC_MODE_MR_IOV 3 83 84 #define VXGE_HW_TXMAC_GEN_CFG1_TMAC_PERMA_STOP_EN vxge_mBIT(3) 85 #define VXGE_HW_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_WIRE vxge_mBIT(19) 86 #define VXGE_HW_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_SWITCH vxge_mBIT(23) 87 #define VXGE_HW_TXMAC_GEN_CFG1_HOST_APPEND_FCS vxge_mBIT(31) 88 89 #define VXGE_HW_VPATH_IS_FIRST_GET_VPATH_IS_FIRST(bits) vxge_bVALn(bits, 3, 1) 90 91 #define VXGE_HW_TIM_VPATH_ASSIGNMENT_GET_BMAP_ROOT(bits) \ 92 vxge_bVALn(bits, 0, 32) 93 94 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN(bits) \ 95 vxge_bVALn(bits, 50, 14) 96 97 #define VXGE_HW_XMAC_VSPORT_CHOICES_VP_GET_VSPORT_VECTOR(bits) \ 98 vxge_bVALn(bits, 0, 17) 99 100 #define VXGE_HW_XMAC_VPATH_TO_VSPORT_VPMGMT_CLONE_GET_VSPORT_NUMBER(bits) \ 101 vxge_bVALn(bits, 3, 5) 102 103 #define VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(bits) \ 104 vxge_bVALn(bits, 17, 15) 105 106 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_LEGACY_MODE 0 107 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY 1 108 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_MULTI_OP_MODE 2 109 110 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE_MESSAGES_ONLY 0 111 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE_MULTI_OP_MODE 1 112 113 #define VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val) \ 114 (val&~VXGE_HW_TOC_KDFC_INITIAL_BIR(7)) 115 #define VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val) \ 116 vxge_bVALn(val, 61, 3) 117 #define VXGE_HW_TOC_GET_USDC_INITIAL_OFFSET(val) \ 118 (val&~VXGE_HW_TOC_USDC_INITIAL_BIR(7)) 119 #define VXGE_HW_TOC_GET_USDC_INITIAL_BIR(val) \ 120 vxge_bVALn(val, 61, 3) 121 122 #define VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(bits) bits 123 #define VXGE_HW_TOC_KDFC_FIFO_STRIDE_GET_TOC_KDFC_FIFO_STRIDE(bits) bits 124 125 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR0(bits) \ 126 vxge_bVALn(bits, 1, 15) 127 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR1(bits) \ 128 vxge_bVALn(bits, 17, 15) 129 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR2(bits) \ 130 vxge_bVALn(bits, 33, 15) 131 132 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_VAPTH_NUM(val) vxge_vBIT(val, 42, 5) 133 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_NUM(val) vxge_vBIT(val, 47, 2) 134 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_OFFSET(val) \ 135 vxge_vBIT(val, 49, 15) 136 137 #define VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER 0 138 #define VXGE_HW_PRC_CFG4_RING_MODE_THREE_BUFFER 1 139 #define VXGE_HW_PRC_CFG4_RING_MODE_FIVE_BUFFER 2 140 141 #define VXGE_HW_PRC_CFG7_SCATTER_MODE_A 0 142 #define VXGE_HW_PRC_CFG7_SCATTER_MODE_B 2 143 #define VXGE_HW_PRC_CFG7_SCATTER_MODE_C 1 144 145 #define VXGE_HW_RTS_MGR_STEER_CTRL_WE_READ 0 146 #define VXGE_HW_RTS_MGR_STEER_CTRL_WE_WRITE 1 147 148 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DA 0 149 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_VID 1 150 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_ETYPE 2 151 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_PN 3 152 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RANGE_PN 4 153 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG 5 154 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT 6 155 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG 7 156 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK 8 157 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY 9 158 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_QOS 10 159 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DS 11 160 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT 12 161 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_FW_VERSION 13 162 163 #define VXGE_HW_RTS_MGR_STEER_DATA0_GET_DA_MAC_ADDR(bits) \ 164 vxge_bVALn(bits, 0, 48) 165 #define VXGE_HW_RTS_MGR_STEER_DATA0_DA_MAC_ADDR(val) vxge_vBIT(val, 0, 48) 166 167 #define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits) \ 168 vxge_bVALn(bits, 0, 48) 169 #define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MASK(val) vxge_vBIT(val, 0, 48) 170 #define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_PRIVILEGED_MODE \ 171 vxge_mBIT(54) 172 #define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_VPATH(bits) \ 173 vxge_bVALn(bits, 55, 5) 174 #define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_VPATH(val) \ 175 vxge_vBIT(val, 55, 5) 176 #define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_MODE(bits) \ 177 vxge_bVALn(bits, 62, 2) 178 #define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MODE(val) vxge_vBIT(val, 62, 2) 179 180 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY 0 181 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY 1 182 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY 2 183 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY 3 184 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY 0 185 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY 1 186 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY 3 187 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL 4 188 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ALL_CLEAR 172 189 190 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA 0 191 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID 1 192 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE 2 193 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN 3 194 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG 5 195 #define VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT 6 196 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG 7 197 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK 8 198 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY 9 199 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_QOS 10 200 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DS 11 201 #define VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT 12 202 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO 13 203 204 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(bits) \ 205 vxge_bVALn(bits, 0, 48) 206 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(val) vxge_vBIT(val, 0, 48) 207 208 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(bits) vxge_bVALn(bits, 0, 12) 209 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(val) vxge_vBIT(val, 0, 12) 210 211 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_ETYPE(bits) vxge_bVALn(bits, 0, 11) 212 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_ETYPE(val) vxge_vBIT(val, 0, 16) 213 214 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL(bits) \ 215 vxge_bVALn(bits, 3, 1) 216 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_SRC_DEST_SEL vxge_mBIT(3) 217 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL(bits) \ 218 vxge_bVALn(bits, 7, 1) 219 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_TCP_UDP_SEL vxge_mBIT(7) 220 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM(bits) \ 221 vxge_bVALn(bits, 8, 16) 222 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_PORT_NUM(val) vxge_vBIT(val, 8, 16) 223 224 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_EN(bits) \ 225 vxge_bVALn(bits, 3, 1) 226 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN vxge_mBIT(3) 227 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_BUCKET_SIZE(bits) \ 228 vxge_bVALn(bits, 4, 4) 229 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(val) \ 230 vxge_vBIT(val, 4, 4) 231 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ALG_SEL(bits) \ 232 vxge_bVALn(bits, 10, 2) 233 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(val) \ 234 vxge_vBIT(val, 10, 2) 235 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_JENKINS 0 236 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_MS_RSS 1 237 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_CRC32C 2 238 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV4_EN(bits) \ 239 vxge_bVALn(bits, 15, 1) 240 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN vxge_mBIT(15) 241 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV4_EN(bits) \ 242 vxge_bVALn(bits, 19, 1) 243 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN vxge_mBIT(19) 244 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EN(bits) \ 245 vxge_bVALn(bits, 23, 1) 246 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN vxge_mBIT(23) 247 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EN(bits) \ 248 vxge_bVALn(bits, 27, 1) 249 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN vxge_mBIT(27) 250 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EX_EN(bits) \ 251 vxge_bVALn(bits, 31, 1) 252 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN vxge_mBIT(31) 253 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EX_EN(bits) \ 254 vxge_bVALn(bits, 35, 1) 255 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN vxge_mBIT(35) 256 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(bits) \ 257 vxge_bVALn(bits, 39, 1) 258 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE vxge_mBIT(39) 259 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_REPL_ENTRY_EN(bits) \ 260 vxge_bVALn(bits, 43, 1) 261 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_REPL_ENTRY_EN vxge_mBIT(43) 262 263 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_ENTRY_EN(bits) \ 264 vxge_bVALn(bits, 3, 1) 265 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN vxge_mBIT(3) 266 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_BUCKET_DATA(bits) \ 267 vxge_bVALn(bits, 9, 7) 268 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(val) \ 269 vxge_vBIT(val, 9, 7) 270 271 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_NUM(bits) \ 272 vxge_bVALn(bits, 0, 8) 273 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(val) \ 274 vxge_vBIT(val, 0, 8) 275 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_ENTRY_EN(bits) \ 276 vxge_bVALn(bits, 8, 1) 277 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN vxge_mBIT(8) 278 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_DATA(bits) \ 279 vxge_bVALn(bits, 9, 7) 280 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(val) \ 281 vxge_vBIT(val, 9, 7) 282 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_NUM(bits) \ 283 vxge_bVALn(bits, 16, 8) 284 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(val) \ 285 vxge_vBIT(val, 16, 8) 286 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_ENTRY_EN(bits) \ 287 vxge_bVALn(bits, 24, 1) 288 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN vxge_mBIT(24) 289 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_DATA(bits) \ 290 vxge_bVALn(bits, 25, 7) 291 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(val) \ 292 vxge_vBIT(val, 25, 7) 293 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_NUM(bits) \ 294 vxge_bVALn(bits, 0, 8) 295 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(val) \ 296 vxge_vBIT(val, 0, 8) 297 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_ENTRY_EN(bits) \ 298 vxge_bVALn(bits, 8, 1) 299 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN vxge_mBIT(8) 300 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_DATA(bits) \ 301 vxge_bVALn(bits, 9, 7) 302 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(val) \ 303 vxge_vBIT(val, 9, 7) 304 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_NUM(bits) \ 305 vxge_bVALn(bits, 16, 8) 306 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(val) \ 307 vxge_vBIT(val, 16, 8) 308 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_ENTRY_EN(bits) \ 309 vxge_bVALn(bits, 24, 1) 310 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN vxge_mBIT(24) 311 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_DATA(bits) \ 312 vxge_bVALn(bits, 25, 7) 313 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(val) \ 314 vxge_vBIT(val, 25, 7) 315 316 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_GOLDEN_RATIO(bits) \ 317 vxge_bVALn(bits, 0, 32) 318 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_GOLDEN_RATIO(val) \ 319 vxge_vBIT(val, 0, 32) 320 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_INIT_VALUE(bits) \ 321 vxge_bVALn(bits, 32, 32) 322 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_INIT_VALUE(val) \ 323 vxge_vBIT(val, 32, 32) 324 325 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_SA_MASK(bits) \ 326 vxge_bVALn(bits, 0, 16) 327 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_SA_MASK(val) \ 328 vxge_vBIT(val, 0, 16) 329 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_DA_MASK(bits) \ 330 vxge_bVALn(bits, 16, 16) 331 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_DA_MASK(val) \ 332 vxge_vBIT(val, 16, 16) 333 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_SA_MASK(bits) \ 334 vxge_bVALn(bits, 32, 4) 335 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_SA_MASK(val) \ 336 vxge_vBIT(val, 32, 4) 337 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_DA_MASK(bits) \ 338 vxge_bVALn(bits, 36, 4) 339 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_DA_MASK(val) \ 340 vxge_vBIT(val, 36, 4) 341 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4SP_MASK(bits) \ 342 vxge_bVALn(bits, 40, 2) 343 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4SP_MASK(val) \ 344 vxge_vBIT(val, 40, 2) 345 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4DP_MASK(bits) \ 346 vxge_bVALn(bits, 42, 2) 347 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4DP_MASK(val) \ 348 vxge_vBIT(val, 42, 2) 349 350 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_KEY_KEY(bits) \ 351 vxge_bVALn(bits, 0, 64) 352 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_KEY_KEY vxge_vBIT(val, 0, 64) 353 354 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_QOS_ENTRY_EN(bits) \ 355 vxge_bVALn(bits, 3, 1) 356 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_QOS_ENTRY_EN vxge_mBIT(3) 357 358 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DS_ENTRY_EN(bits) \ 359 vxge_bVALn(bits, 3, 1) 360 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_DS_ENTRY_EN vxge_mBIT(3) 361 362 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits) \ 363 vxge_bVALn(bits, 0, 48) 364 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(val) \ 365 vxge_vBIT(val, 0, 48) 366 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(val) \ 367 vxge_vBIT(val, 62, 2) 368 369 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_NUM(bits) \ 370 vxge_bVALn(bits, 0, 8) 371 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_NUM(val) \ 372 vxge_vBIT(val, 0, 8) 373 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_ENTRY_EN(bits) \ 374 vxge_bVALn(bits, 8, 1) 375 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_ENTRY_EN vxge_mBIT(8) 376 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_DATA(bits) \ 377 vxge_bVALn(bits, 9, 7) 378 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_DATA(val) \ 379 vxge_vBIT(val, 9, 7) 380 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_NUM(bits) \ 381 vxge_bVALn(bits, 16, 8) 382 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_NUM(val) \ 383 vxge_vBIT(val, 16, 8) 384 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_ENTRY_EN(bits) \ 385 vxge_bVALn(bits, 24, 1) 386 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_ENTRY_EN vxge_mBIT(24) 387 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_DATA(bits) \ 388 vxge_bVALn(bits, 25, 7) 389 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_DATA(val) \ 390 vxge_vBIT(val, 25, 7) 391 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_NUM(bits) \ 392 vxge_bVALn(bits, 32, 8) 393 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_NUM(val) \ 394 vxge_vBIT(val, 32, 8) 395 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_ENTRY_EN(bits) \ 396 vxge_bVALn(bits, 40, 1) 397 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_ENTRY_EN vxge_mBIT(40) 398 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_DATA(bits) \ 399 vxge_bVALn(bits, 41, 7) 400 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_DATA(val) \ 401 vxge_vBIT(val, 41, 7) 402 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_NUM(bits) \ 403 vxge_bVALn(bits, 48, 8) 404 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_NUM(val) \ 405 vxge_vBIT(val, 48, 8) 406 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_ENTRY_EN(bits) \ 407 vxge_bVALn(bits, 56, 1) 408 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_ENTRY_EN vxge_mBIT(56) 409 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_DATA(bits) \ 410 vxge_bVALn(bits, 57, 7) 411 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_DATA(val) \ 412 vxge_vBIT(val, 57, 7) 413 414 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER 0 415 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER 1 416 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_VERSION 2 417 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PCI_MODE 3 418 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0 4 419 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_1 5 420 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_2 6 421 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3 7 422 423 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_LED_CONTROL_ON 1 424 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_LED_CONTROL_OFF 0 425 426 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(bits) \ 427 vxge_bVALn(bits, 0, 8) 428 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_DAY(val) vxge_vBIT(val, 0, 8) 429 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(bits) \ 430 vxge_bVALn(bits, 8, 8) 431 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MONTH(val) vxge_vBIT(val, 8, 8) 432 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(bits) \ 433 vxge_bVALn(bits, 16, 16) 434 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_YEAR(val) \ 435 vxge_vBIT(val, 16, 16) 436 437 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(bits) \ 438 vxge_bVALn(bits, 32, 8) 439 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MAJOR vxge_vBIT(val, 32, 8) 440 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(bits) \ 441 vxge_bVALn(bits, 40, 8) 442 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MINOR vxge_vBIT(val, 40, 8) 443 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(bits) \ 444 vxge_bVALn(bits, 48, 16) 445 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_BUILD vxge_vBIT(val, 48, 16) 446 447 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(bits) \ 448 vxge_bVALn(bits, 0, 8) 449 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_DAY(val) vxge_vBIT(val, 0, 8) 450 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(bits) \ 451 vxge_bVALn(bits, 8, 8) 452 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MONTH(val) vxge_vBIT(val, 8, 8) 453 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(bits) \ 454 vxge_bVALn(bits, 16, 16) 455 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_YEAR(val) \ 456 vxge_vBIT(val, 16, 16) 457 458 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(bits) \ 459 vxge_bVALn(bits, 32, 8) 460 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MAJOR vxge_vBIT(val, 32, 8) 461 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(bits) \ 462 vxge_bVALn(bits, 40, 8) 463 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MINOR vxge_vBIT(val, 40, 8) 464 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(bits) \ 465 vxge_bVALn(bits, 48, 16) 466 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_BUILD vxge_vBIT(val, 48, 16) 467 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION(bits) vxge_bVALn(bits, 0, 8) 468 469 #define VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_GET_PPIF_SRPCIM_TO_VPATH_ALARM(bits)\ 470 vxge_bVALn(bits, 0, 18) 471 472 #define VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(bits) \ 473 vxge_bVALn(bits, 48, 16) 474 #define VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(bits) \ 475 vxge_bVALn(bits, 32, 32) 476 #define VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(bits) vxge_bVALn(bits, 48, 16) 477 #define VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(bits) \ 478 vxge_bVALn(bits, 0, 32) 479 #define VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(bits) \ 480 vxge_bVALn(bits, 0, 32) 481 #define VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(bits) \ 482 vxge_bVALn(bits, 0, 32) 483 #define VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(bits) (bits) 484 #define VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(bits) (bits) 485 #define VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(bits) \ 486 vxge_bVALn(bits, 32, 32) 487 #define VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(bits) \ 488 vxge_bVALn(bits, 32, 32) 489 #define VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(bits) \ 490 vxge_bVALn(bits, 0, 32) 491 #define VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(bits) \ 492 vxge_bVALn(bits, 32, 32) 493 #define VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(bits) \ 494 vxge_bVALn(bits, 0, 32) 495 #define VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(bits) \ 496 vxge_bVALn(bits, 32, 32) 497 #define VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(bits) \ 498 vxge_bVALn(bits, 0, 32) 499 #define VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(bits) \ 500 vxge_bVALn(bits, 32, 32) 501 #define VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(bits\ 502 ) vxge_bVALn(bits, 48, 16) 503 #define VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(bits) vxge_bVALn(bits, 0, 16) 504 #define VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(bits) \ 505 vxge_bVALn(bits, 16, 16) 506 #define VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(bits) \ 507 vxge_bVALn(bits, 32, 16) 508 #define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(bits) vxge_bVALn(bits, 0, 16) 509 #define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(bits) \ 510 vxge_bVALn(bits, 16, 16) 511 #define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(bits) \ 512 vxge_bVALn(bits, 32, 16) 513 514 #define VXGE_HW_MRPCIM_DEBUG_STATS0_GET_INI_WR_DROP(bits) \ 515 vxge_bVALn(bits, 0, 32) 516 #define VXGE_HW_MRPCIM_DEBUG_STATS0_GET_INI_RD_DROP(bits) \ 517 vxge_bVALn(bits, 32, 32) 518 #define VXGE_HW_MRPCIM_DEBUG_STATS1_GET_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(bits\ 519 ) vxge_bVALn(bits, 32, 32) 520 #define VXGE_HW_MRPCIM_DEBUG_STATS2_GET_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(bits\ 521 ) vxge_bVALn(bits, 32, 32) 522 #define \ 523 VXGE_HW_MRPCIM_DEBUG_STATS3_GET_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(bits) \ 524 vxge_bVALn(bits, 32, 32) 525 #define VXGE_HW_MRPCIM_DEBUG_STATS4_GET_INI_WR_VPIN_DROP(bits) \ 526 vxge_bVALn(bits, 0, 32) 527 #define VXGE_HW_MRPCIM_DEBUG_STATS4_GET_INI_RD_VPIN_DROP(bits) \ 528 vxge_bVALn(bits, 32, 32) 529 #define VXGE_HW_GENSTATS_COUNT01_GET_GENSTATS_COUNT1(bits) \ 530 vxge_bVALn(bits, 0, 32) 531 #define VXGE_HW_GENSTATS_COUNT01_GET_GENSTATS_COUNT0(bits) \ 532 vxge_bVALn(bits, 32, 32) 533 #define VXGE_HW_GENSTATS_COUNT23_GET_GENSTATS_COUNT3(bits) \ 534 vxge_bVALn(bits, 0, 32) 535 #define VXGE_HW_GENSTATS_COUNT23_GET_GENSTATS_COUNT2(bits) \ 536 vxge_bVALn(bits, 32, 32) 537 #define VXGE_HW_GENSTATS_COUNT4_GET_GENSTATS_COUNT4(bits) \ 538 vxge_bVALn(bits, 32, 32) 539 #define VXGE_HW_GENSTATS_COUNT5_GET_GENSTATS_COUNT5(bits) \ 540 vxge_bVALn(bits, 32, 32) 541 542 #define VXGE_HW_DEBUG_STATS0_GET_RSTDROP_MSG(bits) vxge_bVALn(bits, 0, 32) 543 #define VXGE_HW_DEBUG_STATS0_GET_RSTDROP_CPL(bits) vxge_bVALn(bits, 32, 32) 544 #define VXGE_HW_DEBUG_STATS1_GET_RSTDROP_CLIENT0(bits) vxge_bVALn(bits, 0, 32) 545 #define VXGE_HW_DEBUG_STATS1_GET_RSTDROP_CLIENT1(bits) vxge_bVALn(bits, 32, 32) 546 #define VXGE_HW_DEBUG_STATS2_GET_RSTDROP_CLIENT2(bits) vxge_bVALn(bits, 0, 32) 547 #define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_PH(bits) vxge_bVALn(bits, 0, 16) 548 #define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_NPH(bits) vxge_bVALn(bits, 16, 16) 549 #define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_CPLH(bits) vxge_bVALn(bits, 32, 16) 550 #define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_PD(bits) vxge_bVALn(bits, 0, 16) 551 #define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_NPD(bits) bVAL(bits, 16, 16) 552 #define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_CPLD(bits) vxge_bVALn(bits, 32, 16) 553 554 #define VXGE_HW_DBG_STATS_TPA_TX_PATH_GET_TX_PERMITTED_FRMS(bits) \ 555 vxge_bVALn(bits, 32, 32) 556 557 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT0_TX_ANY_FRMS(bits) \ 558 vxge_bVALn(bits, 0, 8) 559 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT1_TX_ANY_FRMS(bits) \ 560 vxge_bVALn(bits, 8, 8) 561 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT2_TX_ANY_FRMS(bits) \ 562 vxge_bVALn(bits, 16, 8) 563 564 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT0_RX_ANY_FRMS(bits) \ 565 vxge_bVALn(bits, 0, 8) 566 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT1_RX_ANY_FRMS(bits) \ 567 vxge_bVALn(bits, 8, 8) 568 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT2_RX_ANY_FRMS(bits) \ 569 vxge_bVALn(bits, 16, 8) 570 571 #define VXGE_HW_CONFIG_PRIV_H 572 573 #define VXGE_HW_SWAPPER_INITIAL_VALUE 0x0123456789abcdefULL 574 #define VXGE_HW_SWAPPER_BYTE_SWAPPED 0xefcdab8967452301ULL 575 #define VXGE_HW_SWAPPER_BIT_FLIPPED 0x80c4a2e691d5b3f7ULL 576 #define VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED 0xf7b3d591e6a2c480ULL 577 578 #define VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE 0xFFFFFFFFFFFFFFFFULL 579 #define VXGE_HW_SWAPPER_READ_BYTE_SWAP_DISABLE 0x0000000000000000ULL 580 581 #define VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE 0xFFFFFFFFFFFFFFFFULL 582 #define VXGE_HW_SWAPPER_READ_BIT_FLAP_DISABLE 0x0000000000000000ULL 583 584 #define VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE 0xFFFFFFFFFFFFFFFFULL 585 #define VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_DISABLE 0x0000000000000000ULL 586 587 #define VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE 0xFFFFFFFFFFFFFFFFULL 588 #define VXGE_HW_SWAPPER_WRITE_BIT_FLAP_DISABLE 0x0000000000000000ULL 589 590 /* 591 * The registers are memory mapped and are native big-endian byte order. The 592 * little-endian hosts are handled by enabling hardware byte-swapping for 593 * register and dma operations. 594 */ 595 struct vxge_hw_legacy_reg { 596 597 u8 unused00010[0x00010]; 598 599 /*0x00010*/ u64 toc_swapper_fb; 600 #define VXGE_HW_TOC_SWAPPER_FB_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) 601 /*0x00018*/ u64 pifm_rd_swap_en; 602 #define VXGE_HW_PIFM_RD_SWAP_EN_PIFM_RD_SWAP_EN(val) vxge_vBIT(val, 0, 64) 603 /*0x00020*/ u64 pifm_rd_flip_en; 604 #define VXGE_HW_PIFM_RD_FLIP_EN_PIFM_RD_FLIP_EN(val) vxge_vBIT(val, 0, 64) 605 /*0x00028*/ u64 pifm_wr_swap_en; 606 #define VXGE_HW_PIFM_WR_SWAP_EN_PIFM_WR_SWAP_EN(val) vxge_vBIT(val, 0, 64) 607 /*0x00030*/ u64 pifm_wr_flip_en; 608 #define VXGE_HW_PIFM_WR_FLIP_EN_PIFM_WR_FLIP_EN(val) vxge_vBIT(val, 0, 64) 609 /*0x00038*/ u64 toc_first_pointer; 610 #define VXGE_HW_TOC_FIRST_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) 611 /*0x00040*/ u64 host_access_en; 612 #define VXGE_HW_HOST_ACCESS_EN_HOST_ACCESS_EN(val) vxge_vBIT(val, 0, 64) 613 614 } __packed; 615 616 struct vxge_hw_toc_reg { 617 618 u8 unused00050[0x00050]; 619 620 /*0x00050*/ u64 toc_common_pointer; 621 #define VXGE_HW_TOC_COMMON_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) 622 /*0x00058*/ u64 toc_memrepair_pointer; 623 #define VXGE_HW_TOC_MEMREPAIR_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) 624 /*0x00060*/ u64 toc_pcicfgmgmt_pointer[17]; 625 #define VXGE_HW_TOC_PCICFGMGMT_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) 626 u8 unused001e0[0x001e0-0x000e8]; 627 628 /*0x001e0*/ u64 toc_mrpcim_pointer; 629 #define VXGE_HW_TOC_MRPCIM_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) 630 /*0x001e8*/ u64 toc_srpcim_pointer[17]; 631 #define VXGE_HW_TOC_SRPCIM_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) 632 u8 unused00278[0x00278-0x00270]; 633 634 /*0x00278*/ u64 toc_vpmgmt_pointer[17]; 635 #define VXGE_HW_TOC_VPMGMT_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) 636 u8 unused00390[0x00390-0x00300]; 637 638 /*0x00390*/ u64 toc_vpath_pointer[17]; 639 #define VXGE_HW_TOC_VPATH_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) 640 u8 unused004a0[0x004a0-0x00418]; 641 642 /*0x004a0*/ u64 toc_kdfc; 643 #define VXGE_HW_TOC_KDFC_INITIAL_OFFSET(val) vxge_vBIT(val, 0, 61) 644 #define VXGE_HW_TOC_KDFC_INITIAL_BIR(val) vxge_vBIT(val, 61, 3) 645 /*0x004a8*/ u64 toc_usdc; 646 #define VXGE_HW_TOC_USDC_INITIAL_OFFSET(val) vxge_vBIT(val, 0, 61) 647 #define VXGE_HW_TOC_USDC_INITIAL_BIR(val) vxge_vBIT(val, 61, 3) 648 /*0x004b0*/ u64 toc_kdfc_vpath_stride; 649 #define VXGE_HW_TOC_KDFC_VPATH_STRIDE_INITIAL_TOC_KDFC_VPATH_STRIDE(val) \ 650 vxge_vBIT(val, 0, 64) 651 /*0x004b8*/ u64 toc_kdfc_fifo_stride; 652 #define VXGE_HW_TOC_KDFC_FIFO_STRIDE_INITIAL_TOC_KDFC_FIFO_STRIDE(val) \ 653 vxge_vBIT(val, 0, 64) 654 655 } __packed; 656 657 struct vxge_hw_common_reg { 658 659 u8 unused00a00[0x00a00]; 660 661 /*0x00a00*/ u64 prc_status1; 662 #define VXGE_HW_PRC_STATUS1_PRC_VP_QUIESCENT(n) vxge_mBIT(n) 663 /*0x00a08*/ u64 rxdcm_reset_in_progress; 664 #define VXGE_HW_RXDCM_RESET_IN_PROGRESS_PRC_VP(n) vxge_mBIT(n) 665 /*0x00a10*/ u64 replicq_flush_in_progress; 666 #define VXGE_HW_REPLICQ_FLUSH_IN_PROGRESS_NOA_VP(n) vxge_mBIT(n) 667 /*0x00a18*/ u64 rxpe_cmds_reset_in_progress; 668 #define VXGE_HW_RXPE_CMDS_RESET_IN_PROGRESS_NOA_VP(n) vxge_mBIT(n) 669 /*0x00a20*/ u64 mxp_cmds_reset_in_progress; 670 #define VXGE_HW_MXP_CMDS_RESET_IN_PROGRESS_NOA_VP(n) vxge_mBIT(n) 671 /*0x00a28*/ u64 noffload_reset_in_progress; 672 #define VXGE_HW_NOFFLOAD_RESET_IN_PROGRESS_PRC_VP(n) vxge_mBIT(n) 673 /*0x00a30*/ u64 rd_req_in_progress; 674 #define VXGE_HW_RD_REQ_IN_PROGRESS_VP(n) vxge_mBIT(n) 675 /*0x00a38*/ u64 rd_req_outstanding; 676 #define VXGE_HW_RD_REQ_OUTSTANDING_VP(n) vxge_mBIT(n) 677 /*0x00a40*/ u64 kdfc_reset_in_progress; 678 #define VXGE_HW_KDFC_RESET_IN_PROGRESS_NOA_VP(n) vxge_mBIT(n) 679 u8 unused00b00[0x00b00-0x00a48]; 680 681 /*0x00b00*/ u64 one_cfg_vp; 682 #define VXGE_HW_ONE_CFG_VP_RDY(n) vxge_mBIT(n) 683 /*0x00b08*/ u64 one_common; 684 #define VXGE_HW_ONE_COMMON_PET_VPATH_RESET_IN_PROGRESS(n) vxge_mBIT(n) 685 u8 unused00b80[0x00b80-0x00b10]; 686 687 /*0x00b80*/ u64 tim_int_en; 688 #define VXGE_HW_TIM_INT_EN_TIM_VP(n) vxge_mBIT(n) 689 /*0x00b88*/ u64 tim_set_int_en; 690 #define VXGE_HW_TIM_SET_INT_EN_VP(n) vxge_mBIT(n) 691 /*0x00b90*/ u64 tim_clr_int_en; 692 #define VXGE_HW_TIM_CLR_INT_EN_VP(n) vxge_mBIT(n) 693 /*0x00b98*/ u64 tim_mask_int_during_reset; 694 #define VXGE_HW_TIM_MASK_INT_DURING_RESET_VPATH(n) vxge_mBIT(n) 695 /*0x00ba0*/ u64 tim_reset_in_progress; 696 #define VXGE_HW_TIM_RESET_IN_PROGRESS_TIM_VPATH(n) vxge_mBIT(n) 697 /*0x00ba8*/ u64 tim_outstanding_bmap; 698 #define VXGE_HW_TIM_OUTSTANDING_BMAP_TIM_VPATH(n) vxge_mBIT(n) 699 u8 unused00c00[0x00c00-0x00bb0]; 700 701 /*0x00c00*/ u64 msg_reset_in_progress; 702 #define VXGE_HW_MSG_RESET_IN_PROGRESS_MSG_COMPOSITE(val) vxge_vBIT(val, 0, 17) 703 /*0x00c08*/ u64 msg_mxp_mr_ready; 704 #define VXGE_HW_MSG_MXP_MR_READY_MP_BOOTED(n) vxge_mBIT(n) 705 /*0x00c10*/ u64 msg_uxp_mr_ready; 706 #define VXGE_HW_MSG_UXP_MR_READY_UP_BOOTED(n) vxge_mBIT(n) 707 /*0x00c18*/ u64 msg_dmq_noni_rtl_prefetch; 708 #define VXGE_HW_MSG_DMQ_NONI_RTL_PREFETCH_BYPASS_ENABLE(n) vxge_mBIT(n) 709 /*0x00c20*/ u64 msg_umq_rtl_bwr; 710 #define VXGE_HW_MSG_UMQ_RTL_BWR_PREFETCH_DISABLE(n) vxge_mBIT(n) 711 u8 unused00d00[0x00d00-0x00c28]; 712 713 /*0x00d00*/ u64 cmn_rsthdlr_cfg0; 714 #define VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(val) vxge_vBIT(val, 0, 17) 715 /*0x00d08*/ u64 cmn_rsthdlr_cfg1; 716 #define VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(val) vxge_vBIT(val, 0, 17) 717 /*0x00d10*/ u64 cmn_rsthdlr_cfg2; 718 #define VXGE_HW_CMN_RSTHDLR_CFG2_SW_RESET_FIFO0(val) vxge_vBIT(val, 0, 17) 719 /*0x00d18*/ u64 cmn_rsthdlr_cfg3; 720 #define VXGE_HW_CMN_RSTHDLR_CFG3_SW_RESET_FIFO1(val) vxge_vBIT(val, 0, 17) 721 /*0x00d20*/ u64 cmn_rsthdlr_cfg4; 722 #define VXGE_HW_CMN_RSTHDLR_CFG4_SW_RESET_FIFO2(val) vxge_vBIT(val, 0, 17) 723 u8 unused00d40[0x00d40-0x00d28]; 724 725 /*0x00d40*/ u64 cmn_rsthdlr_cfg8; 726 #define VXGE_HW_CMN_RSTHDLR_CFG8_INCR_VPATH_INST_NUM(val) vxge_vBIT(val, 0, 17) 727 /*0x00d48*/ u64 stats_cfg0; 728 #define VXGE_HW_STATS_CFG0_STATS_ENABLE(val) vxge_vBIT(val, 0, 17) 729 u8 unused00da8[0x00da8-0x00d50]; 730 731 /*0x00da8*/ u64 clear_msix_mask_vect[4]; 732 #define VXGE_HW_CLEAR_MSIX_MASK_VECT_CLEAR_MSIX_MASK_VECT(val) \ 733 vxge_vBIT(val, 0, 17) 734 /*0x00dc8*/ u64 set_msix_mask_vect[4]; 735 #define VXGE_HW_SET_MSIX_MASK_VECT_SET_MSIX_MASK_VECT(val) vxge_vBIT(val, 0, 17) 736 /*0x00de8*/ u64 clear_msix_mask_all_vect; 737 #define VXGE_HW_CLEAR_MSIX_MASK_ALL_VECT_CLEAR_MSIX_MASK_ALL_VECT(val) \ 738 vxge_vBIT(val, 0, 17) 739 /*0x00df0*/ u64 set_msix_mask_all_vect; 740 #define VXGE_HW_SET_MSIX_MASK_ALL_VECT_SET_MSIX_MASK_ALL_VECT(val) \ 741 vxge_vBIT(val, 0, 17) 742 /*0x00df8*/ u64 mask_vector[4]; 743 #define VXGE_HW_MASK_VECTOR_MASK_VECTOR(val) vxge_vBIT(val, 0, 17) 744 /*0x00e18*/ u64 msix_pending_vector[4]; 745 #define VXGE_HW_MSIX_PENDING_VECTOR_MSIX_PENDING_VECTOR(val) \ 746 vxge_vBIT(val, 0, 17) 747 /*0x00e38*/ u64 clr_msix_one_shot_vec[4]; 748 #define VXGE_HW_CLR_MSIX_ONE_SHOT_VEC_CLR_MSIX_ONE_SHOT_VEC(val) \ 749 vxge_vBIT(val, 0, 17) 750 /*0x00e58*/ u64 titan_asic_id; 751 #define VXGE_HW_TITAN_ASIC_ID_INITIAL_DEVICE_ID(val) vxge_vBIT(val, 0, 16) 752 #define VXGE_HW_TITAN_ASIC_ID_INITIAL_MAJOR_REVISION(val) vxge_vBIT(val, 48, 8) 753 #define VXGE_HW_TITAN_ASIC_ID_INITIAL_MINOR_REVISION(val) vxge_vBIT(val, 56, 8) 754 /*0x00e60*/ u64 titan_general_int_status; 755 #define VXGE_HW_TITAN_GENERAL_INT_STATUS_MRPCIM_ALARM_INT vxge_mBIT(0) 756 #define VXGE_HW_TITAN_GENERAL_INT_STATUS_SRPCIM_ALARM_INT vxge_mBIT(1) 757 #define VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT vxge_mBIT(2) 758 #define VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(val) \ 759 vxge_vBIT(val, 3, 17) 760 u8 unused00e70[0x00e70-0x00e68]; 761 762 /*0x00e70*/ u64 titan_mask_all_int; 763 #define VXGE_HW_TITAN_MASK_ALL_INT_ALARM vxge_mBIT(7) 764 #define VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC vxge_mBIT(15) 765 u8 unused00e80[0x00e80-0x00e78]; 766 767 /*0x00e80*/ u64 tim_int_status0; 768 #define VXGE_HW_TIM_INT_STATUS0_TIM_INT_STATUS0(val) vxge_vBIT(val, 0, 64) 769 /*0x00e88*/ u64 tim_int_mask0; 770 #define VXGE_HW_TIM_INT_MASK0_TIM_INT_MASK0(val) vxge_vBIT(val, 0, 64) 771 /*0x00e90*/ u64 tim_int_status1; 772 #define VXGE_HW_TIM_INT_STATUS1_TIM_INT_STATUS1(val) vxge_vBIT(val, 0, 4) 773 /*0x00e98*/ u64 tim_int_mask1; 774 #define VXGE_HW_TIM_INT_MASK1_TIM_INT_MASK1(val) vxge_vBIT(val, 0, 4) 775 /*0x00ea0*/ u64 rti_int_status; 776 #define VXGE_HW_RTI_INT_STATUS_RTI_INT_STATUS(val) vxge_vBIT(val, 0, 17) 777 /*0x00ea8*/ u64 rti_int_mask; 778 #define VXGE_HW_RTI_INT_MASK_RTI_INT_MASK(val) vxge_vBIT(val, 0, 17) 779 /*0x00eb0*/ u64 adapter_status; 780 #define VXGE_HW_ADAPTER_STATUS_RTDMA_RTDMA_READY vxge_mBIT(0) 781 #define VXGE_HW_ADAPTER_STATUS_WRDMA_WRDMA_READY vxge_mBIT(1) 782 #define VXGE_HW_ADAPTER_STATUS_KDFC_KDFC_READY vxge_mBIT(2) 783 #define VXGE_HW_ADAPTER_STATUS_TPA_TMAC_BUF_EMPTY vxge_mBIT(3) 784 #define VXGE_HW_ADAPTER_STATUS_RDCTL_PIC_QUIESCENT vxge_mBIT(4) 785 #define VXGE_HW_ADAPTER_STATUS_XGMAC_NETWORK_FAULT vxge_mBIT(5) 786 #define VXGE_HW_ADAPTER_STATUS_ROCRC_OFFLOAD_QUIESCENT vxge_mBIT(6) 787 #define VXGE_HW_ADAPTER_STATUS_G3IF_FB_G3IF_FB_GDDR3_READY vxge_mBIT(7) 788 #define VXGE_HW_ADAPTER_STATUS_G3IF_CM_G3IF_CM_GDDR3_READY vxge_mBIT(8) 789 #define VXGE_HW_ADAPTER_STATUS_RIC_RIC_RUNNING vxge_mBIT(9) 790 #define VXGE_HW_ADAPTER_STATUS_CMG_C_PLL_IN_LOCK vxge_mBIT(10) 791 #define VXGE_HW_ADAPTER_STATUS_XGMAC_X_PLL_IN_LOCK vxge_mBIT(11) 792 #define VXGE_HW_ADAPTER_STATUS_FBIF_M_PLL_IN_LOCK vxge_mBIT(12) 793 #define VXGE_HW_ADAPTER_STATUS_PCC_PCC_IDLE(val) vxge_vBIT(val, 24, 8) 794 #define VXGE_HW_ADAPTER_STATUS_ROCRC_RC_PRC_QUIESCENT(val) vxge_vBIT(val, 44, 8) 795 /*0x00eb8*/ u64 gen_ctrl; 796 #define VXGE_HW_GEN_CTRL_SPI_MRPCIM_WR_DIS vxge_mBIT(0) 797 #define VXGE_HW_GEN_CTRL_SPI_MRPCIM_RD_DIS vxge_mBIT(1) 798 #define VXGE_HW_GEN_CTRL_SPI_SRPCIM_WR_DIS vxge_mBIT(2) 799 #define VXGE_HW_GEN_CTRL_SPI_SRPCIM_RD_DIS vxge_mBIT(3) 800 #define VXGE_HW_GEN_CTRL_SPI_DEBUG_DIS vxge_mBIT(4) 801 #define VXGE_HW_GEN_CTRL_SPI_APP_LTSSM_TIMER_DIS vxge_mBIT(5) 802 #define VXGE_HW_GEN_CTRL_SPI_NOT_USED(val) vxge_vBIT(val, 6, 4) 803 u8 unused00ed0[0x00ed0-0x00ec0]; 804 805 /*0x00ed0*/ u64 adapter_ready; 806 #define VXGE_HW_ADAPTER_READY_ADAPTER_READY vxge_mBIT(63) 807 /*0x00ed8*/ u64 outstanding_read; 808 #define VXGE_HW_OUTSTANDING_READ_OUTSTANDING_READ(val) vxge_vBIT(val, 0, 17) 809 /*0x00ee0*/ u64 vpath_rst_in_prog; 810 #define VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(val) vxge_vBIT(val, 0, 17) 811 /*0x00ee8*/ u64 vpath_reg_modified; 812 #define VXGE_HW_VPATH_REG_MODIFIED_VPATH_REG_MODIFIED(val) vxge_vBIT(val, 0, 17) 813 u8 unused00fc0[0x00fc0-0x00ef0]; 814 815 /*0x00fc0*/ u64 cp_reset_in_progress; 816 #define VXGE_HW_CP_RESET_IN_PROGRESS_CP_VPATH(n) vxge_mBIT(n) 817 u8 unused01080[0x01080-0x00fc8]; 818 819 /*0x01080*/ u64 xgmac_ready; 820 #define VXGE_HW_XGMAC_READY_XMACJ_READY(val) vxge_vBIT(val, 0, 17) 821 u8 unused010c0[0x010c0-0x01088]; 822 823 /*0x010c0*/ u64 fbif_ready; 824 #define VXGE_HW_FBIF_READY_FAU_READY(val) vxge_vBIT(val, 0, 17) 825 u8 unused01100[0x01100-0x010c8]; 826 827 /*0x01100*/ u64 vplane_assignments; 828 #define VXGE_HW_VPLANE_ASSIGNMENTS_VPLANE_ASSIGNMENTS(val) vxge_vBIT(val, 3, 5) 829 /*0x01108*/ u64 vpath_assignments; 830 #define VXGE_HW_VPATH_ASSIGNMENTS_VPATH_ASSIGNMENTS(val) vxge_vBIT(val, 0, 17) 831 /*0x01110*/ u64 resource_assignments; 832 #define VXGE_HW_RESOURCE_ASSIGNMENTS_RESOURCE_ASSIGNMENTS(val) \ 833 vxge_vBIT(val, 0, 17) 834 /*0x01118*/ u64 host_type_assignments; 835 #define VXGE_HW_HOST_TYPE_ASSIGNMENTS_HOST_TYPE_ASSIGNMENTS(val) \ 836 vxge_vBIT(val, 5, 3) 837 u8 unused01128[0x01128-0x01120]; 838 839 /*0x01128*/ u64 max_resource_assignments; 840 #define VXGE_HW_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPLANE(val) \ 841 vxge_vBIT(val, 3, 5) 842 #define VXGE_HW_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPATHS(val) \ 843 vxge_vBIT(val, 11, 5) 844 /*0x01130*/ u64 pf_vpath_assignments; 845 #define VXGE_HW_PF_VPATH_ASSIGNMENTS_PF_VPATH_ASSIGNMENTS(val) \ 846 vxge_vBIT(val, 0, 17) 847 u8 unused01200[0x01200-0x01138]; 848 849 /*0x01200*/ u64 rts_access_icmp; 850 #define VXGE_HW_RTS_ACCESS_ICMP_EN(val) vxge_vBIT(val, 0, 17) 851 /*0x01208*/ u64 rts_access_tcpsyn; 852 #define VXGE_HW_RTS_ACCESS_TCPSYN_EN(val) vxge_vBIT(val, 0, 17) 853 /*0x01210*/ u64 rts_access_zl4pyld; 854 #define VXGE_HW_RTS_ACCESS_ZL4PYLD_EN(val) vxge_vBIT(val, 0, 17) 855 /*0x01218*/ u64 rts_access_l4prtcl_tcp; 856 #define VXGE_HW_RTS_ACCESS_L4PRTCL_TCP_EN(val) vxge_vBIT(val, 0, 17) 857 /*0x01220*/ u64 rts_access_l4prtcl_udp; 858 #define VXGE_HW_RTS_ACCESS_L4PRTCL_UDP_EN(val) vxge_vBIT(val, 0, 17) 859 /*0x01228*/ u64 rts_access_l4prtcl_flex; 860 #define VXGE_HW_RTS_ACCESS_L4PRTCL_FLEX_EN(val) vxge_vBIT(val, 0, 17) 861 /*0x01230*/ u64 rts_access_ipfrag; 862 #define VXGE_HW_RTS_ACCESS_IPFRAG_EN(val) vxge_vBIT(val, 0, 17) 863 864 } __packed; 865 866 struct vxge_hw_memrepair_reg { 867 u64 unused1; 868 u64 unused2; 869 } __packed; 870 871 struct vxge_hw_pcicfgmgmt_reg { 872 873 /*0x00000*/ u64 resource_no; 874 #define VXGE_HW_RESOURCE_NO_PFN_OR_VF BIT(3) 875 /*0x00008*/ u64 bargrp_pf_or_vf_bar0_mask; 876 #define VXGE_HW_BARGRP_PF_OR_VF_BAR0_MASK_BARGRP_PF_OR_VF_BAR0_MASK(val) \ 877 vxge_vBIT(val, 2, 6) 878 /*0x00010*/ u64 bargrp_pf_or_vf_bar1_mask; 879 #define VXGE_HW_BARGRP_PF_OR_VF_BAR1_MASK_BARGRP_PF_OR_VF_BAR1_MASK(val) \ 880 vxge_vBIT(val, 2, 6) 881 /*0x00018*/ u64 bargrp_pf_or_vf_bar2_mask; 882 #define VXGE_HW_BARGRP_PF_OR_VF_BAR2_MASK_BARGRP_PF_OR_VF_BAR2_MASK(val) \ 883 vxge_vBIT(val, 2, 6) 884 /*0x00020*/ u64 msixgrp_no; 885 #define VXGE_HW_MSIXGRP_NO_TABLE_SIZE(val) vxge_vBIT(val, 5, 11) 886 887 } __packed; 888 889 struct vxge_hw_mrpcim_reg { 890 /*0x00000*/ u64 g3fbct_int_status; 891 #define VXGE_HW_G3FBCT_INT_STATUS_ERR_G3IF_INT vxge_mBIT(0) 892 /*0x00008*/ u64 g3fbct_int_mask; 893 /*0x00010*/ u64 g3fbct_err_reg; 894 #define VXGE_HW_G3FBCT_ERR_REG_G3IF_SM_ERR vxge_mBIT(4) 895 #define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_DECC vxge_mBIT(5) 896 #define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_U_DECC vxge_mBIT(6) 897 #define VXGE_HW_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_DECC vxge_mBIT(7) 898 #define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_SECC vxge_mBIT(29) 899 #define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_U_SECC vxge_mBIT(30) 900 #define VXGE_HW_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_SECC vxge_mBIT(31) 901 /*0x00018*/ u64 g3fbct_err_mask; 902 /*0x00020*/ u64 g3fbct_err_alarm; 903 904 u8 unused00a00[0x00a00-0x00028]; 905 906 /*0x00a00*/ u64 wrdma_int_status; 907 #define VXGE_HW_WRDMA_INT_STATUS_RC_ALARM_RC_INT vxge_mBIT(0) 908 #define VXGE_HW_WRDMA_INT_STATUS_RXDRM_SM_ERR_RXDRM_INT vxge_mBIT(1) 909 #define VXGE_HW_WRDMA_INT_STATUS_RXDCM_SM_ERR_RXDCM_SM_INT vxge_mBIT(2) 910 #define VXGE_HW_WRDMA_INT_STATUS_RXDWM_SM_ERR_RXDWM_INT vxge_mBIT(3) 911 #define VXGE_HW_WRDMA_INT_STATUS_RDA_ERR_RDA_INT vxge_mBIT(6) 912 #define VXGE_HW_WRDMA_INT_STATUS_RDA_ECC_DB_RDA_ECC_DB_INT vxge_mBIT(8) 913 #define VXGE_HW_WRDMA_INT_STATUS_RDA_ECC_SG_RDA_ECC_SG_INT vxge_mBIT(9) 914 #define VXGE_HW_WRDMA_INT_STATUS_FRF_ALARM_FRF_INT vxge_mBIT(12) 915 #define VXGE_HW_WRDMA_INT_STATUS_ROCRC_ALARM_ROCRC_INT vxge_mBIT(13) 916 #define VXGE_HW_WRDMA_INT_STATUS_WDE0_ALARM_WDE0_INT vxge_mBIT(14) 917 #define VXGE_HW_WRDMA_INT_STATUS_WDE1_ALARM_WDE1_INT vxge_mBIT(15) 918 #define VXGE_HW_WRDMA_INT_STATUS_WDE2_ALARM_WDE2_INT vxge_mBIT(16) 919 #define VXGE_HW_WRDMA_INT_STATUS_WDE3_ALARM_WDE3_INT vxge_mBIT(17) 920 /*0x00a08*/ u64 wrdma_int_mask; 921 /*0x00a10*/ u64 rc_alarm_reg; 922 #define VXGE_HW_RC_ALARM_REG_FTC_SM_ERR vxge_mBIT(0) 923 #define VXGE_HW_RC_ALARM_REG_FTC_SM_PHASE_ERR vxge_mBIT(1) 924 #define VXGE_HW_RC_ALARM_REG_BTDWM_SM_ERR vxge_mBIT(2) 925 #define VXGE_HW_RC_ALARM_REG_BTC_SM_ERR vxge_mBIT(3) 926 #define VXGE_HW_RC_ALARM_REG_BTDCM_SM_ERR vxge_mBIT(4) 927 #define VXGE_HW_RC_ALARM_REG_BTDRM_SM_ERR vxge_mBIT(5) 928 #define VXGE_HW_RC_ALARM_REG_RMM_RXD_RC_ECC_DB_ERR vxge_mBIT(6) 929 #define VXGE_HW_RC_ALARM_REG_RMM_RXD_RC_ECC_SG_ERR vxge_mBIT(7) 930 #define VXGE_HW_RC_ALARM_REG_RHS_RXD_RHS_ECC_DB_ERR vxge_mBIT(8) 931 #define VXGE_HW_RC_ALARM_REG_RHS_RXD_RHS_ECC_SG_ERR vxge_mBIT(9) 932 #define VXGE_HW_RC_ALARM_REG_RMM_SM_ERR vxge_mBIT(10) 933 #define VXGE_HW_RC_ALARM_REG_BTC_VPATH_MISMATCH_ERR vxge_mBIT(12) 934 /*0x00a18*/ u64 rc_alarm_mask; 935 /*0x00a20*/ u64 rc_alarm_alarm; 936 /*0x00a28*/ u64 rxdrm_sm_err_reg; 937 #define VXGE_HW_RXDRM_SM_ERR_REG_PRC_VP(n) vxge_mBIT(n) 938 /*0x00a30*/ u64 rxdrm_sm_err_mask; 939 /*0x00a38*/ u64 rxdrm_sm_err_alarm; 940 /*0x00a40*/ u64 rxdcm_sm_err_reg; 941 #define VXGE_HW_RXDCM_SM_ERR_REG_PRC_VP(n) vxge_mBIT(n) 942 /*0x00a48*/ u64 rxdcm_sm_err_mask; 943 /*0x00a50*/ u64 rxdcm_sm_err_alarm; 944 /*0x00a58*/ u64 rxdwm_sm_err_reg; 945 #define VXGE_HW_RXDWM_SM_ERR_REG_PRC_VP(n) vxge_mBIT(n) 946 /*0x00a60*/ u64 rxdwm_sm_err_mask; 947 /*0x00a68*/ u64 rxdwm_sm_err_alarm; 948 /*0x00a70*/ u64 rda_err_reg; 949 #define VXGE_HW_RDA_ERR_REG_RDA_SM0_ERR_ALARM vxge_mBIT(0) 950 #define VXGE_HW_RDA_ERR_REG_RDA_MISC_ERR vxge_mBIT(1) 951 #define VXGE_HW_RDA_ERR_REG_RDA_PCIX_ERR vxge_mBIT(2) 952 #define VXGE_HW_RDA_ERR_REG_RDA_RXD_ECC_DB_ERR vxge_mBIT(3) 953 #define VXGE_HW_RDA_ERR_REG_RDA_FRM_ECC_DB_ERR vxge_mBIT(4) 954 #define VXGE_HW_RDA_ERR_REG_RDA_UQM_ECC_DB_ERR vxge_mBIT(5) 955 #define VXGE_HW_RDA_ERR_REG_RDA_IMM_ECC_DB_ERR vxge_mBIT(6) 956 #define VXGE_HW_RDA_ERR_REG_RDA_TIM_ECC_DB_ERR vxge_mBIT(7) 957 /*0x00a78*/ u64 rda_err_mask; 958 /*0x00a80*/ u64 rda_err_alarm; 959 /*0x00a88*/ u64 rda_ecc_db_reg; 960 #define VXGE_HW_RDA_ECC_DB_REG_RDA_RXD_ERR(n) vxge_mBIT(n) 961 /*0x00a90*/ u64 rda_ecc_db_mask; 962 /*0x00a98*/ u64 rda_ecc_db_alarm; 963 /*0x00aa0*/ u64 rda_ecc_sg_reg; 964 #define VXGE_HW_RDA_ECC_SG_REG_RDA_RXD_ERR(n) vxge_mBIT(n) 965 /*0x00aa8*/ u64 rda_ecc_sg_mask; 966 /*0x00ab0*/ u64 rda_ecc_sg_alarm; 967 /*0x00ab8*/ u64 rqa_err_reg; 968 #define VXGE_HW_RQA_ERR_REG_RQA_SM_ERR_ALARM vxge_mBIT(0) 969 /*0x00ac0*/ u64 rqa_err_mask; 970 /*0x00ac8*/ u64 rqa_err_alarm; 971 /*0x00ad0*/ u64 frf_alarm_reg; 972 #define VXGE_HW_FRF_ALARM_REG_PRC_VP_FRF_SM_ERR(n) vxge_mBIT(n) 973 /*0x00ad8*/ u64 frf_alarm_mask; 974 /*0x00ae0*/ u64 frf_alarm_alarm; 975 /*0x00ae8*/ u64 rocrc_alarm_reg; 976 #define VXGE_HW_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_DB vxge_mBIT(0) 977 #define VXGE_HW_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_SG vxge_mBIT(1) 978 #define VXGE_HW_ROCRC_ALARM_REG_NOA_NMA_SM_ERR vxge_mBIT(2) 979 #define VXGE_HW_ROCRC_ALARM_REG_NOA_IMMM_ECC_DB vxge_mBIT(3) 980 #define VXGE_HW_ROCRC_ALARM_REG_NOA_IMMM_ECC_SG vxge_mBIT(4) 981 #define VXGE_HW_ROCRC_ALARM_REG_UDQ_UMQM_ECC_DB vxge_mBIT(5) 982 #define VXGE_HW_ROCRC_ALARM_REG_UDQ_UMQM_ECC_SG vxge_mBIT(6) 983 #define VXGE_HW_ROCRC_ALARM_REG_NOA_RCBM_ECC_DB vxge_mBIT(11) 984 #define VXGE_HW_ROCRC_ALARM_REG_NOA_RCBM_ECC_SG vxge_mBIT(12) 985 #define VXGE_HW_ROCRC_ALARM_REG_QCQ_MULTI_EGB_RSVD_ERR vxge_mBIT(13) 986 #define VXGE_HW_ROCRC_ALARM_REG_QCQ_MULTI_EGB_OWN_ERR vxge_mBIT(14) 987 #define VXGE_HW_ROCRC_ALARM_REG_QCQ_MULTI_BYP_OWN_ERR vxge_mBIT(15) 988 #define VXGE_HW_ROCRC_ALARM_REG_QCQ_OWN_NOT_ASSIGNED_ERR vxge_mBIT(16) 989 #define VXGE_HW_ROCRC_ALARM_REG_QCQ_OWN_RSVD_SYNC_ERR vxge_mBIT(17) 990 #define VXGE_HW_ROCRC_ALARM_REG_QCQ_LOST_EGB_ERR vxge_mBIT(18) 991 #define VXGE_HW_ROCRC_ALARM_REG_RCQ_BYPQ0_OVERFLOW vxge_mBIT(19) 992 #define VXGE_HW_ROCRC_ALARM_REG_RCQ_BYPQ1_OVERFLOW vxge_mBIT(20) 993 #define VXGE_HW_ROCRC_ALARM_REG_RCQ_BYPQ2_OVERFLOW vxge_mBIT(21) 994 #define VXGE_HW_ROCRC_ALARM_REG_NOA_WCT_CMD_FIFO_ERR vxge_mBIT(22) 995 /*0x00af0*/ u64 rocrc_alarm_mask; 996 /*0x00af8*/ u64 rocrc_alarm_alarm; 997 /*0x00b00*/ u64 wde0_alarm_reg; 998 #define VXGE_HW_WDE0_ALARM_REG_WDE0_DCC_SM_ERR vxge_mBIT(0) 999 #define VXGE_HW_WDE0_ALARM_REG_WDE0_PRM_SM_ERR vxge_mBIT(1) 1000 #define VXGE_HW_WDE0_ALARM_REG_WDE0_CP_SM_ERR vxge_mBIT(2) 1001 #define VXGE_HW_WDE0_ALARM_REG_WDE0_CP_CMD_ERR vxge_mBIT(3) 1002 #define VXGE_HW_WDE0_ALARM_REG_WDE0_PCR_SM_ERR vxge_mBIT(4) 1003 /*0x00b08*/ u64 wde0_alarm_mask; 1004 /*0x00b10*/ u64 wde0_alarm_alarm; 1005 /*0x00b18*/ u64 wde1_alarm_reg; 1006 #define VXGE_HW_WDE1_ALARM_REG_WDE1_DCC_SM_ERR vxge_mBIT(0) 1007 #define VXGE_HW_WDE1_ALARM_REG_WDE1_PRM_SM_ERR vxge_mBIT(1) 1008 #define VXGE_HW_WDE1_ALARM_REG_WDE1_CP_SM_ERR vxge_mBIT(2) 1009 #define VXGE_HW_WDE1_ALARM_REG_WDE1_CP_CMD_ERR vxge_mBIT(3) 1010 #define VXGE_HW_WDE1_ALARM_REG_WDE1_PCR_SM_ERR vxge_mBIT(4) 1011 /*0x00b20*/ u64 wde1_alarm_mask; 1012 /*0x00b28*/ u64 wde1_alarm_alarm; 1013 /*0x00b30*/ u64 wde2_alarm_reg; 1014 #define VXGE_HW_WDE2_ALARM_REG_WDE2_DCC_SM_ERR vxge_mBIT(0) 1015 #define VXGE_HW_WDE2_ALARM_REG_WDE2_PRM_SM_ERR vxge_mBIT(1) 1016 #define VXGE_HW_WDE2_ALARM_REG_WDE2_CP_SM_ERR vxge_mBIT(2) 1017 #define VXGE_HW_WDE2_ALARM_REG_WDE2_CP_CMD_ERR vxge_mBIT(3) 1018 #define VXGE_HW_WDE2_ALARM_REG_WDE2_PCR_SM_ERR vxge_mBIT(4) 1019 /*0x00b38*/ u64 wde2_alarm_mask; 1020 /*0x00b40*/ u64 wde2_alarm_alarm; 1021 /*0x00b48*/ u64 wde3_alarm_reg; 1022 #define VXGE_HW_WDE3_ALARM_REG_WDE3_DCC_SM_ERR vxge_mBIT(0) 1023 #define VXGE_HW_WDE3_ALARM_REG_WDE3_PRM_SM_ERR vxge_mBIT(1) 1024 #define VXGE_HW_WDE3_ALARM_REG_WDE3_CP_SM_ERR vxge_mBIT(2) 1025 #define VXGE_HW_WDE3_ALARM_REG_WDE3_CP_CMD_ERR vxge_mBIT(3) 1026 #define VXGE_HW_WDE3_ALARM_REG_WDE3_PCR_SM_ERR vxge_mBIT(4) 1027 /*0x00b50*/ u64 wde3_alarm_mask; 1028 /*0x00b58*/ u64 wde3_alarm_alarm; 1029 1030 u8 unused00be8[0x00be8-0x00b60]; 1031 1032 /*0x00be8*/ u64 rx_w_round_robin_0; 1033 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_0(val) vxge_vBIT(val, 3, 5) 1034 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_1(val) vxge_vBIT(val, 11, 5) 1035 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_2(val) vxge_vBIT(val, 19, 5) 1036 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_3(val) vxge_vBIT(val, 27, 5) 1037 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_4(val) vxge_vBIT(val, 35, 5) 1038 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_5(val) vxge_vBIT(val, 43, 5) 1039 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_6(val) vxge_vBIT(val, 51, 5) 1040 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_7(val) vxge_vBIT(val, 59, 5) 1041 /*0x00bf0*/ u64 rx_w_round_robin_1; 1042 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_8(val) vxge_vBIT(val, 3, 5) 1043 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_9(val) vxge_vBIT(val, 11, 5) 1044 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_10(val) \ 1045 vxge_vBIT(val, 19, 5) 1046 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_11(val) \ 1047 vxge_vBIT(val, 27, 5) 1048 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_12(val) \ 1049 vxge_vBIT(val, 35, 5) 1050 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_13(val) \ 1051 vxge_vBIT(val, 43, 5) 1052 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_14(val) \ 1053 vxge_vBIT(val, 51, 5) 1054 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_15(val) \ 1055 vxge_vBIT(val, 59, 5) 1056 /*0x00bf8*/ u64 rx_w_round_robin_2; 1057 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_16(val) vxge_vBIT(val, 3, 5) 1058 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_17(val) \ 1059 vxge_vBIT(val, 11, 5) 1060 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_18(val) \ 1061 vxge_vBIT(val, 19, 5) 1062 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_19(val) \ 1063 vxge_vBIT(val, 27, 5) 1064 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_20(val) \ 1065 vxge_vBIT(val, 35, 5) 1066 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_21(val) \ 1067 vxge_vBIT(val, 43, 5) 1068 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_22(val) \ 1069 vxge_vBIT(val, 51, 5) 1070 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_23(val) \ 1071 vxge_vBIT(val, 59, 5) 1072 /*0x00c00*/ u64 rx_w_round_robin_3; 1073 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_24(val) vxge_vBIT(val, 3, 5) 1074 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_25(val) \ 1075 vxge_vBIT(val, 11, 5) 1076 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_26(val) \ 1077 vxge_vBIT(val, 19, 5) 1078 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_27(val) \ 1079 vxge_vBIT(val, 27, 5) 1080 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_28(val) \ 1081 vxge_vBIT(val, 35, 5) 1082 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_29(val) \ 1083 vxge_vBIT(val, 43, 5) 1084 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_30(val) \ 1085 vxge_vBIT(val, 51, 5) 1086 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_31(val) \ 1087 vxge_vBIT(val, 59, 5) 1088 /*0x00c08*/ u64 rx_w_round_robin_4; 1089 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_32(val) vxge_vBIT(val, 3, 5) 1090 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_33(val) \ 1091 vxge_vBIT(val, 11, 5) 1092 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_34(val) \ 1093 vxge_vBIT(val, 19, 5) 1094 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_35(val) \ 1095 vxge_vBIT(val, 27, 5) 1096 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_36(val) \ 1097 vxge_vBIT(val, 35, 5) 1098 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_37(val) \ 1099 vxge_vBIT(val, 43, 5) 1100 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_38(val) \ 1101 vxge_vBIT(val, 51, 5) 1102 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_39(val) \ 1103 vxge_vBIT(val, 59, 5) 1104 /*0x00c10*/ u64 rx_w_round_robin_5; 1105 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_40(val) vxge_vBIT(val, 3, 5) 1106 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_41(val) \ 1107 vxge_vBIT(val, 11, 5) 1108 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_42(val) \ 1109 vxge_vBIT(val, 19, 5) 1110 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_43(val) \ 1111 vxge_vBIT(val, 27, 5) 1112 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_44(val) \ 1113 vxge_vBIT(val, 35, 5) 1114 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_45(val) \ 1115 vxge_vBIT(val, 43, 5) 1116 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_46(val) \ 1117 vxge_vBIT(val, 51, 5) 1118 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_47(val) \ 1119 vxge_vBIT(val, 59, 5) 1120 /*0x00c18*/ u64 rx_w_round_robin_6; 1121 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_48(val) vxge_vBIT(val, 3, 5) 1122 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_49(val) \ 1123 vxge_vBIT(val, 11, 5) 1124 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_50(val) \ 1125 vxge_vBIT(val, 19, 5) 1126 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_51(val) \ 1127 vxge_vBIT(val, 27, 5) 1128 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_52(val) \ 1129 vxge_vBIT(val, 35, 5) 1130 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_53(val) \ 1131 vxge_vBIT(val, 43, 5) 1132 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_54(val) \ 1133 vxge_vBIT(val, 51, 5) 1134 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_55(val) \ 1135 vxge_vBIT(val, 59, 5) 1136 /*0x00c20*/ u64 rx_w_round_robin_7; 1137 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_56(val) vxge_vBIT(val, 3, 5) 1138 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_57(val) \ 1139 vxge_vBIT(val, 11, 5) 1140 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_58(val) \ 1141 vxge_vBIT(val, 19, 5) 1142 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_59(val) \ 1143 vxge_vBIT(val, 27, 5) 1144 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_60(val) \ 1145 vxge_vBIT(val, 35, 5) 1146 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_61(val) \ 1147 vxge_vBIT(val, 43, 5) 1148 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_62(val) \ 1149 vxge_vBIT(val, 51, 5) 1150 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_63(val) \ 1151 vxge_vBIT(val, 59, 5) 1152 /*0x00c28*/ u64 rx_w_round_robin_8; 1153 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_64(val) vxge_vBIT(val, 3, 5) 1154 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_65(val) \ 1155 vxge_vBIT(val, 11, 5) 1156 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_66(val) \ 1157 vxge_vBIT(val, 19, 5) 1158 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_67(val) \ 1159 vxge_vBIT(val, 27, 5) 1160 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_68(val) \ 1161 vxge_vBIT(val, 35, 5) 1162 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_69(val) \ 1163 vxge_vBIT(val, 43, 5) 1164 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_70(val) \ 1165 vxge_vBIT(val, 51, 5) 1166 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_71(val) \ 1167 vxge_vBIT(val, 59, 5) 1168 /*0x00c30*/ u64 rx_w_round_robin_9; 1169 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_72(val) vxge_vBIT(val, 3, 5) 1170 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_73(val) \ 1171 vxge_vBIT(val, 11, 5) 1172 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_74(val) \ 1173 vxge_vBIT(val, 19, 5) 1174 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_75(val) \ 1175 vxge_vBIT(val, 27, 5) 1176 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_76(val) \ 1177 vxge_vBIT(val, 35, 5) 1178 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_77(val) \ 1179 vxge_vBIT(val, 43, 5) 1180 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_78(val) \ 1181 vxge_vBIT(val, 51, 5) 1182 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_79(val) \ 1183 vxge_vBIT(val, 59, 5) 1184 /*0x00c38*/ u64 rx_w_round_robin_10; 1185 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_80(val) \ 1186 vxge_vBIT(val, 3, 5) 1187 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_81(val) \ 1188 vxge_vBIT(val, 11, 5) 1189 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_82(val) \ 1190 vxge_vBIT(val, 19, 5) 1191 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_83(val) \ 1192 vxge_vBIT(val, 27, 5) 1193 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_84(val) \ 1194 vxge_vBIT(val, 35, 5) 1195 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_85(val) \ 1196 vxge_vBIT(val, 43, 5) 1197 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_86(val) \ 1198 vxge_vBIT(val, 51, 5) 1199 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_87(val) \ 1200 vxge_vBIT(val, 59, 5) 1201 /*0x00c40*/ u64 rx_w_round_robin_11; 1202 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_88(val) \ 1203 vxge_vBIT(val, 3, 5) 1204 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_89(val) \ 1205 vxge_vBIT(val, 11, 5) 1206 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_90(val) \ 1207 vxge_vBIT(val, 19, 5) 1208 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_91(val) \ 1209 vxge_vBIT(val, 27, 5) 1210 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_92(val) \ 1211 vxge_vBIT(val, 35, 5) 1212 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_93(val) \ 1213 vxge_vBIT(val, 43, 5) 1214 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_94(val) \ 1215 vxge_vBIT(val, 51, 5) 1216 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_95(val) \ 1217 vxge_vBIT(val, 59, 5) 1218 /*0x00c48*/ u64 rx_w_round_robin_12; 1219 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_96(val) \ 1220 vxge_vBIT(val, 3, 5) 1221 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_97(val) \ 1222 vxge_vBIT(val, 11, 5) 1223 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_98(val) \ 1224 vxge_vBIT(val, 19, 5) 1225 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_99(val) \ 1226 vxge_vBIT(val, 27, 5) 1227 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_100(val) \ 1228 vxge_vBIT(val, 35, 5) 1229 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_101(val) \ 1230 vxge_vBIT(val, 43, 5) 1231 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_102(val) \ 1232 vxge_vBIT(val, 51, 5) 1233 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_103(val) \ 1234 vxge_vBIT(val, 59, 5) 1235 /*0x00c50*/ u64 rx_w_round_robin_13; 1236 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_104(val) \ 1237 vxge_vBIT(val, 3, 5) 1238 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_105(val) \ 1239 vxge_vBIT(val, 11, 5) 1240 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_106(val) \ 1241 vxge_vBIT(val, 19, 5) 1242 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_107(val) \ 1243 vxge_vBIT(val, 27, 5) 1244 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_108(val) \ 1245 vxge_vBIT(val, 35, 5) 1246 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_109(val) \ 1247 vxge_vBIT(val, 43, 5) 1248 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_110(val) \ 1249 vxge_vBIT(val, 51, 5) 1250 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_111(val) \ 1251 vxge_vBIT(val, 59, 5) 1252 /*0x00c58*/ u64 rx_w_round_robin_14; 1253 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_112(val) \ 1254 vxge_vBIT(val, 3, 5) 1255 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_113(val) \ 1256 vxge_vBIT(val, 11, 5) 1257 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_114(val) \ 1258 vxge_vBIT(val, 19, 5) 1259 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_115(val) \ 1260 vxge_vBIT(val, 27, 5) 1261 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_116(val) \ 1262 vxge_vBIT(val, 35, 5) 1263 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_117(val) \ 1264 vxge_vBIT(val, 43, 5) 1265 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_118(val) \ 1266 vxge_vBIT(val, 51, 5) 1267 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_119(val) \ 1268 vxge_vBIT(val, 59, 5) 1269 /*0x00c60*/ u64 rx_w_round_robin_15; 1270 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_120(val) \ 1271 vxge_vBIT(val, 3, 5) 1272 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_121(val) \ 1273 vxge_vBIT(val, 11, 5) 1274 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_122(val) \ 1275 vxge_vBIT(val, 19, 5) 1276 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_123(val) \ 1277 vxge_vBIT(val, 27, 5) 1278 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_124(val) \ 1279 vxge_vBIT(val, 35, 5) 1280 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_125(val) \ 1281 vxge_vBIT(val, 43, 5) 1282 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_126(val) \ 1283 vxge_vBIT(val, 51, 5) 1284 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_127(val) \ 1285 vxge_vBIT(val, 59, 5) 1286 /*0x00c68*/ u64 rx_w_round_robin_16; 1287 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_128(val) \ 1288 vxge_vBIT(val, 3, 5) 1289 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_129(val) \ 1290 vxge_vBIT(val, 11, 5) 1291 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_130(val) \ 1292 vxge_vBIT(val, 19, 5) 1293 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_131(val) \ 1294 vxge_vBIT(val, 27, 5) 1295 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_132(val) \ 1296 vxge_vBIT(val, 35, 5) 1297 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_133(val) \ 1298 vxge_vBIT(val, 43, 5) 1299 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_134(val) \ 1300 vxge_vBIT(val, 51, 5) 1301 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_135(val) \ 1302 vxge_vBIT(val, 59, 5) 1303 /*0x00c70*/ u64 rx_w_round_robin_17; 1304 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_136(val) \ 1305 vxge_vBIT(val, 3, 5) 1306 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_137(val) \ 1307 vxge_vBIT(val, 11, 5) 1308 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_138(val) \ 1309 vxge_vBIT(val, 19, 5) 1310 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_139(val) \ 1311 vxge_vBIT(val, 27, 5) 1312 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_140(val) \ 1313 vxge_vBIT(val, 35, 5) 1314 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_141(val) \ 1315 vxge_vBIT(val, 43, 5) 1316 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_142(val) \ 1317 vxge_vBIT(val, 51, 5) 1318 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_143(val) \ 1319 vxge_vBIT(val, 59, 5) 1320 /*0x00c78*/ u64 rx_w_round_robin_18; 1321 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_144(val) \ 1322 vxge_vBIT(val, 3, 5) 1323 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_145(val) \ 1324 vxge_vBIT(val, 11, 5) 1325 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_146(val) \ 1326 vxge_vBIT(val, 19, 5) 1327 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_147(val) \ 1328 vxge_vBIT(val, 27, 5) 1329 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_148(val) \ 1330 vxge_vBIT(val, 35, 5) 1331 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_149(val) \ 1332 vxge_vBIT(val, 43, 5) 1333 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_150(val) \ 1334 vxge_vBIT(val, 51, 5) 1335 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_151(val) \ 1336 vxge_vBIT(val, 59, 5) 1337 /*0x00c80*/ u64 rx_w_round_robin_19; 1338 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_152(val) \ 1339 vxge_vBIT(val, 3, 5) 1340 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_153(val) \ 1341 vxge_vBIT(val, 11, 5) 1342 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_154(val) \ 1343 vxge_vBIT(val, 19, 5) 1344 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_155(val) \ 1345 vxge_vBIT(val, 27, 5) 1346 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_156(val) \ 1347 vxge_vBIT(val, 35, 5) 1348 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_157(val) \ 1349 vxge_vBIT(val, 43, 5) 1350 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_158(val) \ 1351 vxge_vBIT(val, 51, 5) 1352 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_159(val) \ 1353 vxge_vBIT(val, 59, 5) 1354 /*0x00c88*/ u64 rx_w_round_robin_20; 1355 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_160(val) \ 1356 vxge_vBIT(val, 3, 5) 1357 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_161(val) \ 1358 vxge_vBIT(val, 11, 5) 1359 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_162(val) \ 1360 vxge_vBIT(val, 19, 5) 1361 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_163(val) \ 1362 vxge_vBIT(val, 27, 5) 1363 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_164(val) \ 1364 vxge_vBIT(val, 35, 5) 1365 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_165(val) \ 1366 vxge_vBIT(val, 43, 5) 1367 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_166(val) \ 1368 vxge_vBIT(val, 51, 5) 1369 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_167(val) \ 1370 vxge_vBIT(val, 59, 5) 1371 /*0x00c90*/ u64 rx_w_round_robin_21; 1372 #define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_168(val) \ 1373 vxge_vBIT(val, 3, 5) 1374 #define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_169(val) \ 1375 vxge_vBIT(val, 11, 5) 1376 #define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_170(val) \ 1377 vxge_vBIT(val, 19, 5) 1378 1379 #define VXGE_HW_WRR_RING_SERVICE_STATES 171 1380 #define VXGE_HW_WRR_RING_COUNT 22 1381 1382 /*0x00c98*/ u64 rx_queue_priority_0; 1383 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_0(val) vxge_vBIT(val, 3, 5) 1384 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_1(val) vxge_vBIT(val, 11, 5) 1385 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_2(val) vxge_vBIT(val, 19, 5) 1386 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_3(val) vxge_vBIT(val, 27, 5) 1387 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_4(val) vxge_vBIT(val, 35, 5) 1388 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_5(val) vxge_vBIT(val, 43, 5) 1389 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_6(val) vxge_vBIT(val, 51, 5) 1390 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_7(val) vxge_vBIT(val, 59, 5) 1391 /*0x00ca0*/ u64 rx_queue_priority_1; 1392 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_8(val) vxge_vBIT(val, 3, 5) 1393 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_9(val) vxge_vBIT(val, 11, 5) 1394 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_10(val) vxge_vBIT(val, 19, 5) 1395 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_11(val) vxge_vBIT(val, 27, 5) 1396 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_12(val) vxge_vBIT(val, 35, 5) 1397 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_13(val) vxge_vBIT(val, 43, 5) 1398 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_14(val) vxge_vBIT(val, 51, 5) 1399 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_15(val) vxge_vBIT(val, 59, 5) 1400 /*0x00ca8*/ u64 rx_queue_priority_2; 1401 #define VXGE_HW_RX_QUEUE_PRIORITY_2_RX_Q_NUMBER_16(val) vxge_vBIT(val, 3, 5) 1402 u8 unused00cc8[0x00cc8-0x00cb0]; 1403 1404 /*0x00cc8*/ u64 replication_queue_priority; 1405 #define VXGE_HW_REPLICATION_QUEUE_PRIORITY_REPLICATION_QUEUE_PRIORITY(val) \ 1406 vxge_vBIT(val, 59, 5) 1407 /*0x00cd0*/ u64 rx_queue_select; 1408 #define VXGE_HW_RX_QUEUE_SELECT_NUMBER(n) vxge_mBIT(n) 1409 #define VXGE_HW_RX_QUEUE_SELECT_ENABLE_CODE vxge_mBIT(15) 1410 #define VXGE_HW_RX_QUEUE_SELECT_ENABLE_HIERARCHICAL_PRTY vxge_mBIT(23) 1411 /*0x00cd8*/ u64 rqa_vpbp_ctrl; 1412 #define VXGE_HW_RQA_VPBP_CTRL_WR_XON_DIS vxge_mBIT(15) 1413 #define VXGE_HW_RQA_VPBP_CTRL_ROCRC_DIS vxge_mBIT(23) 1414 #define VXGE_HW_RQA_VPBP_CTRL_TXPE_DIS vxge_mBIT(31) 1415 /*0x00ce0*/ u64 rx_multi_cast_ctrl; 1416 #define VXGE_HW_RX_MULTI_CAST_CTRL_TIME_OUT_DIS vxge_mBIT(0) 1417 #define VXGE_HW_RX_MULTI_CAST_CTRL_FRM_DROP_DIS vxge_mBIT(1) 1418 #define VXGE_HW_RX_MULTI_CAST_CTRL_NO_RXD_TIME_OUT_CNT(val) \ 1419 vxge_vBIT(val, 2, 30) 1420 #define VXGE_HW_RX_MULTI_CAST_CTRL_TIME_OUT_CNT(val) vxge_vBIT(val, 32, 32) 1421 /*0x00ce8*/ u64 wde_prm_ctrl; 1422 #define VXGE_HW_WDE_PRM_CTRL_SPAV_THRESHOLD(val) vxge_vBIT(val, 2, 10) 1423 #define VXGE_HW_WDE_PRM_CTRL_SPLIT_THRESHOLD(val) vxge_vBIT(val, 18, 14) 1424 #define VXGE_HW_WDE_PRM_CTRL_SPLIT_ON_1ST_ROW vxge_mBIT(32) 1425 #define VXGE_HW_WDE_PRM_CTRL_SPLIT_ON_ROW_BNDRY vxge_mBIT(33) 1426 #define VXGE_HW_WDE_PRM_CTRL_FB_ROW_SIZE(val) vxge_vBIT(val, 46, 2) 1427 /*0x00cf0*/ u64 noa_ctrl; 1428 #define VXGE_HW_NOA_CTRL_FRM_PRTY_QUOTA(val) vxge_vBIT(val, 3, 5) 1429 #define VXGE_HW_NOA_CTRL_NON_FRM_PRTY_QUOTA(val) vxge_vBIT(val, 11, 5) 1430 #define VXGE_HW_NOA_CTRL_IGNORE_KDFC_IF_STATUS vxge_mBIT(16) 1431 #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE0(val) vxge_vBIT(val, 37, 4) 1432 #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE1(val) vxge_vBIT(val, 45, 4) 1433 #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE2(val) vxge_vBIT(val, 53, 4) 1434 #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE3(val) vxge_vBIT(val, 60, 4) 1435 /*0x00cf8*/ u64 phase_cfg; 1436 #define VXGE_HW_PHASE_CFG_QCC_WR_PHASE_EN vxge_mBIT(0) 1437 #define VXGE_HW_PHASE_CFG_QCC_RD_PHASE_EN vxge_mBIT(3) 1438 #define VXGE_HW_PHASE_CFG_IMMM_WR_PHASE_EN vxge_mBIT(7) 1439 #define VXGE_HW_PHASE_CFG_IMMM_RD_PHASE_EN vxge_mBIT(11) 1440 #define VXGE_HW_PHASE_CFG_UMQM_WR_PHASE_EN vxge_mBIT(15) 1441 #define VXGE_HW_PHASE_CFG_UMQM_RD_PHASE_EN vxge_mBIT(19) 1442 #define VXGE_HW_PHASE_CFG_RCBM_WR_PHASE_EN vxge_mBIT(23) 1443 #define VXGE_HW_PHASE_CFG_RCBM_RD_PHASE_EN vxge_mBIT(27) 1444 #define VXGE_HW_PHASE_CFG_RXD_RC_WR_PHASE_EN vxge_mBIT(31) 1445 #define VXGE_HW_PHASE_CFG_RXD_RC_RD_PHASE_EN vxge_mBIT(35) 1446 #define VXGE_HW_PHASE_CFG_RXD_RHS_WR_PHASE_EN vxge_mBIT(39) 1447 #define VXGE_HW_PHASE_CFG_RXD_RHS_RD_PHASE_EN vxge_mBIT(43) 1448 /*0x00d00*/ u64 rcq_bypq_cfg; 1449 #define VXGE_HW_RCQ_BYPQ_CFG_OVERFLOW_THRESHOLD(val) vxge_vBIT(val, 10, 22) 1450 #define VXGE_HW_RCQ_BYPQ_CFG_BYP_ON_THRESHOLD(val) vxge_vBIT(val, 39, 9) 1451 #define VXGE_HW_RCQ_BYPQ_CFG_BYP_OFF_THRESHOLD(val) vxge_vBIT(val, 55, 9) 1452 u8 unused00e00[0x00e00-0x00d08]; 1453 1454 /*0x00e00*/ u64 doorbell_int_status; 1455 #define VXGE_HW_DOORBELL_INT_STATUS_KDFC_ERR_REG_TXDMA_KDFC_INT vxge_mBIT(7) 1456 #define VXGE_HW_DOORBELL_INT_STATUS_USDC_ERR_REG_TXDMA_USDC_INT vxge_mBIT(15) 1457 /*0x00e08*/ u64 doorbell_int_mask; 1458 /*0x00e10*/ u64 kdfc_err_reg; 1459 #define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_ECC_SG_ERR vxge_mBIT(7) 1460 #define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_ECC_DB_ERR vxge_mBIT(15) 1461 #define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_SM_ERR_ALARM vxge_mBIT(23) 1462 #define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_MISC_ERR_1 vxge_mBIT(32) 1463 #define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_PCIX_ERR vxge_mBIT(39) 1464 /*0x00e18*/ u64 kdfc_err_mask; 1465 /*0x00e20*/ u64 kdfc_err_reg_alarm; 1466 #define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_ECC_SG_ERR vxge_mBIT(7) 1467 #define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_ECC_DB_ERR vxge_mBIT(15) 1468 #define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_SM_ERR_ALARM vxge_mBIT(23) 1469 #define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_MISC_ERR_1 vxge_mBIT(32) 1470 #define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_PCIX_ERR vxge_mBIT(39) 1471 u8 unused00e40[0x00e40-0x00e28]; 1472 /*0x00e40*/ u64 kdfc_vp_partition_0; 1473 #define VXGE_HW_KDFC_VP_PARTITION_0_ENABLE vxge_mBIT(0) 1474 #define VXGE_HW_KDFC_VP_PARTITION_0_NUMBER_0(val) vxge_vBIT(val, 5, 3) 1475 #define VXGE_HW_KDFC_VP_PARTITION_0_LENGTH_0(val) vxge_vBIT(val, 17, 15) 1476 #define VXGE_HW_KDFC_VP_PARTITION_0_NUMBER_1(val) vxge_vBIT(val, 37, 3) 1477 #define VXGE_HW_KDFC_VP_PARTITION_0_LENGTH_1(val) vxge_vBIT(val, 49, 15) 1478 /*0x00e48*/ u64 kdfc_vp_partition_1; 1479 #define VXGE_HW_KDFC_VP_PARTITION_1_NUMBER_2(val) vxge_vBIT(val, 5, 3) 1480 #define VXGE_HW_KDFC_VP_PARTITION_1_LENGTH_2(val) vxge_vBIT(val, 17, 15) 1481 #define VXGE_HW_KDFC_VP_PARTITION_1_NUMBER_3(val) vxge_vBIT(val, 37, 3) 1482 #define VXGE_HW_KDFC_VP_PARTITION_1_LENGTH_3(val) vxge_vBIT(val, 49, 15) 1483 /*0x00e50*/ u64 kdfc_vp_partition_2; 1484 #define VXGE_HW_KDFC_VP_PARTITION_2_NUMBER_4(val) vxge_vBIT(val, 5, 3) 1485 #define VXGE_HW_KDFC_VP_PARTITION_2_LENGTH_4(val) vxge_vBIT(val, 17, 15) 1486 #define VXGE_HW_KDFC_VP_PARTITION_2_NUMBER_5(val) vxge_vBIT(val, 37, 3) 1487 #define VXGE_HW_KDFC_VP_PARTITION_2_LENGTH_5(val) vxge_vBIT(val, 49, 15) 1488 /*0x00e58*/ u64 kdfc_vp_partition_3; 1489 #define VXGE_HW_KDFC_VP_PARTITION_3_NUMBER_6(val) vxge_vBIT(val, 5, 3) 1490 #define VXGE_HW_KDFC_VP_PARTITION_3_LENGTH_6(val) vxge_vBIT(val, 17, 15) 1491 #define VXGE_HW_KDFC_VP_PARTITION_3_NUMBER_7(val) vxge_vBIT(val, 37, 3) 1492 #define VXGE_HW_KDFC_VP_PARTITION_3_LENGTH_7(val) vxge_vBIT(val, 49, 15) 1493 /*0x00e60*/ u64 kdfc_vp_partition_4; 1494 #define VXGE_HW_KDFC_VP_PARTITION_4_LENGTH_8(val) vxge_vBIT(val, 17, 15) 1495 #define VXGE_HW_KDFC_VP_PARTITION_4_LENGTH_9(val) vxge_vBIT(val, 49, 15) 1496 /*0x00e68*/ u64 kdfc_vp_partition_5; 1497 #define VXGE_HW_KDFC_VP_PARTITION_5_LENGTH_10(val) vxge_vBIT(val, 17, 15) 1498 #define VXGE_HW_KDFC_VP_PARTITION_5_LENGTH_11(val) vxge_vBIT(val, 49, 15) 1499 /*0x00e70*/ u64 kdfc_vp_partition_6; 1500 #define VXGE_HW_KDFC_VP_PARTITION_6_LENGTH_12(val) vxge_vBIT(val, 17, 15) 1501 #define VXGE_HW_KDFC_VP_PARTITION_6_LENGTH_13(val) vxge_vBIT(val, 49, 15) 1502 /*0x00e78*/ u64 kdfc_vp_partition_7; 1503 #define VXGE_HW_KDFC_VP_PARTITION_7_LENGTH_14(val) vxge_vBIT(val, 17, 15) 1504 #define VXGE_HW_KDFC_VP_PARTITION_7_LENGTH_15(val) vxge_vBIT(val, 49, 15) 1505 /*0x00e80*/ u64 kdfc_vp_partition_8; 1506 #define VXGE_HW_KDFC_VP_PARTITION_8_LENGTH_16(val) vxge_vBIT(val, 17, 15) 1507 /*0x00e88*/ u64 kdfc_w_round_robin_0; 1508 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_0(val) vxge_vBIT(val, 3, 5) 1509 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_1(val) vxge_vBIT(val, 11, 5) 1510 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_2(val) vxge_vBIT(val, 19, 5) 1511 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_3(val) vxge_vBIT(val, 27, 5) 1512 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_4(val) vxge_vBIT(val, 35, 5) 1513 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_5(val) vxge_vBIT(val, 43, 5) 1514 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_6(val) vxge_vBIT(val, 51, 5) 1515 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_7(val) vxge_vBIT(val, 59, 5) 1516 1517 u8 unused0f28[0x0f28-0x0e90]; 1518 1519 /*0x00f28*/ u64 kdfc_w_round_robin_20; 1520 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_0(val) vxge_vBIT(val, 3, 5) 1521 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_1(val) vxge_vBIT(val, 11, 5) 1522 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_2(val) vxge_vBIT(val, 19, 5) 1523 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_3(val) vxge_vBIT(val, 27, 5) 1524 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_4(val) vxge_vBIT(val, 35, 5) 1525 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_5(val) vxge_vBIT(val, 43, 5) 1526 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_6(val) vxge_vBIT(val, 51, 5) 1527 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_7(val) vxge_vBIT(val, 59, 5) 1528 1529 #define VXGE_HW_WRR_FIFO_COUNT 20 1530 1531 u8 unused0fc8[0x0fc8-0x0f30]; 1532 1533 /*0x00fc8*/ u64 kdfc_w_round_robin_40; 1534 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_0(val) vxge_vBIT(val, 3, 5) 1535 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_1(val) vxge_vBIT(val, 11, 5) 1536 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_2(val) vxge_vBIT(val, 19, 5) 1537 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_3(val) vxge_vBIT(val, 27, 5) 1538 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_4(val) vxge_vBIT(val, 35, 5) 1539 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_5(val) vxge_vBIT(val, 43, 5) 1540 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_6(val) vxge_vBIT(val, 51, 5) 1541 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_7(val) vxge_vBIT(val, 59, 5) 1542 1543 u8 unused1068[0x01068-0x0fd0]; 1544 1545 /*0x01068*/ u64 kdfc_entry_type_sel_0; 1546 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_0(val) vxge_vBIT(val, 6, 2) 1547 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_1(val) vxge_vBIT(val, 14, 2) 1548 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_2(val) vxge_vBIT(val, 22, 2) 1549 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_3(val) vxge_vBIT(val, 30, 2) 1550 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_4(val) vxge_vBIT(val, 38, 2) 1551 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_5(val) vxge_vBIT(val, 46, 2) 1552 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_6(val) vxge_vBIT(val, 54, 2) 1553 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_7(val) vxge_vBIT(val, 62, 2) 1554 /*0x01070*/ u64 kdfc_entry_type_sel_1; 1555 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_1_NUMBER_8(val) vxge_vBIT(val, 6, 2) 1556 /*0x01078*/ u64 kdfc_fifo_0_ctrl; 1557 #define VXGE_HW_KDFC_FIFO_0_CTRL_WRR_NUMBER(val) vxge_vBIT(val, 3, 5) 1558 #define VXGE_HW_WEIGHTED_RR_SERVICE_STATES 176 1559 #define VXGE_HW_WRR_FIFO_SERVICE_STATES 153 1560 1561 u8 unused1100[0x01100-0x1080]; 1562 1563 /*0x01100*/ u64 kdfc_fifo_17_ctrl; 1564 #define VXGE_HW_KDFC_FIFO_17_CTRL_WRR_NUMBER(val) vxge_vBIT(val, 3, 5) 1565 1566 u8 unused1600[0x01600-0x1108]; 1567 1568 /*0x01600*/ u64 rxmac_int_status; 1569 #define VXGE_HW_RXMAC_INT_STATUS_RXMAC_GEN_ERR_RXMAC_GEN_INT vxge_mBIT(3) 1570 #define VXGE_HW_RXMAC_INT_STATUS_RXMAC_ECC_ERR_RXMAC_ECC_INT vxge_mBIT(7) 1571 #define VXGE_HW_RXMAC_INT_STATUS_RXMAC_VARIOUS_ERR_RXMAC_VARIOUS_INT \ 1572 vxge_mBIT(11) 1573 /*0x01608*/ u64 rxmac_int_mask; 1574 u8 unused01618[0x01618-0x01610]; 1575 1576 /*0x01618*/ u64 rxmac_gen_err_reg; 1577 /*0x01620*/ u64 rxmac_gen_err_mask; 1578 /*0x01628*/ u64 rxmac_gen_err_alarm; 1579 /*0x01630*/ u64 rxmac_ecc_err_reg; 1580 #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_SG_ERR(val) \ 1581 vxge_vBIT(val, 0, 4) 1582 #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_DB_ERR(val) \ 1583 vxge_vBIT(val, 4, 4) 1584 #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_SG_ERR(val) \ 1585 vxge_vBIT(val, 8, 4) 1586 #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_DB_ERR(val) \ 1587 vxge_vBIT(val, 12, 4) 1588 #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_SG_ERR(val) \ 1589 vxge_vBIT(val, 16, 4) 1590 #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_DB_ERR(val) \ 1591 vxge_vBIT(val, 20, 4) 1592 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_SG_ERR(val) \ 1593 vxge_vBIT(val, 24, 2) 1594 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_DB_ERR(val) \ 1595 vxge_vBIT(val, 26, 2) 1596 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_SG_ERR(val) \ 1597 vxge_vBIT(val, 28, 2) 1598 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_DB_ERR(val) \ 1599 vxge_vBIT(val, 30, 2) 1600 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_SG_ERR vxge_mBIT(32) 1601 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_DB_ERR vxge_mBIT(33) 1602 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_SG_ERR vxge_mBIT(34) 1603 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_DB_ERR vxge_mBIT(35) 1604 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_SG_ERR vxge_mBIT(36) 1605 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_DB_ERR vxge_mBIT(37) 1606 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_SG_ERR vxge_mBIT(38) 1607 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_DB_ERR vxge_mBIT(39) 1608 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_SG_ERR(val) \ 1609 vxge_vBIT(val, 40, 7) 1610 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_DB_ERR(val) \ 1611 vxge_vBIT(val, 47, 7) 1612 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_SG_ERR(val) \ 1613 vxge_vBIT(val, 54, 3) 1614 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_DB_ERR(val) \ 1615 vxge_vBIT(val, 57, 3) 1616 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_SG_ERR \ 1617 vxge_mBIT(60) 1618 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_DB_ERR \ 1619 vxge_mBIT(61) 1620 /*0x01638*/ u64 rxmac_ecc_err_mask; 1621 /*0x01640*/ u64 rxmac_ecc_err_alarm; 1622 /*0x01648*/ u64 rxmac_various_err_reg; 1623 #define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT0_FSM_ERR vxge_mBIT(0) 1624 #define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT1_FSM_ERR vxge_mBIT(1) 1625 #define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT2_FSM_ERR vxge_mBIT(2) 1626 #define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMACJ_RMACJ_FSM_ERR vxge_mBIT(3) 1627 /*0x01650*/ u64 rxmac_various_err_mask; 1628 /*0x01658*/ u64 rxmac_various_err_alarm; 1629 /*0x01660*/ u64 rxmac_gen_cfg; 1630 #define VXGE_HW_RXMAC_GEN_CFG_SCALE_RMAC_UTIL vxge_mBIT(11) 1631 /*0x01668*/ u64 rxmac_authorize_all_addr; 1632 #define VXGE_HW_RXMAC_AUTHORIZE_ALL_ADDR_VP(n) vxge_mBIT(n) 1633 /*0x01670*/ u64 rxmac_authorize_all_vid; 1634 #define VXGE_HW_RXMAC_AUTHORIZE_ALL_VID_VP(n) vxge_mBIT(n) 1635 u8 unused016c0[0x016c0-0x01678]; 1636 1637 /*0x016c0*/ u64 rxmac_red_rate_repl_queue; 1638 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR0(val) vxge_vBIT(val, 0, 4) 1639 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR1(val) vxge_vBIT(val, 4, 4) 1640 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR2(val) vxge_vBIT(val, 8, 4) 1641 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR3(val) vxge_vBIT(val, 12, 4) 1642 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR0(val) vxge_vBIT(val, 16, 4) 1643 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR1(val) vxge_vBIT(val, 20, 4) 1644 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR2(val) vxge_vBIT(val, 24, 4) 1645 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR3(val) vxge_vBIT(val, 28, 4) 1646 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_TRICKLE_EN vxge_mBIT(35) 1647 u8 unused016e0[0x016e0-0x016c8]; 1648 1649 /*0x016e0*/ u64 rxmac_cfg0_port[3]; 1650 #define VXGE_HW_RXMAC_CFG0_PORT_RMAC_EN vxge_mBIT(3) 1651 #define VXGE_HW_RXMAC_CFG0_PORT_STRIP_FCS vxge_mBIT(7) 1652 #define VXGE_HW_RXMAC_CFG0_PORT_DISCARD_PFRM vxge_mBIT(11) 1653 #define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_FCS_ERR vxge_mBIT(15) 1654 #define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_LONG_ERR vxge_mBIT(19) 1655 #define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_USIZED_ERR vxge_mBIT(23) 1656 #define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_LEN_MISMATCH vxge_mBIT(27) 1657 #define VXGE_HW_RXMAC_CFG0_PORT_MAX_PYLD_LEN(val) vxge_vBIT(val, 50, 14) 1658 u8 unused01710[0x01710-0x016f8]; 1659 1660 /*0x01710*/ u64 rxmac_cfg2_port[3]; 1661 #define VXGE_HW_RXMAC_CFG2_PORT_PROM_EN vxge_mBIT(3) 1662 /*0x01728*/ u64 rxmac_pause_cfg_port[3]; 1663 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN vxge_mBIT(3) 1664 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN vxge_mBIT(7) 1665 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_ACCEL_SEND(val) vxge_vBIT(val, 9, 3) 1666 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_DUAL_THR vxge_mBIT(15) 1667 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(val) vxge_vBIT(val, 20, 16) 1668 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_IGNORE_PF_FCS_ERR vxge_mBIT(39) 1669 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_IGNORE_PF_LEN_ERR vxge_mBIT(43) 1670 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_LIMITER_EN vxge_mBIT(47) 1671 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(val) vxge_vBIT(val, 48, 8) 1672 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_PERMIT_RATEMGMT_CTRL vxge_mBIT(59) 1673 u8 unused01758[0x01758-0x01740]; 1674 1675 /*0x01758*/ u64 rxmac_red_cfg0_port[3]; 1676 #define VXGE_HW_RXMAC_RED_CFG0_PORT_RED_EN_VP(n) vxge_mBIT(n) 1677 /*0x01770*/ u64 rxmac_red_cfg1_port[3]; 1678 #define VXGE_HW_RXMAC_RED_CFG1_PORT_FINE_EN vxge_mBIT(3) 1679 #define VXGE_HW_RXMAC_RED_CFG1_PORT_RED_EN_REPL_QUEUE vxge_mBIT(11) 1680 /*0x01788*/ u64 rxmac_red_cfg2_port[3]; 1681 #define VXGE_HW_RXMAC_RED_CFG2_PORT_TRICKLE_EN_VP(n) vxge_mBIT(n) 1682 /*0x017a0*/ u64 rxmac_link_util_port[3]; 1683 #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_UTILIZATION(val) \ 1684 vxge_vBIT(val, 1, 7) 1685 #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(val) vxge_vBIT(val, 8, 4) 1686 #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_FRAC_UTIL(val) \ 1687 vxge_vBIT(val, 12, 4) 1688 #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_PKT_WEIGHT(val) vxge_vBIT(val, 16, 4) 1689 #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_SCALE_FACTOR vxge_mBIT(23) 1690 u8 unused017d0[0x017d0-0x017b8]; 1691 1692 /*0x017d0*/ u64 rxmac_status_port[3]; 1693 #define VXGE_HW_RXMAC_STATUS_PORT_RMAC_RX_FRM_RCVD vxge_mBIT(3) 1694 u8 unused01800[0x01800-0x017e8]; 1695 1696 /*0x01800*/ u64 rxmac_rx_pa_cfg0; 1697 #define VXGE_HW_RXMAC_RX_PA_CFG0_IGNORE_FRAME_ERR vxge_mBIT(3) 1698 #define VXGE_HW_RXMAC_RX_PA_CFG0_SUPPORT_SNAP_AB_N vxge_mBIT(7) 1699 #define VXGE_HW_RXMAC_RX_PA_CFG0_SEARCH_FOR_HAO vxge_mBIT(18) 1700 #define VXGE_HW_RXMAC_RX_PA_CFG0_SUPPORT_MOBILE_IPV6_HDRS vxge_mBIT(19) 1701 #define VXGE_HW_RXMAC_RX_PA_CFG0_IPV6_STOP_SEARCHING vxge_mBIT(23) 1702 #define VXGE_HW_RXMAC_RX_PA_CFG0_NO_PS_IF_UNKNOWN vxge_mBIT(27) 1703 #define VXGE_HW_RXMAC_RX_PA_CFG0_SEARCH_FOR_ETYPE vxge_mBIT(35) 1704 #define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_L3_CSUM_ERR vxge_mBIT(39) 1705 #define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_L3_CSUM_ERR vxge_mBIT(43) 1706 #define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_L4_CSUM_ERR vxge_mBIT(47) 1707 #define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_L4_CSUM_ERR vxge_mBIT(51) 1708 #define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_RPA_ERR vxge_mBIT(55) 1709 #define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_RPA_ERR vxge_mBIT(59) 1710 #define VXGE_HW_RXMAC_RX_PA_CFG0_JUMBO_SNAP_EN vxge_mBIT(63) 1711 /*0x01808*/ u64 rxmac_rx_pa_cfg1; 1712 #define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV4_TCP_INCL_PH vxge_mBIT(3) 1713 #define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV6_TCP_INCL_PH vxge_mBIT(7) 1714 #define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV4_UDP_INCL_PH vxge_mBIT(11) 1715 #define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV6_UDP_INCL_PH vxge_mBIT(15) 1716 #define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_L4_INCL_CF vxge_mBIT(19) 1717 #define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG vxge_mBIT(23) 1718 u8 unused01828[0x01828-0x01810]; 1719 1720 /*0x01828*/ u64 rts_mgr_cfg0; 1721 #define VXGE_HW_RTS_MGR_CFG0_RTS_DP_SP_PRIORITY vxge_mBIT(3) 1722 #define VXGE_HW_RTS_MGR_CFG0_FLEX_L4PRTCL_VALUE(val) vxge_vBIT(val, 24, 8) 1723 #define VXGE_HW_RTS_MGR_CFG0_ICMP_TRASH vxge_mBIT(35) 1724 #define VXGE_HW_RTS_MGR_CFG0_TCPSYN_TRASH vxge_mBIT(39) 1725 #define VXGE_HW_RTS_MGR_CFG0_ZL4PYLD_TRASH vxge_mBIT(43) 1726 #define VXGE_HW_RTS_MGR_CFG0_L4PRTCL_TCP_TRASH vxge_mBIT(47) 1727 #define VXGE_HW_RTS_MGR_CFG0_L4PRTCL_UDP_TRASH vxge_mBIT(51) 1728 #define VXGE_HW_RTS_MGR_CFG0_L4PRTCL_FLEX_TRASH vxge_mBIT(55) 1729 #define VXGE_HW_RTS_MGR_CFG0_IPFRAG_TRASH vxge_mBIT(59) 1730 /*0x01830*/ u64 rts_mgr_cfg1; 1731 #define VXGE_HW_RTS_MGR_CFG1_DA_ACTIVE_TABLE vxge_mBIT(3) 1732 #define VXGE_HW_RTS_MGR_CFG1_PN_ACTIVE_TABLE vxge_mBIT(7) 1733 /*0x01838*/ u64 rts_mgr_criteria_priority; 1734 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ETYPE(val) vxge_vBIT(val, 5, 3) 1735 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ICMP_TCPSYN(val) vxge_vBIT(val, 9, 3) 1736 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_L4PN(val) vxge_vBIT(val, 13, 3) 1737 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_RANGE_L4PN(val) vxge_vBIT(val, 17, 3) 1738 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_RTH_IT(val) vxge_vBIT(val, 21, 3) 1739 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_DS(val) vxge_vBIT(val, 25, 3) 1740 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_QOS(val) vxge_vBIT(val, 29, 3) 1741 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ZL4PYLD(val) vxge_vBIT(val, 33, 3) 1742 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_L4PRTCL(val) vxge_vBIT(val, 37, 3) 1743 /*0x01840*/ u64 rts_mgr_da_pause_cfg; 1744 #define VXGE_HW_RTS_MGR_DA_PAUSE_CFG_VPATH_VECTOR(val) vxge_vBIT(val, 0, 17) 1745 /*0x01848*/ u64 rts_mgr_da_slow_proto_cfg; 1746 #define VXGE_HW_RTS_MGR_DA_SLOW_PROTO_CFG_VPATH_VECTOR(val) \ 1747 vxge_vBIT(val, 0, 17) 1748 u8 unused01890[0x01890-0x01850]; 1749 /*0x01890*/ u64 rts_mgr_cbasin_cfg; 1750 u8 unused01968[0x01968-0x01898]; 1751 1752 /*0x01968*/ u64 dbg_stat_rx_any_frms; 1753 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT0_RX_ANY_FRMS(val) vxge_vBIT(val, 0, 8) 1754 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT1_RX_ANY_FRMS(val) vxge_vBIT(val, 8, 8) 1755 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT2_RX_ANY_FRMS(val) \ 1756 vxge_vBIT(val, 16, 8) 1757 u8 unused01a00[0x01a00-0x01970]; 1758 1759 /*0x01a00*/ u64 rxmac_red_rate_vp[17]; 1760 #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR0(val) vxge_vBIT(val, 0, 4) 1761 #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR1(val) vxge_vBIT(val, 4, 4) 1762 #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR2(val) vxge_vBIT(val, 8, 4) 1763 #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR3(val) vxge_vBIT(val, 12, 4) 1764 #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR0(val) vxge_vBIT(val, 16, 4) 1765 #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR1(val) vxge_vBIT(val, 20, 4) 1766 #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR2(val) vxge_vBIT(val, 24, 4) 1767 #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR3(val) vxge_vBIT(val, 28, 4) 1768 u8 unused01e00[0x01e00-0x01a88]; 1769 1770 /*0x01e00*/ u64 xgmac_int_status; 1771 #define VXGE_HW_XGMAC_INT_STATUS_XMAC_GEN_ERR_XMAC_GEN_INT vxge_mBIT(3) 1772 #define VXGE_HW_XGMAC_INT_STATUS_XMAC_LINK_ERR_PORT0_XMAC_LINK_INT_PORT0 \ 1773 vxge_mBIT(7) 1774 #define VXGE_HW_XGMAC_INT_STATUS_XMAC_LINK_ERR_PORT1_XMAC_LINK_INT_PORT1 \ 1775 vxge_mBIT(11) 1776 #define VXGE_HW_XGMAC_INT_STATUS_XGXS_GEN_ERR_XGXS_GEN_INT vxge_mBIT(15) 1777 #define VXGE_HW_XGMAC_INT_STATUS_ASIC_NTWK_ERR_ASIC_NTWK_INT vxge_mBIT(19) 1778 #define VXGE_HW_XGMAC_INT_STATUS_ASIC_GPIO_ERR_ASIC_GPIO_INT vxge_mBIT(23) 1779 /*0x01e08*/ u64 xgmac_int_mask; 1780 /*0x01e10*/ u64 xmac_gen_err_reg; 1781 #define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_ACTOR_CHURN_DETECTED \ 1782 vxge_mBIT(7) 1783 #define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_PARTNER_CHURN_DETECTED \ 1784 vxge_mBIT(11) 1785 #define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_RECEIVED_LACPDU vxge_mBIT(15) 1786 #define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_ACTOR_CHURN_DETECTED \ 1787 vxge_mBIT(19) 1788 #define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_PARTNER_CHURN_DETECTED \ 1789 vxge_mBIT(23) 1790 #define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_RECEIVED_LACPDU vxge_mBIT(27) 1791 #define VXGE_HW_XMAC_GEN_ERR_REG_XLCM_LAG_FAILOVER_DETECTED vxge_mBIT(31) 1792 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_SG_ERR(val) \ 1793 vxge_vBIT(val, 40, 2) 1794 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_DB_ERR(val) \ 1795 vxge_vBIT(val, 42, 2) 1796 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_SG_ERR(val) \ 1797 vxge_vBIT(val, 44, 2) 1798 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_DB_ERR(val) \ 1799 vxge_vBIT(val, 46, 2) 1800 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_SG_ERR(val) \ 1801 vxge_vBIT(val, 48, 2) 1802 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_DB_ERR(val) \ 1803 vxge_vBIT(val, 50, 2) 1804 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_SG_ERR(val) \ 1805 vxge_vBIT(val, 52, 2) 1806 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_DB_ERR(val) \ 1807 vxge_vBIT(val, 54, 2) 1808 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_SG_ERR(val) \ 1809 vxge_vBIT(val, 56, 2) 1810 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_DB_ERR(val) \ 1811 vxge_vBIT(val, 58, 2) 1812 #define VXGE_HW_XMAC_GEN_ERR_REG_XMACJ_XMAC_FSM_ERR vxge_mBIT(63) 1813 /*0x01e18*/ u64 xmac_gen_err_mask; 1814 /*0x01e20*/ u64 xmac_gen_err_alarm; 1815 /*0x01e28*/ u64 xmac_link_err_port0_reg; 1816 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_DOWN vxge_mBIT(3) 1817 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_UP vxge_mBIT(7) 1818 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_WENT_DOWN vxge_mBIT(11) 1819 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_WENT_UP vxge_mBIT(15) 1820 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_REAFFIRMED_FAULT \ 1821 vxge_mBIT(19) 1822 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_REAFFIRMED_OK vxge_mBIT(23) 1823 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_LINK_DOWN vxge_mBIT(27) 1824 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_LINK_UP vxge_mBIT(31) 1825 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_RATEMGMT_RATE_CHANGE vxge_mBIT(35) 1826 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_RATEMGMT_LASI_INV vxge_mBIT(39) 1827 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMDIO_MDIO_MGR_ACCESS_COMPLETE \ 1828 vxge_mBIT(47) 1829 /*0x01e30*/ u64 xmac_link_err_port0_mask; 1830 /*0x01e38*/ u64 xmac_link_err_port0_alarm; 1831 /*0x01e40*/ u64 xmac_link_err_port1_reg; 1832 /*0x01e48*/ u64 xmac_link_err_port1_mask; 1833 /*0x01e50*/ u64 xmac_link_err_port1_alarm; 1834 /*0x01e58*/ u64 xgxs_gen_err_reg; 1835 #define VXGE_HW_XGXS_GEN_ERR_REG_XGXS_XGXS_FSM_ERR vxge_mBIT(63) 1836 /*0x01e60*/ u64 xgxs_gen_err_mask; 1837 /*0x01e68*/ u64 xgxs_gen_err_alarm; 1838 /*0x01e70*/ u64 asic_ntwk_err_reg; 1839 #define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_DOWN vxge_mBIT(3) 1840 #define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_UP vxge_mBIT(7) 1841 #define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_DOWN vxge_mBIT(11) 1842 #define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_UP vxge_mBIT(15) 1843 #define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT vxge_mBIT(19) 1844 #define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK vxge_mBIT(23) 1845 /*0x01e78*/ u64 asic_ntwk_err_mask; 1846 /*0x01e80*/ u64 asic_ntwk_err_alarm; 1847 /*0x01e88*/ u64 asic_gpio_err_reg; 1848 #define VXGE_HW_ASIC_GPIO_ERR_REG_XMACJ_GPIO_INT(n) vxge_mBIT(n) 1849 /*0x01e90*/ u64 asic_gpio_err_mask; 1850 /*0x01e98*/ u64 asic_gpio_err_alarm; 1851 /*0x01ea0*/ u64 xgmac_gen_status; 1852 #define VXGE_HW_XGMAC_GEN_STATUS_XMACJ_NTWK_OK vxge_mBIT(3) 1853 #define VXGE_HW_XGMAC_GEN_STATUS_XMACJ_NTWK_DATA_RATE vxge_mBIT(11) 1854 /*0x01ea8*/ u64 xgmac_gen_fw_memo_status; 1855 #define VXGE_HW_XGMAC_GEN_FW_MEMO_STATUS_XMACJ_EVENTS_PENDING(val) \ 1856 vxge_vBIT(val, 0, 17) 1857 /*0x01eb0*/ u64 xgmac_gen_fw_memo_mask; 1858 #define VXGE_HW_XGMAC_GEN_FW_MEMO_MASK_MASK(val) vxge_vBIT(val, 0, 64) 1859 /*0x01eb8*/ u64 xgmac_gen_fw_vpath_to_vsport_status; 1860 #define VXGE_HW_XGMAC_GEN_FW_VPATH_TO_VSPORT_STATUS_XMACJ_EVENTS_PENDING(val) \ 1861 vxge_vBIT(val, 0, 17) 1862 /*0x01ec0*/ u64 xgmac_main_cfg_port[2]; 1863 #define VXGE_HW_XGMAC_MAIN_CFG_PORT_PORT_EN vxge_mBIT(3) 1864 u8 unused01f40[0x01f40-0x01ed0]; 1865 1866 /*0x01f40*/ u64 xmac_gen_cfg; 1867 #define VXGE_HW_XMAC_GEN_CFG_RATEMGMT_MAC_RATE_SEL(val) vxge_vBIT(val, 2, 2) 1868 #define VXGE_HW_XMAC_GEN_CFG_TX_HEAD_DROP_WHEN_FAULT vxge_mBIT(7) 1869 #define VXGE_HW_XMAC_GEN_CFG_FAULT_BEHAVIOUR vxge_mBIT(27) 1870 #define VXGE_HW_XMAC_GEN_CFG_PERIOD_NTWK_UP(val) vxge_vBIT(val, 28, 4) 1871 #define VXGE_HW_XMAC_GEN_CFG_PERIOD_NTWK_DOWN(val) vxge_vBIT(val, 32, 4) 1872 /*0x01f48*/ u64 xmac_timestamp; 1873 #define VXGE_HW_XMAC_TIMESTAMP_EN vxge_mBIT(3) 1874 #define VXGE_HW_XMAC_TIMESTAMP_USE_LINK_ID(val) vxge_vBIT(val, 6, 2) 1875 #define VXGE_HW_XMAC_TIMESTAMP_INTERVAL(val) vxge_vBIT(val, 12, 4) 1876 #define VXGE_HW_XMAC_TIMESTAMP_TIMER_RESTART vxge_mBIT(19) 1877 #define VXGE_HW_XMAC_TIMESTAMP_XMACJ_ROLLOVER_CNT(val) vxge_vBIT(val, 32, 16) 1878 /*0x01f50*/ u64 xmac_stats_gen_cfg; 1879 #define VXGE_HW_XMAC_STATS_GEN_CFG_PRTAGGR_CUM_TIMER(val) vxge_vBIT(val, 4, 4) 1880 #define VXGE_HW_XMAC_STATS_GEN_CFG_VPATH_CUM_TIMER(val) vxge_vBIT(val, 8, 4) 1881 #define VXGE_HW_XMAC_STATS_GEN_CFG_VLAN_HANDLING vxge_mBIT(15) 1882 /*0x01f58*/ u64 xmac_stats_sys_cmd; 1883 #define VXGE_HW_XMAC_STATS_SYS_CMD_OP(val) vxge_vBIT(val, 5, 3) 1884 #define VXGE_HW_XMAC_STATS_SYS_CMD_STROBE vxge_mBIT(15) 1885 #define VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(val) vxge_vBIT(val, 27, 5) 1886 #define VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(val) vxge_vBIT(val, 32, 8) 1887 /*0x01f60*/ u64 xmac_stats_sys_data; 1888 #define VXGE_HW_XMAC_STATS_SYS_DATA_XSMGR_DATA(val) vxge_vBIT(val, 0, 64) 1889 u8 unused01f80[0x01f80-0x01f68]; 1890 1891 /*0x01f80*/ u64 asic_ntwk_ctrl; 1892 #define VXGE_HW_ASIC_NTWK_CTRL_REQ_TEST_NTWK vxge_mBIT(3) 1893 #define VXGE_HW_ASIC_NTWK_CTRL_PORT0_REQ_TEST_PORT vxge_mBIT(11) 1894 #define VXGE_HW_ASIC_NTWK_CTRL_PORT1_REQ_TEST_PORT vxge_mBIT(15) 1895 /*0x01f88*/ u64 asic_ntwk_cfg_show_port_info; 1896 #define VXGE_HW_ASIC_NTWK_CFG_SHOW_PORT_INFO_VP(n) vxge_mBIT(n) 1897 /*0x01f90*/ u64 asic_ntwk_cfg_port_num; 1898 #define VXGE_HW_ASIC_NTWK_CFG_PORT_NUM_VP(n) vxge_mBIT(n) 1899 /*0x01f98*/ u64 xmac_cfg_port[3]; 1900 #define VXGE_HW_XMAC_CFG_PORT_XGMII_LOOPBACK vxge_mBIT(3) 1901 #define VXGE_HW_XMAC_CFG_PORT_XGMII_REVERSE_LOOPBACK vxge_mBIT(7) 1902 #define VXGE_HW_XMAC_CFG_PORT_XGMII_TX_BEHAV vxge_mBIT(11) 1903 #define VXGE_HW_XMAC_CFG_PORT_XGMII_RX_BEHAV vxge_mBIT(15) 1904 /*0x01fb0*/ u64 xmac_station_addr_port[2]; 1905 #define VXGE_HW_XMAC_STATION_ADDR_PORT_MAC_ADDR(val) vxge_vBIT(val, 0, 48) 1906 u8 unused02020[0x02020-0x01fc0]; 1907 1908 /*0x02020*/ u64 lag_cfg; 1909 #define VXGE_HW_LAG_CFG_EN vxge_mBIT(3) 1910 #define VXGE_HW_LAG_CFG_MODE(val) vxge_vBIT(val, 6, 2) 1911 #define VXGE_HW_LAG_CFG_TX_DISCARD_BEHAV vxge_mBIT(11) 1912 #define VXGE_HW_LAG_CFG_RX_DISCARD_BEHAV vxge_mBIT(15) 1913 #define VXGE_HW_LAG_CFG_PREF_INDIV_PORT_NUM vxge_mBIT(19) 1914 /*0x02028*/ u64 lag_status; 1915 #define VXGE_HW_LAG_STATUS_XLCM_WAITING_TO_FAILBACK vxge_mBIT(3) 1916 #define VXGE_HW_LAG_STATUS_XLCM_TIMER_VAL_COLD_FAILOVER(val) \ 1917 vxge_vBIT(val, 8, 8) 1918 /*0x02030*/ u64 lag_active_passive_cfg; 1919 #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_HOT_STANDBY vxge_mBIT(3) 1920 #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_LACP_DECIDES vxge_mBIT(7) 1921 #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_PREF_ACTIVE_PORT_NUM vxge_mBIT(11) 1922 #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_AUTO_FAILBACK vxge_mBIT(15) 1923 #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_FAILBACK_EN vxge_mBIT(19) 1924 #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT(val) \ 1925 vxge_vBIT(val, 32, 16) 1926 u8 unused02040[0x02040-0x02038]; 1927 1928 /*0x02040*/ u64 lag_lacp_cfg; 1929 #define VXGE_HW_LAG_LACP_CFG_EN vxge_mBIT(3) 1930 #define VXGE_HW_LAG_LACP_CFG_LACP_BEGIN vxge_mBIT(7) 1931 #define VXGE_HW_LAG_LACP_CFG_DISCARD_LACP vxge_mBIT(11) 1932 #define VXGE_HW_LAG_LACP_CFG_LIBERAL_LEN_CHK vxge_mBIT(15) 1933 /*0x02048*/ u64 lag_timer_cfg_1; 1934 #define VXGE_HW_LAG_TIMER_CFG_1_FAST_PER(val) vxge_vBIT(val, 0, 16) 1935 #define VXGE_HW_LAG_TIMER_CFG_1_SLOW_PER(val) vxge_vBIT(val, 16, 16) 1936 #define VXGE_HW_LAG_TIMER_CFG_1_SHORT_TIMEOUT(val) vxge_vBIT(val, 32, 16) 1937 #define VXGE_HW_LAG_TIMER_CFG_1_LONG_TIMEOUT(val) vxge_vBIT(val, 48, 16) 1938 /*0x02050*/ u64 lag_timer_cfg_2; 1939 #define VXGE_HW_LAG_TIMER_CFG_2_CHURN_DET(val) vxge_vBIT(val, 0, 16) 1940 #define VXGE_HW_LAG_TIMER_CFG_2_AGGR_WAIT(val) vxge_vBIT(val, 16, 16) 1941 #define VXGE_HW_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE(val) vxge_vBIT(val, 32, 16) 1942 #define VXGE_HW_LAG_TIMER_CFG_2_LONG_TIMER_SCALE(val) vxge_vBIT(val, 48, 16) 1943 /*0x02058*/ u64 lag_sys_id; 1944 #define VXGE_HW_LAG_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48) 1945 #define VXGE_HW_LAG_SYS_ID_USE_PORT_ADDR vxge_mBIT(51) 1946 #define VXGE_HW_LAG_SYS_ID_ADDR_SEL vxge_mBIT(55) 1947 /*0x02060*/ u64 lag_sys_cfg; 1948 #define VXGE_HW_LAG_SYS_CFG_SYS_PRI(val) vxge_vBIT(val, 0, 16) 1949 u8 unused02070[0x02070-0x02068]; 1950 1951 /*0x02070*/ u64 lag_aggr_addr_cfg[2]; 1952 #define VXGE_HW_LAG_AGGR_ADDR_CFG_ADDR(val) vxge_vBIT(val, 0, 48) 1953 #define VXGE_HW_LAG_AGGR_ADDR_CFG_USE_PORT_ADDR vxge_mBIT(51) 1954 #define VXGE_HW_LAG_AGGR_ADDR_CFG_ADDR_SEL vxge_mBIT(55) 1955 /*0x02080*/ u64 lag_aggr_id_cfg[2]; 1956 #define VXGE_HW_LAG_AGGR_ID_CFG_ID(val) vxge_vBIT(val, 0, 16) 1957 /*0x02090*/ u64 lag_aggr_admin_key[2]; 1958 #define VXGE_HW_LAG_AGGR_ADMIN_KEY_KEY(val) vxge_vBIT(val, 0, 16) 1959 /*0x020a0*/ u64 lag_aggr_alt_admin_key; 1960 #define VXGE_HW_LAG_AGGR_ALT_ADMIN_KEY_KEY(val) vxge_vBIT(val, 0, 16) 1961 #define VXGE_HW_LAG_AGGR_ALT_ADMIN_KEY_ALT_AGGR vxge_mBIT(19) 1962 /*0x020a8*/ u64 lag_aggr_oper_key[2]; 1963 #define VXGE_HW_LAG_AGGR_OPER_KEY_LAGC_KEY(val) vxge_vBIT(val, 0, 16) 1964 /*0x020b8*/ u64 lag_aggr_partner_sys_id[2]; 1965 #define VXGE_HW_LAG_AGGR_PARTNER_SYS_ID_LAGC_ADDR(val) vxge_vBIT(val, 0, 48) 1966 /*0x020c8*/ u64 lag_aggr_partner_info[2]; 1967 #define VXGE_HW_LAG_AGGR_PARTNER_INFO_LAGC_SYS_PRI(val) vxge_vBIT(val, 0, 16) 1968 #define VXGE_HW_LAG_AGGR_PARTNER_INFO_LAGC_OPER_KEY(val) \ 1969 vxge_vBIT(val, 16, 16) 1970 /*0x020d8*/ u64 lag_aggr_state[2]; 1971 #define VXGE_HW_LAG_AGGR_STATE_LAGC_TX vxge_mBIT(3) 1972 #define VXGE_HW_LAG_AGGR_STATE_LAGC_RX vxge_mBIT(7) 1973 #define VXGE_HW_LAG_AGGR_STATE_LAGC_READY vxge_mBIT(11) 1974 #define VXGE_HW_LAG_AGGR_STATE_LAGC_INDIVIDUAL vxge_mBIT(15) 1975 u8 unused020f0[0x020f0-0x020e8]; 1976 1977 /*0x020f0*/ u64 lag_port_cfg[2]; 1978 #define VXGE_HW_LAG_PORT_CFG_EN vxge_mBIT(3) 1979 #define VXGE_HW_LAG_PORT_CFG_DISCARD_SLOW_PROTO vxge_mBIT(7) 1980 #define VXGE_HW_LAG_PORT_CFG_HOST_CHOSEN_AGGR vxge_mBIT(11) 1981 #define VXGE_HW_LAG_PORT_CFG_DISCARD_UNKNOWN_SLOW_PROTO vxge_mBIT(15) 1982 /*0x02100*/ u64 lag_port_actor_admin_cfg[2]; 1983 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM(val) vxge_vBIT(val, 0, 16) 1984 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI(val) vxge_vBIT(val, 16, 16) 1985 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G(val) vxge_vBIT(val, 32, 16) 1986 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G(val) vxge_vBIT(val, 48, 16) 1987 /*0x02110*/ u64 lag_port_actor_admin_state[2]; 1988 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_LACP_ACTIVITY vxge_mBIT(3) 1989 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_LACP_TIMEOUT vxge_mBIT(7) 1990 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_AGGREGATION vxge_mBIT(11) 1991 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_SYNCHRONIZATION vxge_mBIT(15) 1992 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_COLLECTING vxge_mBIT(19) 1993 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_DISTRIBUTING vxge_mBIT(23) 1994 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_DEFAULTED vxge_mBIT(27) 1995 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_EXPIRED vxge_mBIT(31) 1996 /*0x02120*/ u64 lag_port_partner_admin_sys_id[2]; 1997 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48) 1998 /*0x02130*/ u64 lag_port_partner_admin_cfg[2]; 1999 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI(val) vxge_vBIT(val, 0, 16) 2000 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_KEY(val) vxge_vBIT(val, 16, 16) 2001 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM(val) \ 2002 vxge_vBIT(val, 32, 16) 2003 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI(val) \ 2004 vxge_vBIT(val, 48, 16) 2005 /*0x02140*/ u64 lag_port_partner_admin_state[2]; 2006 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_LACP_ACTIVITY vxge_mBIT(3) 2007 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_LACP_TIMEOUT vxge_mBIT(7) 2008 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_AGGREGATION vxge_mBIT(11) 2009 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_SYNCHRONIZATION vxge_mBIT(15) 2010 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_COLLECTING vxge_mBIT(19) 2011 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_DISTRIBUTING vxge_mBIT(23) 2012 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_DEFAULTED vxge_mBIT(27) 2013 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_EXPIRED vxge_mBIT(31) 2014 /*0x02150*/ u64 lag_port_to_aggr[2]; 2015 #define VXGE_HW_LAG_PORT_TO_AGGR_LAGC_AGGR_ID(val) vxge_vBIT(val, 0, 16) 2016 #define VXGE_HW_LAG_PORT_TO_AGGR_LAGC_AGGR_VLD_ID vxge_mBIT(19) 2017 /*0x02160*/ u64 lag_port_actor_oper_key[2]; 2018 #define VXGE_HW_LAG_PORT_ACTOR_OPER_KEY_LAGC_KEY(val) vxge_vBIT(val, 0, 16) 2019 /*0x02170*/ u64 lag_port_actor_oper_state[2]; 2020 #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_LACP_ACTIVITY vxge_mBIT(3) 2021 #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_LACP_TIMEOUT vxge_mBIT(7) 2022 #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_AGGREGATION vxge_mBIT(11) 2023 #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_SYNCHRONIZATION vxge_mBIT(15) 2024 #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_COLLECTING vxge_mBIT(19) 2025 #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_DISTRIBUTING vxge_mBIT(23) 2026 #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_DEFAULTED vxge_mBIT(27) 2027 #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_EXPIRED vxge_mBIT(31) 2028 /*0x02180*/ u64 lag_port_partner_oper_sys_id[2]; 2029 #define VXGE_HW_LAG_PORT_PARTNER_OPER_SYS_ID_LAGC_ADDR(val) \ 2030 vxge_vBIT(val, 0, 48) 2031 /*0x02190*/ u64 lag_port_partner_oper_info[2]; 2032 #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_SYS_PRI(val) \ 2033 vxge_vBIT(val, 0, 16) 2034 #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_KEY(val) \ 2035 vxge_vBIT(val, 16, 16) 2036 #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_NUM(val) \ 2037 vxge_vBIT(val, 32, 16) 2038 #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_PRI(val) \ 2039 vxge_vBIT(val, 48, 16) 2040 /*0x021a0*/ u64 lag_port_partner_oper_state[2]; 2041 #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_LACP_ACTIVITY vxge_mBIT(3) 2042 #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_LACP_TIMEOUT vxge_mBIT(7) 2043 #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_AGGREGATION vxge_mBIT(11) 2044 #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_SYNCHRONIZATION \ 2045 vxge_mBIT(15) 2046 #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_COLLECTING vxge_mBIT(19) 2047 #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_DISTRIBUTING vxge_mBIT(23) 2048 #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_DEFAULTED vxge_mBIT(27) 2049 #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_EXPIRED vxge_mBIT(31) 2050 /*0x021b0*/ u64 lag_port_state_vars[2]; 2051 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_READY vxge_mBIT(3) 2052 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_SELECTED(val) vxge_vBIT(val, 6, 2) 2053 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_AGGR_NUM vxge_mBIT(11) 2054 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PORT_MOVED vxge_mBIT(15) 2055 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PORT_ENABLED vxge_mBIT(18) 2056 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PORT_DISABLED vxge_mBIT(19) 2057 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_NTT vxge_mBIT(23) 2058 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN vxge_mBIT(27) 2059 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN vxge_mBIT(31) 2060 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_INFO_LEN_MISMATCH \ 2061 vxge_mBIT(32) 2062 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_INFO_LEN_MISMATCH \ 2063 vxge_mBIT(33) 2064 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_COLL_INFO_LEN_MISMATCH vxge_mBIT(34) 2065 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_TERM_INFO_LEN_MISMATCH vxge_mBIT(35) 2066 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_RX_FSM_STATE(val) vxge_vBIT(val, 37, 3) 2067 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_MUX_FSM_STATE(val) \ 2068 vxge_vBIT(val, 41, 3) 2069 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_MUX_REASON(val) vxge_vBIT(val, 44, 4) 2070 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_STATE vxge_mBIT(54) 2071 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_STATE vxge_mBIT(55) 2072 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_COUNT(val) \ 2073 vxge_vBIT(val, 56, 4) 2074 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_COUNT(val) \ 2075 vxge_vBIT(val, 60, 4) 2076 /*0x021c0*/ u64 lag_port_timer_cntr[2]; 2077 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_CURRENT_WHILE(val) vxge_vBIT(val, 0, 8) 2078 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PERIODIC_WHILE(val) \ 2079 vxge_vBIT(val, 8, 8) 2080 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_WAIT_WHILE(val) vxge_vBIT(val, 16, 8) 2081 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_TX_LACP(val) vxge_vBIT(val, 24, 8) 2082 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_SYNC_TRANSITION_COUNT(val) \ 2083 vxge_vBIT(val, 32, 8) 2084 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_SYNC_TRANSITION_COUNT(val) \ 2085 vxge_vBIT(val, 40, 8) 2086 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_CHANGE_COUNT(val) \ 2087 vxge_vBIT(val, 48, 8) 2088 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_CHANGE_COUNT(val) \ 2089 vxge_vBIT(val, 56, 8) 2090 u8 unused02208[0x02700-0x021d0]; 2091 2092 /*0x02700*/ u64 rtdma_int_status; 2093 #define VXGE_HW_RTDMA_INT_STATUS_PDA_ALARM_PDA_INT vxge_mBIT(1) 2094 #define VXGE_HW_RTDMA_INT_STATUS_PCC_ERROR_PCC_INT vxge_mBIT(2) 2095 #define VXGE_HW_RTDMA_INT_STATUS_LSO_ERROR_LSO_INT vxge_mBIT(4) 2096 #define VXGE_HW_RTDMA_INT_STATUS_SM_ERROR_SM_INT vxge_mBIT(5) 2097 /*0x02708*/ u64 rtdma_int_mask; 2098 /*0x02710*/ u64 pda_alarm_reg; 2099 #define VXGE_HW_PDA_ALARM_REG_PDA_HSC_FIFO_ERR vxge_mBIT(0) 2100 #define VXGE_HW_PDA_ALARM_REG_PDA_SM_ERR vxge_mBIT(1) 2101 /*0x02718*/ u64 pda_alarm_mask; 2102 /*0x02720*/ u64 pda_alarm_alarm; 2103 /*0x02728*/ u64 pcc_error_reg; 2104 #define VXGE_HW_PCC_ERROR_REG_PCC_PCC_FRM_BUF_SBE(n) vxge_mBIT(n) 2105 #define VXGE_HW_PCC_ERROR_REG_PCC_PCC_TXDO_SBE(n) vxge_mBIT(n) 2106 #define VXGE_HW_PCC_ERROR_REG_PCC_PCC_FRM_BUF_DBE(n) vxge_mBIT(n) 2107 #define VXGE_HW_PCC_ERROR_REG_PCC_PCC_TXDO_DBE(n) vxge_mBIT(n) 2108 #define VXGE_HW_PCC_ERROR_REG_PCC_PCC_FSM_ERR_ALARM(n) vxge_mBIT(n) 2109 #define VXGE_HW_PCC_ERROR_REG_PCC_PCC_SERR(n) vxge_mBIT(n) 2110 /*0x02730*/ u64 pcc_error_mask; 2111 /*0x02738*/ u64 pcc_error_alarm; 2112 /*0x02740*/ u64 lso_error_reg; 2113 #define VXGE_HW_LSO_ERROR_REG_PCC_LSO_ABORT(n) vxge_mBIT(n) 2114 #define VXGE_HW_LSO_ERROR_REG_PCC_LSO_FSM_ERR_ALARM(n) vxge_mBIT(n) 2115 /*0x02748*/ u64 lso_error_mask; 2116 /*0x02750*/ u64 lso_error_alarm; 2117 /*0x02758*/ u64 sm_error_reg; 2118 #define VXGE_HW_SM_ERROR_REG_SM_FSM_ERR_ALARM vxge_mBIT(15) 2119 /*0x02760*/ u64 sm_error_mask; 2120 /*0x02768*/ u64 sm_error_alarm; 2121 2122 u8 unused027a8[0x027a8-0x02770]; 2123 2124 /*0x027a8*/ u64 txd_ownership_ctrl; 2125 #define VXGE_HW_TXD_OWNERSHIP_CTRL_KEEP_OWNERSHIP vxge_mBIT(7) 2126 /*0x027b0*/ u64 pcc_cfg; 2127 #define VXGE_HW_PCC_CFG_PCC_ENABLE(n) vxge_mBIT(n) 2128 #define VXGE_HW_PCC_CFG_PCC_ECC_ENABLE_N(n) vxge_mBIT(n) 2129 /*0x027b8*/ u64 pcc_control; 2130 #define VXGE_HW_PCC_CONTROL_FE_ENABLE(val) vxge_vBIT(val, 6, 2) 2131 #define VXGE_HW_PCC_CONTROL_EARLY_ASSIGN_EN vxge_mBIT(15) 2132 #define VXGE_HW_PCC_CONTROL_UNBLOCK_DB_ERR vxge_mBIT(31) 2133 /*0x027c0*/ u64 pda_status1; 2134 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_0_CTR(val) vxge_vBIT(val, 4, 4) 2135 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_1_CTR(val) vxge_vBIT(val, 12, 4) 2136 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_2_CTR(val) vxge_vBIT(val, 20, 4) 2137 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_3_CTR(val) vxge_vBIT(val, 28, 4) 2138 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_4_CTR(val) vxge_vBIT(val, 36, 4) 2139 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_5_CTR(val) vxge_vBIT(val, 44, 4) 2140 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_6_CTR(val) vxge_vBIT(val, 52, 4) 2141 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_7_CTR(val) vxge_vBIT(val, 60, 4) 2142 /*0x027c8*/ u64 rtdma_bw_timer; 2143 #define VXGE_HW_RTDMA_BW_TIMER_TIMER_CTRL(val) vxge_vBIT(val, 12, 4) 2144 2145 u8 unused02900[0x02900-0x027d0]; 2146 /*0x02900*/ u64 g3cmct_int_status; 2147 #define VXGE_HW_G3CMCT_INT_STATUS_ERR_G3IF_INT vxge_mBIT(0) 2148 /*0x02908*/ u64 g3cmct_int_mask; 2149 /*0x02910*/ u64 g3cmct_err_reg; 2150 #define VXGE_HW_G3CMCT_ERR_REG_G3IF_SM_ERR vxge_mBIT(4) 2151 #define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_DECC vxge_mBIT(5) 2152 #define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_U_DECC vxge_mBIT(6) 2153 #define VXGE_HW_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_DECC vxge_mBIT(7) 2154 #define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_SECC vxge_mBIT(29) 2155 #define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_U_SECC vxge_mBIT(30) 2156 #define VXGE_HW_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_SECC vxge_mBIT(31) 2157 /*0x02918*/ u64 g3cmct_err_mask; 2158 /*0x02920*/ u64 g3cmct_err_alarm; 2159 u8 unused03000[0x03000-0x02928]; 2160 2161 /*0x03000*/ u64 mc_int_status; 2162 #define VXGE_HW_MC_INT_STATUS_MC_ERR_MC_INT vxge_mBIT(3) 2163 #define VXGE_HW_MC_INT_STATUS_GROCRC_ALARM_ROCRC_INT vxge_mBIT(7) 2164 #define VXGE_HW_MC_INT_STATUS_FAU_GEN_ERR_FAU_GEN_INT vxge_mBIT(11) 2165 #define VXGE_HW_MC_INT_STATUS_FAU_ECC_ERR_FAU_ECC_INT vxge_mBIT(15) 2166 /*0x03008*/ u64 mc_int_mask; 2167 /*0x03010*/ u64 mc_err_reg; 2168 #define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_SG_ERR_A vxge_mBIT(3) 2169 #define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_SG_ERR_B vxge_mBIT(4) 2170 #define VXGE_HW_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_SG_ERR vxge_mBIT(5) 2171 #define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_SG_ERR_0 vxge_mBIT(6) 2172 #define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_SG_ERR_1 vxge_mBIT(7) 2173 #define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_A vxge_mBIT(10) 2174 #define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_B vxge_mBIT(11) 2175 #define VXGE_HW_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_DB_ERR vxge_mBIT(12) 2176 #define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_0 vxge_mBIT(13) 2177 #define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_1 vxge_mBIT(14) 2178 #define VXGE_HW_MC_ERR_REG_MC_SM_ERR vxge_mBIT(15) 2179 /*0x03018*/ u64 mc_err_mask; 2180 /*0x03020*/ u64 mc_err_alarm; 2181 /*0x03028*/ u64 grocrc_alarm_reg; 2182 #define VXGE_HW_GROCRC_ALARM_REG_XFMD_WR_FIFO_ERR vxge_mBIT(3) 2183 #define VXGE_HW_GROCRC_ALARM_REG_WDE2MSR_RD_FIFO_ERR vxge_mBIT(7) 2184 /*0x03030*/ u64 grocrc_alarm_mask; 2185 /*0x03038*/ u64 grocrc_alarm_alarm; 2186 u8 unused03100[0x03100-0x03040]; 2187 2188 /*0x03100*/ u64 rx_thresh_cfg_repl; 2189 #define VXGE_HW_RX_THRESH_CFG_REPL_PAUSE_LOW_THR(val) vxge_vBIT(val, 0, 8) 2190 #define VXGE_HW_RX_THRESH_CFG_REPL_PAUSE_HIGH_THR(val) vxge_vBIT(val, 8, 8) 2191 #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_0(val) vxge_vBIT(val, 16, 8) 2192 #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_1(val) vxge_vBIT(val, 24, 8) 2193 #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_2(val) vxge_vBIT(val, 32, 8) 2194 #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_3(val) vxge_vBIT(val, 40, 8) 2195 #define VXGE_HW_RX_THRESH_CFG_REPL_GLOBAL_WOL_EN vxge_mBIT(62) 2196 #define VXGE_HW_RX_THRESH_CFG_REPL_EXACT_VP_MATCH_REQ vxge_mBIT(63) 2197 u8 unused033b8[0x033b8-0x03108]; 2198 2199 /*0x033b8*/ u64 fbmc_ecc_cfg; 2200 #define VXGE_HW_FBMC_ECC_CFG_ENABLE(val) vxge_vBIT(val, 3, 5) 2201 u8 unused03400[0x03400-0x033c0]; 2202 2203 /*0x03400*/ u64 pcipif_int_status; 2204 #define VXGE_HW_PCIPIF_INT_STATUS_DBECC_ERR_DBECC_ERR_INT vxge_mBIT(3) 2205 #define VXGE_HW_PCIPIF_INT_STATUS_SBECC_ERR_SBECC_ERR_INT vxge_mBIT(7) 2206 #define VXGE_HW_PCIPIF_INT_STATUS_GENERAL_ERR_GENERAL_ERR_INT vxge_mBIT(11) 2207 #define VXGE_HW_PCIPIF_INT_STATUS_SRPCIM_MSG_SRPCIM_MSG_INT vxge_mBIT(15) 2208 #define VXGE_HW_PCIPIF_INT_STATUS_MRPCIM_SPARE_R1_MRPCIM_SPARE_R1_INT \ 2209 vxge_mBIT(19) 2210 /*0x03408*/ u64 pcipif_int_mask; 2211 /*0x03410*/ u64 dbecc_err_reg; 2212 #define VXGE_HW_DBECC_ERR_REG_PCI_RETRY_BUF_DB_ERR vxge_mBIT(3) 2213 #define VXGE_HW_DBECC_ERR_REG_PCI_RETRY_SOT_DB_ERR vxge_mBIT(7) 2214 #define VXGE_HW_DBECC_ERR_REG_PCI_P_HDR_DB_ERR vxge_mBIT(11) 2215 #define VXGE_HW_DBECC_ERR_REG_PCI_P_DATA_DB_ERR vxge_mBIT(15) 2216 #define VXGE_HW_DBECC_ERR_REG_PCI_NP_HDR_DB_ERR vxge_mBIT(19) 2217 #define VXGE_HW_DBECC_ERR_REG_PCI_NP_DATA_DB_ERR vxge_mBIT(23) 2218 /*0x03418*/ u64 dbecc_err_mask; 2219 /*0x03420*/ u64 dbecc_err_alarm; 2220 /*0x03428*/ u64 sbecc_err_reg; 2221 #define VXGE_HW_SBECC_ERR_REG_PCI_RETRY_BUF_SG_ERR vxge_mBIT(3) 2222 #define VXGE_HW_SBECC_ERR_REG_PCI_RETRY_SOT_SG_ERR vxge_mBIT(7) 2223 #define VXGE_HW_SBECC_ERR_REG_PCI_P_HDR_SG_ERR vxge_mBIT(11) 2224 #define VXGE_HW_SBECC_ERR_REG_PCI_P_DATA_SG_ERR vxge_mBIT(15) 2225 #define VXGE_HW_SBECC_ERR_REG_PCI_NP_HDR_SG_ERR vxge_mBIT(19) 2226 #define VXGE_HW_SBECC_ERR_REG_PCI_NP_DATA_SG_ERR vxge_mBIT(23) 2227 /*0x03430*/ u64 sbecc_err_mask; 2228 /*0x03438*/ u64 sbecc_err_alarm; 2229 /*0x03440*/ u64 general_err_reg; 2230 #define VXGE_HW_GENERAL_ERR_REG_PCI_DROPPED_ILLEGAL_CFG vxge_mBIT(3) 2231 #define VXGE_HW_GENERAL_ERR_REG_PCI_ILLEGAL_MEM_MAP_PROG vxge_mBIT(7) 2232 #define VXGE_HW_GENERAL_ERR_REG_PCI_LINK_RST_FSM_ERR vxge_mBIT(11) 2233 #define VXGE_HW_GENERAL_ERR_REG_PCI_RX_ILLEGAL_TLP_VPLANE vxge_mBIT(15) 2234 #define VXGE_HW_GENERAL_ERR_REG_PCI_TRAINING_RESET_DET vxge_mBIT(19) 2235 #define VXGE_HW_GENERAL_ERR_REG_PCI_PCI_LINK_DOWN_DET vxge_mBIT(23) 2236 #define VXGE_HW_GENERAL_ERR_REG_PCI_RESET_ACK_DLLP vxge_mBIT(27) 2237 /*0x03448*/ u64 general_err_mask; 2238 /*0x03450*/ u64 general_err_alarm; 2239 /*0x03458*/ u64 srpcim_msg_reg; 2240 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE0_RMSG_INT \ 2241 vxge_mBIT(0) 2242 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE1_RMSG_INT \ 2243 vxge_mBIT(1) 2244 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE2_RMSG_INT \ 2245 vxge_mBIT(2) 2246 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE3_RMSG_INT \ 2247 vxge_mBIT(3) 2248 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE4_RMSG_INT \ 2249 vxge_mBIT(4) 2250 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE5_RMSG_INT \ 2251 vxge_mBIT(5) 2252 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE6_RMSG_INT \ 2253 vxge_mBIT(6) 2254 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE7_RMSG_INT \ 2255 vxge_mBIT(7) 2256 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE8_RMSG_INT \ 2257 vxge_mBIT(8) 2258 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE9_RMSG_INT \ 2259 vxge_mBIT(9) 2260 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE10_RMSG_INT \ 2261 vxge_mBIT(10) 2262 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE11_RMSG_INT \ 2263 vxge_mBIT(11) 2264 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE12_RMSG_INT \ 2265 vxge_mBIT(12) 2266 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE13_RMSG_INT \ 2267 vxge_mBIT(13) 2268 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE14_RMSG_INT \ 2269 vxge_mBIT(14) 2270 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE15_RMSG_INT \ 2271 vxge_mBIT(15) 2272 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE16_RMSG_INT \ 2273 vxge_mBIT(16) 2274 /*0x03460*/ u64 srpcim_msg_mask; 2275 /*0x03468*/ u64 srpcim_msg_alarm; 2276 u8 unused03600[0x03600-0x03470]; 2277 2278 /*0x03600*/ u64 gcmg1_int_status; 2279 #define VXGE_HW_GCMG1_INT_STATUS_GSSCC_ERR_GSSCC_INT vxge_mBIT(0) 2280 #define VXGE_HW_GCMG1_INT_STATUS_GSSC0_ERR0_GSSC0_0_INT vxge_mBIT(1) 2281 #define VXGE_HW_GCMG1_INT_STATUS_GSSC0_ERR1_GSSC0_1_INT vxge_mBIT(2) 2282 #define VXGE_HW_GCMG1_INT_STATUS_GSSC1_ERR0_GSSC1_0_INT vxge_mBIT(3) 2283 #define VXGE_HW_GCMG1_INT_STATUS_GSSC1_ERR1_GSSC1_1_INT vxge_mBIT(4) 2284 #define VXGE_HW_GCMG1_INT_STATUS_GSSC2_ERR0_GSSC2_0_INT vxge_mBIT(5) 2285 #define VXGE_HW_GCMG1_INT_STATUS_GSSC2_ERR1_GSSC2_1_INT vxge_mBIT(6) 2286 #define VXGE_HW_GCMG1_INT_STATUS_UQM_ERR_UQM_INT vxge_mBIT(7) 2287 #define VXGE_HW_GCMG1_INT_STATUS_GQCC_ERR_GQCC_INT vxge_mBIT(8) 2288 /*0x03608*/ u64 gcmg1_int_mask; 2289 u8 unused03a00[0x03a00-0x03610]; 2290 2291 /*0x03a00*/ u64 pcmg1_int_status; 2292 #define VXGE_HW_PCMG1_INT_STATUS_PSSCC_ERR_PSSCC_INT vxge_mBIT(0) 2293 #define VXGE_HW_PCMG1_INT_STATUS_PQCC_ERR_PQCC_INT vxge_mBIT(1) 2294 #define VXGE_HW_PCMG1_INT_STATUS_PQCC_CQM_ERR_PQCC_CQM_INT vxge_mBIT(2) 2295 #define VXGE_HW_PCMG1_INT_STATUS_PQCC_SQM_ERR_PQCC_SQM_INT vxge_mBIT(3) 2296 /*0x03a08*/ u64 pcmg1_int_mask; 2297 u8 unused04000[0x04000-0x03a10]; 2298 2299 /*0x04000*/ u64 one_int_status; 2300 #define VXGE_HW_ONE_INT_STATUS_RXPE_ERR_RXPE_INT vxge_mBIT(7) 2301 #define VXGE_HW_ONE_INT_STATUS_TXPE_BCC_MEM_SG_ECC_ERR_TXPE_BCC_MEM_SG_ECC_INT \ 2302 vxge_mBIT(13) 2303 #define VXGE_HW_ONE_INT_STATUS_TXPE_BCC_MEM_DB_ECC_ERR_TXPE_BCC_MEM_DB_ECC_INT \ 2304 vxge_mBIT(14) 2305 #define VXGE_HW_ONE_INT_STATUS_TXPE_ERR_TXPE_INT vxge_mBIT(15) 2306 #define VXGE_HW_ONE_INT_STATUS_DLM_ERR_DLM_INT vxge_mBIT(23) 2307 #define VXGE_HW_ONE_INT_STATUS_PE_ERR_PE_INT vxge_mBIT(31) 2308 #define VXGE_HW_ONE_INT_STATUS_RPE_ERR_RPE_INT vxge_mBIT(39) 2309 #define VXGE_HW_ONE_INT_STATUS_RPE_FSM_ERR_RPE_FSM_INT vxge_mBIT(47) 2310 #define VXGE_HW_ONE_INT_STATUS_OES_ERR_OES_INT vxge_mBIT(55) 2311 /*0x04008*/ u64 one_int_mask; 2312 u8 unused04818[0x04818-0x04010]; 2313 2314 /*0x04818*/ u64 noa_wct_ctrl; 2315 #define VXGE_HW_NOA_WCT_CTRL_VP_INT_NUM vxge_mBIT(0) 2316 /*0x04820*/ u64 rc_cfg2; 2317 #define VXGE_HW_RC_CFG2_BUFF1_SIZE(val) vxge_vBIT(val, 0, 16) 2318 #define VXGE_HW_RC_CFG2_BUFF2_SIZE(val) vxge_vBIT(val, 16, 16) 2319 #define VXGE_HW_RC_CFG2_BUFF3_SIZE(val) vxge_vBIT(val, 32, 16) 2320 #define VXGE_HW_RC_CFG2_BUFF4_SIZE(val) vxge_vBIT(val, 48, 16) 2321 /*0x04828*/ u64 rc_cfg3; 2322 #define VXGE_HW_RC_CFG3_BUFF5_SIZE(val) vxge_vBIT(val, 0, 16) 2323 /*0x04830*/ u64 rx_multi_cast_ctrl1; 2324 #define VXGE_HW_RX_MULTI_CAST_CTRL1_ENABLE vxge_mBIT(7) 2325 #define VXGE_HW_RX_MULTI_CAST_CTRL1_DELAY_COUNT(val) vxge_vBIT(val, 11, 5) 2326 /*0x04838*/ u64 rxdm_dbg_rd; 2327 #define VXGE_HW_RXDM_DBG_RD_ADDR(val) vxge_vBIT(val, 0, 12) 2328 #define VXGE_HW_RXDM_DBG_RD_ENABLE vxge_mBIT(31) 2329 /*0x04840*/ u64 rxdm_dbg_rd_data; 2330 #define VXGE_HW_RXDM_DBG_RD_DATA_RMC_RXDM_DBG_RD_DATA(val) vxge_vBIT(val, 0, 64) 2331 /*0x04848*/ u64 rqa_top_prty_for_vh[17]; 2332 #define VXGE_HW_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val) \ 2333 vxge_vBIT(val, 59, 5) 2334 u8 unused04900[0x04900-0x048d0]; 2335 2336 /*0x04900*/ u64 tim_status; 2337 #define VXGE_HW_TIM_STATUS_TIM_RESET_IN_PROGRESS vxge_mBIT(0) 2338 /*0x04908*/ u64 tim_ecc_enable; 2339 #define VXGE_HW_TIM_ECC_ENABLE_VBLS_N vxge_mBIT(7) 2340 #define VXGE_HW_TIM_ECC_ENABLE_BMAP_N vxge_mBIT(15) 2341 #define VXGE_HW_TIM_ECC_ENABLE_BMAP_MSG_N vxge_mBIT(23) 2342 /*0x04910*/ u64 tim_bp_ctrl; 2343 #define VXGE_HW_TIM_BP_CTRL_RD_XON vxge_mBIT(7) 2344 #define VXGE_HW_TIM_BP_CTRL_WR_XON vxge_mBIT(15) 2345 #define VXGE_HW_TIM_BP_CTRL_ROCRC_BYP vxge_mBIT(23) 2346 /*0x04918*/ u64 tim_resource_assignment_vh[17]; 2347 #define VXGE_HW_TIM_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val) vxge_vBIT(val, 0, 32) 2348 /*0x049a0*/ u64 tim_bmap_mapping_vp_err[17]; 2349 #define VXGE_HW_TIM_BMAP_MAPPING_VP_ERR_TIM_DEST_VPATH(val) vxge_vBIT(val, 3, 5) 2350 u8 unused04b00[0x04b00-0x04a28]; 2351 2352 /*0x04b00*/ u64 gcmg2_int_status; 2353 #define VXGE_HW_GCMG2_INT_STATUS_GXTMC_ERR_GXTMC_INT vxge_mBIT(7) 2354 #define VXGE_HW_GCMG2_INT_STATUS_GCP_ERR_GCP_INT vxge_mBIT(15) 2355 #define VXGE_HW_GCMG2_INT_STATUS_CMC_ERR_CMC_INT vxge_mBIT(23) 2356 /*0x04b08*/ u64 gcmg2_int_mask; 2357 /*0x04b10*/ u64 gxtmc_err_reg; 2358 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_MEM_DB_ERR(val) vxge_vBIT(val, 0, 4) 2359 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_MEM_SG_ERR(val) vxge_vBIT(val, 4, 4) 2360 #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMC_RD_DATA_DB_ERR vxge_mBIT(8) 2361 #define VXGE_HW_GXTMC_ERR_REG_XTMC_REQ_FIFO_ERR vxge_mBIT(9) 2362 #define VXGE_HW_GXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR vxge_mBIT(10) 2363 #define VXGE_HW_GXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR vxge_mBIT(11) 2364 #define VXGE_HW_GXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR vxge_mBIT(12) 2365 #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_WRP_FIFO_ERR vxge_mBIT(13) 2366 #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_WRP_ERR vxge_mBIT(14) 2367 #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_RRP_FIFO_ERR vxge_mBIT(15) 2368 #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_RRP_ERR vxge_mBIT(16) 2369 #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_DATA_SM_ERR vxge_mBIT(17) 2370 #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_CMC0_IF_ERR vxge_mBIT(18) 2371 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_ARB_SM_ERR vxge_mBIT(19) 2372 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_CFC_SM_ERR vxge_mBIT(20) 2373 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_OVERFLOW \ 2374 vxge_mBIT(21) 2375 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_UNDERFLOW \ 2376 vxge_mBIT(22) 2377 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_SM_ERR vxge_mBIT(23) 2378 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_OVERFLOW \ 2379 vxge_mBIT(24) 2380 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_UNDERFLOW \ 2381 vxge_mBIT(25) 2382 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_SM_ERR vxge_mBIT(26) 2383 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_SM_ERR vxge_mBIT(27) 2384 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_TAG_ERR vxge_mBIT(28) 2385 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_SM_ERR vxge_mBIT(29) 2386 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_FIFO_ERR vxge_mBIT(30) 2387 #define VXGE_HW_GXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_POP_ERR vxge_mBIT(31) 2388 #define VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_CMI_OP_ERR vxge_mBIT(32) 2389 #define VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFETCH_OP_ERR vxge_mBIT(33) 2390 #define VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFIFO_ERR vxge_mBIT(34) 2391 #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_ARB_SM_ERR vxge_mBIT(35) 2392 /*0x04b18*/ u64 gxtmc_err_mask; 2393 /*0x04b20*/ u64 gxtmc_err_alarm; 2394 /*0x04b28*/ u64 cmc_err_reg; 2395 #define VXGE_HW_CMC_ERR_REG_CMC_CMC_SM_ERR vxge_mBIT(0) 2396 /*0x04b30*/ u64 cmc_err_mask; 2397 /*0x04b38*/ u64 cmc_err_alarm; 2398 /*0x04b40*/ u64 gcp_err_reg; 2399 #define VXGE_HW_GCP_ERR_REG_CP_H2L2CP_FIFO_ERR vxge_mBIT(0) 2400 #define VXGE_HW_GCP_ERR_REG_CP_STC2CP_FIFO_ERR vxge_mBIT(1) 2401 #define VXGE_HW_GCP_ERR_REG_CP_STE2CP_FIFO_ERR vxge_mBIT(2) 2402 #define VXGE_HW_GCP_ERR_REG_CP_TTE2CP_FIFO_ERR vxge_mBIT(3) 2403 /*0x04b48*/ u64 gcp_err_mask; 2404 /*0x04b50*/ u64 gcp_err_alarm; 2405 u8 unused04f00[0x04f00-0x04b58]; 2406 2407 /*0x04f00*/ u64 pcmg2_int_status; 2408 #define VXGE_HW_PCMG2_INT_STATUS_PXTMC_ERR_PXTMC_INT vxge_mBIT(7) 2409 #define VXGE_HW_PCMG2_INT_STATUS_CP_EXC_CP_XT_EXC_INT vxge_mBIT(15) 2410 #define VXGE_HW_PCMG2_INT_STATUS_CP_ERR_CP_ERR_INT vxge_mBIT(23) 2411 /*0x04f08*/ u64 pcmg2_int_mask; 2412 /*0x04f10*/ u64 pxtmc_err_reg; 2413 #define VXGE_HW_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_DB_ERR(val) vxge_vBIT(val, 0, 2) 2414 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_REQ_FIFO_ERR vxge_mBIT(2) 2415 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_PRSP_FIFO_ERR vxge_mBIT(3) 2416 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_WRSP_FIFO_ERR vxge_mBIT(4) 2417 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_REQ_FIFO_ERR vxge_mBIT(5) 2418 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_PRSP_FIFO_ERR vxge_mBIT(6) 2419 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_WRSP_FIFO_ERR vxge_mBIT(7) 2420 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_REQ_FIFO_ERR vxge_mBIT(8) 2421 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_PRSP_FIFO_ERR vxge_mBIT(9) 2422 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_WRSP_FIFO_ERR vxge_mBIT(10) 2423 #define VXGE_HW_PXTMC_ERR_REG_XTMC_REQ_FIFO_ERR vxge_mBIT(11) 2424 #define VXGE_HW_PXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR vxge_mBIT(12) 2425 #define VXGE_HW_PXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR vxge_mBIT(13) 2426 #define VXGE_HW_PXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR vxge_mBIT(14) 2427 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_REQ_SHADOW_ERR vxge_mBIT(15) 2428 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_RSP_SHADOW_ERR vxge_mBIT(16) 2429 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_REQ_SHADOW_ERR vxge_mBIT(17) 2430 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_RSP_SHADOW_ERR vxge_mBIT(18) 2431 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_REQ_SHADOW_ERR vxge_mBIT(19) 2432 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_RSP_SHADOW_ERR vxge_mBIT(20) 2433 #define VXGE_HW_PXTMC_ERR_REG_XTMC_XIL_SHADOW_ERR vxge_mBIT(21) 2434 #define VXGE_HW_PXTMC_ERR_REG_XTMC_ARB_SHADOW_ERR vxge_mBIT(22) 2435 #define VXGE_HW_PXTMC_ERR_REG_XTMC_RAM_SHADOW_ERR vxge_mBIT(23) 2436 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CMW_SHADOW_ERR vxge_mBIT(24) 2437 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CMR_SHADOW_ERR vxge_mBIT(25) 2438 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_REQ_FSM_ERR vxge_mBIT(26) 2439 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_RSP_FSM_ERR vxge_mBIT(27) 2440 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_REQ_FSM_ERR vxge_mBIT(28) 2441 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_RSP_FSM_ERR vxge_mBIT(29) 2442 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_REQ_FSM_ERR vxge_mBIT(30) 2443 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_RSP_FSM_ERR vxge_mBIT(31) 2444 #define VXGE_HW_PXTMC_ERR_REG_XTMC_XIL_FSM_ERR vxge_mBIT(32) 2445 #define VXGE_HW_PXTMC_ERR_REG_XTMC_ARB_FSM_ERR vxge_mBIT(33) 2446 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CMW_FSM_ERR vxge_mBIT(34) 2447 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CMR_FSM_ERR vxge_mBIT(35) 2448 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_ERR vxge_mBIT(36) 2449 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_ERR vxge_mBIT(37) 2450 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_ERR vxge_mBIT(38) 2451 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_ERR vxge_mBIT(39) 2452 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_ERR vxge_mBIT(40) 2453 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_ERR vxge_mBIT(41) 2454 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_ERR vxge_mBIT(42) 2455 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_ERR vxge_mBIT(43) 2456 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_ERR vxge_mBIT(44) 2457 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_INFO_ERR vxge_mBIT(45) 2458 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_INFO_ERR vxge_mBIT(46) 2459 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_INFO_ERR vxge_mBIT(47) 2460 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_INFO_ERR vxge_mBIT(48) 2461 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_INFO_ERR vxge_mBIT(49) 2462 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_INFO_ERR vxge_mBIT(50) 2463 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_INFO_ERR vxge_mBIT(51) 2464 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_INFO_ERR vxge_mBIT(52) 2465 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_INFO_ERR vxge_mBIT(53) 2466 #define VXGE_HW_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_SG_ERR(val) vxge_vBIT(val, 54, 2) 2467 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CP2BDT_DFIFO_PUSH_ERR vxge_mBIT(56) 2468 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_PUSH_ERR vxge_mBIT(57) 2469 /*0x04f18*/ u64 pxtmc_err_mask; 2470 /*0x04f20*/ u64 pxtmc_err_alarm; 2471 /*0x04f28*/ u64 cp_err_reg; 2472 #define VXGE_HW_CP_ERR_REG_CP_CP_DCACHE_SG_ERR(val) vxge_vBIT(val, 0, 8) 2473 #define VXGE_HW_CP_ERR_REG_CP_CP_ICACHE_SG_ERR(val) vxge_vBIT(val, 8, 2) 2474 #define VXGE_HW_CP_ERR_REG_CP_CP_DTAG_SG_ERR vxge_mBIT(10) 2475 #define VXGE_HW_CP_ERR_REG_CP_CP_ITAG_SG_ERR vxge_mBIT(11) 2476 #define VXGE_HW_CP_ERR_REG_CP_CP_TRACE_SG_ERR vxge_mBIT(12) 2477 #define VXGE_HW_CP_ERR_REG_CP_DMA2CP_SG_ERR vxge_mBIT(13) 2478 #define VXGE_HW_CP_ERR_REG_CP_MP2CP_SG_ERR vxge_mBIT(14) 2479 #define VXGE_HW_CP_ERR_REG_CP_QCC2CP_SG_ERR vxge_mBIT(15) 2480 #define VXGE_HW_CP_ERR_REG_CP_STC2CP_SG_ERR(val) vxge_vBIT(val, 16, 2) 2481 #define VXGE_HW_CP_ERR_REG_CP_CP_DCACHE_DB_ERR(val) vxge_vBIT(val, 24, 8) 2482 #define VXGE_HW_CP_ERR_REG_CP_CP_ICACHE_DB_ERR(val) vxge_vBIT(val, 32, 2) 2483 #define VXGE_HW_CP_ERR_REG_CP_CP_DTAG_DB_ERR vxge_mBIT(34) 2484 #define VXGE_HW_CP_ERR_REG_CP_CP_ITAG_DB_ERR vxge_mBIT(35) 2485 #define VXGE_HW_CP_ERR_REG_CP_CP_TRACE_DB_ERR vxge_mBIT(36) 2486 #define VXGE_HW_CP_ERR_REG_CP_DMA2CP_DB_ERR vxge_mBIT(37) 2487 #define VXGE_HW_CP_ERR_REG_CP_MP2CP_DB_ERR vxge_mBIT(38) 2488 #define VXGE_HW_CP_ERR_REG_CP_QCC2CP_DB_ERR vxge_mBIT(39) 2489 #define VXGE_HW_CP_ERR_REG_CP_STC2CP_DB_ERR(val) vxge_vBIT(val, 40, 2) 2490 #define VXGE_HW_CP_ERR_REG_CP_H2L2CP_FIFO_ERR vxge_mBIT(48) 2491 #define VXGE_HW_CP_ERR_REG_CP_STC2CP_FIFO_ERR vxge_mBIT(49) 2492 #define VXGE_HW_CP_ERR_REG_CP_STE2CP_FIFO_ERR vxge_mBIT(50) 2493 #define VXGE_HW_CP_ERR_REG_CP_TTE2CP_FIFO_ERR vxge_mBIT(51) 2494 #define VXGE_HW_CP_ERR_REG_CP_SWIF2CP_FIFO_ERR vxge_mBIT(52) 2495 #define VXGE_HW_CP_ERR_REG_CP_CP2DMA_FIFO_ERR vxge_mBIT(53) 2496 #define VXGE_HW_CP_ERR_REG_CP_DAM2CP_FIFO_ERR vxge_mBIT(54) 2497 #define VXGE_HW_CP_ERR_REG_CP_MP2CP_FIFO_ERR vxge_mBIT(55) 2498 #define VXGE_HW_CP_ERR_REG_CP_QCC2CP_FIFO_ERR vxge_mBIT(56) 2499 #define VXGE_HW_CP_ERR_REG_CP_DMA2CP_FIFO_ERR vxge_mBIT(57) 2500 #define VXGE_HW_CP_ERR_REG_CP_CP_WAKE_FSM_INTEGRITY_ERR vxge_mBIT(60) 2501 #define VXGE_HW_CP_ERR_REG_CP_CP_PMON_FSM_INTEGRITY_ERR vxge_mBIT(61) 2502 #define VXGE_HW_CP_ERR_REG_CP_DMA_RD_SHADOW_ERR vxge_mBIT(62) 2503 #define VXGE_HW_CP_ERR_REG_CP_PIFT_CREDIT_ERR vxge_mBIT(63) 2504 /*0x04f30*/ u64 cp_err_mask; 2505 /*0x04f38*/ u64 cp_err_alarm; 2506 u8 unused04fe8[0x04f50-0x04f40]; 2507 2508 /*0x04f50*/ u64 cp_exc_reg; 2509 #define VXGE_HW_CP_EXC_REG_CP_CP_CAUSE_INFO_INT vxge_mBIT(47) 2510 #define VXGE_HW_CP_EXC_REG_CP_CP_CAUSE_CRIT_INT vxge_mBIT(55) 2511 #define VXGE_HW_CP_EXC_REG_CP_CP_SERR vxge_mBIT(63) 2512 /*0x04f58*/ u64 cp_exc_mask; 2513 /*0x04f60*/ u64 cp_exc_alarm; 2514 /*0x04f68*/ u64 cp_exc_cause; 2515 #define VXGE_HW_CP_EXC_CAUSE_CP_CP_CAUSE(val) vxge_vBIT(val, 32, 32) 2516 u8 unused05200[0x05200-0x04f70]; 2517 2518 /*0x05200*/ u64 msg_int_status; 2519 #define VXGE_HW_MSG_INT_STATUS_TIM_ERR_TIM_INT vxge_mBIT(7) 2520 #define VXGE_HW_MSG_INT_STATUS_MSG_EXC_MSG_XT_EXC_INT vxge_mBIT(60) 2521 #define VXGE_HW_MSG_INT_STATUS_MSG_ERR3_MSG_ERR3_INT vxge_mBIT(61) 2522 #define VXGE_HW_MSG_INT_STATUS_MSG_ERR2_MSG_ERR2_INT vxge_mBIT(62) 2523 #define VXGE_HW_MSG_INT_STATUS_MSG_ERR_MSG_ERR_INT vxge_mBIT(63) 2524 /*0x05208*/ u64 msg_int_mask; 2525 /*0x05210*/ u64 tim_err_reg; 2526 #define VXGE_HW_TIM_ERR_REG_TIM_VBLS_SG_ERR vxge_mBIT(4) 2527 #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PA_SG_ERR vxge_mBIT(5) 2528 #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PB_SG_ERR vxge_mBIT(6) 2529 #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MSG_SG_ERR vxge_mBIT(7) 2530 #define VXGE_HW_TIM_ERR_REG_TIM_VBLS_DB_ERR vxge_mBIT(12) 2531 #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PA_DB_ERR vxge_mBIT(13) 2532 #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PB_DB_ERR vxge_mBIT(14) 2533 #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MSG_DB_ERR vxge_mBIT(15) 2534 #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MEM_CNTRL_SM_ERR vxge_mBIT(18) 2535 #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MSG_MEM_CNTRL_SM_ERR vxge_mBIT(19) 2536 #define VXGE_HW_TIM_ERR_REG_TIM_MPIF_PCIWR_ERR vxge_mBIT(20) 2537 #define VXGE_HW_TIM_ERR_REG_TIM_ROCRC_BMAP_UPDT_FIFO_ERR vxge_mBIT(22) 2538 #define VXGE_HW_TIM_ERR_REG_TIM_CREATE_BMAPMSG_FIFO_ERR vxge_mBIT(23) 2539 #define VXGE_HW_TIM_ERR_REG_TIM_ROCRCIF_MISMATCH vxge_mBIT(46) 2540 #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MAPPING_VP_ERR(n) vxge_mBIT(n) 2541 /*0x05218*/ u64 tim_err_mask; 2542 /*0x05220*/ u64 tim_err_alarm; 2543 /*0x05228*/ u64 msg_err_reg; 2544 #define VXGE_HW_MSG_ERR_REG_UP_UXP_WAKE_FSM_INTEGRITY_ERR vxge_mBIT(0) 2545 #define VXGE_HW_MSG_ERR_REG_MP_MXP_WAKE_FSM_INTEGRITY_ERR vxge_mBIT(1) 2546 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_DMA_READ_CMD_FSM_INTEGRITY_ERR \ 2547 vxge_mBIT(2) 2548 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_DMA_RESP_FSM_INTEGRITY_ERR \ 2549 vxge_mBIT(3) 2550 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_OWN_FSM_INTEGRITY_ERR vxge_mBIT(4) 2551 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_PDA_ACC_FSM_INTEGRITY_ERR vxge_mBIT(5) 2552 #define VXGE_HW_MSG_ERR_REG_MP_MXP_PMON_FSM_INTEGRITY_ERR vxge_mBIT(6) 2553 #define VXGE_HW_MSG_ERR_REG_UP_UXP_PMON_FSM_INTEGRITY_ERR vxge_mBIT(7) 2554 #define VXGE_HW_MSG_ERR_REG_UP_UXP_DTAG_SG_ERR vxge_mBIT(8) 2555 #define VXGE_HW_MSG_ERR_REG_UP_UXP_ITAG_SG_ERR vxge_mBIT(10) 2556 #define VXGE_HW_MSG_ERR_REG_MP_MXP_DTAG_SG_ERR vxge_mBIT(12) 2557 #define VXGE_HW_MSG_ERR_REG_MP_MXP_ITAG_SG_ERR vxge_mBIT(14) 2558 #define VXGE_HW_MSG_ERR_REG_UP_UXP_TRACE_SG_ERR vxge_mBIT(16) 2559 #define VXGE_HW_MSG_ERR_REG_MP_MXP_TRACE_SG_ERR vxge_mBIT(17) 2560 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_CMG2MSG_SG_ERR vxge_mBIT(18) 2561 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_TXPE2MSG_SG_ERR vxge_mBIT(19) 2562 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_RXPE2MSG_SG_ERR vxge_mBIT(20) 2563 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_RPE2MSG_SG_ERR vxge_mBIT(21) 2564 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_SG_ERR vxge_mBIT(26) 2565 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_BWR_PF_SG_ERR vxge_mBIT(27) 2566 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_ECC_SG_ERR vxge_mBIT(29) 2567 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_SG_ERR vxge_mBIT(31) 2568 #define VXGE_HW_MSG_ERR_REG_MSG_XFMDQRY_FSM_INTEGRITY_ERR vxge_mBIT(33) 2569 #define VXGE_HW_MSG_ERR_REG_MSG_FRMQRY_FSM_INTEGRITY_ERR vxge_mBIT(34) 2570 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_WRITE_FSM_INTEGRITY_ERR vxge_mBIT(35) 2571 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_BWR_PF_FSM_INTEGRITY_ERR \ 2572 vxge_mBIT(36) 2573 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_REG_RESP_FIFO_ERR vxge_mBIT(38) 2574 #define VXGE_HW_MSG_ERR_REG_UP_UXP_DTAG_DB_ERR vxge_mBIT(39) 2575 #define VXGE_HW_MSG_ERR_REG_UP_UXP_ITAG_DB_ERR vxge_mBIT(41) 2576 #define VXGE_HW_MSG_ERR_REG_MP_MXP_DTAG_DB_ERR vxge_mBIT(43) 2577 #define VXGE_HW_MSG_ERR_REG_MP_MXP_ITAG_DB_ERR vxge_mBIT(45) 2578 #define VXGE_HW_MSG_ERR_REG_UP_UXP_TRACE_DB_ERR vxge_mBIT(47) 2579 #define VXGE_HW_MSG_ERR_REG_MP_MXP_TRACE_DB_ERR vxge_mBIT(48) 2580 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_CMG2MSG_DB_ERR vxge_mBIT(49) 2581 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_TXPE2MSG_DB_ERR vxge_mBIT(50) 2582 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_RXPE2MSG_DB_ERR vxge_mBIT(51) 2583 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_RPE2MSG_DB_ERR vxge_mBIT(52) 2584 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_REG_READ_FIFO_ERR vxge_mBIT(53) 2585 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_MXP2UXP_FIFO_ERR vxge_mBIT(54) 2586 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_KDFC_SIF_FIFO_ERR vxge_mBIT(55) 2587 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_CXP2SWIF_FIFO_ERR vxge_mBIT(56) 2588 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_DB_ERR vxge_mBIT(57) 2589 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_BWR_PF_DB_ERR vxge_mBIT(58) 2590 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_BWR_SIF_FIFO_ERR vxge_mBIT(59) 2591 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_ECC_DB_ERR vxge_mBIT(60) 2592 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMA_READ_FIFO_ERR vxge_mBIT(61) 2593 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_DB_ERR vxge_mBIT(62) 2594 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_UXP2MXP_FIFO_ERR vxge_mBIT(63) 2595 /*0x05230*/ u64 msg_err_mask; 2596 /*0x05238*/ u64 msg_err_alarm; 2597 u8 unused05340[0x05340-0x05240]; 2598 2599 /*0x05340*/ u64 msg_exc_reg; 2600 #define VXGE_HW_MSG_EXC_REG_MP_MXP_CAUSE_INFO_INT vxge_mBIT(50) 2601 #define VXGE_HW_MSG_EXC_REG_MP_MXP_CAUSE_CRIT_INT vxge_mBIT(51) 2602 #define VXGE_HW_MSG_EXC_REG_UP_UXP_CAUSE_INFO_INT vxge_mBIT(54) 2603 #define VXGE_HW_MSG_EXC_REG_UP_UXP_CAUSE_CRIT_INT vxge_mBIT(55) 2604 #define VXGE_HW_MSG_EXC_REG_MP_MXP_SERR vxge_mBIT(62) 2605 #define VXGE_HW_MSG_EXC_REG_UP_UXP_SERR vxge_mBIT(63) 2606 /*0x05348*/ u64 msg_exc_mask; 2607 /*0x05350*/ u64 msg_exc_alarm; 2608 /*0x05358*/ u64 msg_exc_cause; 2609 #define VXGE_HW_MSG_EXC_CAUSE_MP_MXP(val) vxge_vBIT(val, 0, 32) 2610 #define VXGE_HW_MSG_EXC_CAUSE_UP_UXP(val) vxge_vBIT(val, 32, 32) 2611 u8 unused05368[0x05380-0x05360]; 2612 2613 /*0x05380*/ u64 msg_err2_reg; 2614 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_CMG2MSG_DISPATCH_FSM_INTEGRITY_ERR \ 2615 vxge_mBIT(0) 2616 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_DMQ_DISPATCH_FSM_INTEGRITY_ERR \ 2617 vxge_mBIT(1) 2618 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_SWIF_DISPATCH_FSM_INTEGRITY_ERR \ 2619 vxge_mBIT(2) 2620 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_PIC_WRITE_FSM_INTEGRITY_ERR \ 2621 vxge_mBIT(3) 2622 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_SWIFREG_FSM_INTEGRITY_ERR vxge_mBIT(4) 2623 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_TIM_WRITE_FSM_INTEGRITY_ERR \ 2624 vxge_mBIT(5) 2625 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_UMQ_TA_FSM_INTEGRITY_ERR vxge_mBIT(6) 2626 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_TXPE_TA_FSM_INTEGRITY_ERR vxge_mBIT(7) 2627 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_RXPE_TA_FSM_INTEGRITY_ERR vxge_mBIT(8) 2628 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_SWIF_TA_FSM_INTEGRITY_ERR vxge_mBIT(9) 2629 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_DMA_TA_FSM_INTEGRITY_ERR vxge_mBIT(10) 2630 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_CP_TA_FSM_INTEGRITY_ERR vxge_mBIT(11) 2631 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA16_FSM_INTEGRITY_ERR \ 2632 vxge_mBIT(12) 2633 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA15_FSM_INTEGRITY_ERR \ 2634 vxge_mBIT(13) 2635 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA14_FSM_INTEGRITY_ERR \ 2636 vxge_mBIT(14) 2637 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA13_FSM_INTEGRITY_ERR \ 2638 vxge_mBIT(15) 2639 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA12_FSM_INTEGRITY_ERR \ 2640 vxge_mBIT(16) 2641 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA11_FSM_INTEGRITY_ERR \ 2642 vxge_mBIT(17) 2643 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA10_FSM_INTEGRITY_ERR \ 2644 vxge_mBIT(18) 2645 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA9_FSM_INTEGRITY_ERR \ 2646 vxge_mBIT(19) 2647 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA8_FSM_INTEGRITY_ERR \ 2648 vxge_mBIT(20) 2649 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA7_FSM_INTEGRITY_ERR \ 2650 vxge_mBIT(21) 2651 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA6_FSM_INTEGRITY_ERR \ 2652 vxge_mBIT(22) 2653 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA5_FSM_INTEGRITY_ERR \ 2654 vxge_mBIT(23) 2655 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA4_FSM_INTEGRITY_ERR \ 2656 vxge_mBIT(24) 2657 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA3_FSM_INTEGRITY_ERR \ 2658 vxge_mBIT(25) 2659 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA2_FSM_INTEGRITY_ERR \ 2660 vxge_mBIT(26) 2661 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA1_FSM_INTEGRITY_ERR \ 2662 vxge_mBIT(27) 2663 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA0_FSM_INTEGRITY_ERR \ 2664 vxge_mBIT(28) 2665 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_FBMC_OWN_FSM_INTEGRITY_ERR vxge_mBIT(29) 2666 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_TXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR \ 2667 vxge_mBIT(30) 2668 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_RXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR \ 2669 vxge_mBIT(31) 2670 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_RPE2MSG_DISPATCH_FSM_INTEGRITY_ERR \ 2671 vxge_mBIT(32) 2672 #define VXGE_HW_MSG_ERR2_REG_MP_MP_PIFT_IF_CREDIT_CNT_ERR vxge_mBIT(33) 2673 #define VXGE_HW_MSG_ERR2_REG_UP_UP_PIFT_IF_CREDIT_CNT_ERR vxge_mBIT(34) 2674 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_UMQ2PIC_CMD_FIFO_ERR vxge_mBIT(62) 2675 #define VXGE_HW_MSG_ERR2_REG_TIM_TIM2MSG_CMD_FIFO_ERR vxge_mBIT(63) 2676 /*0x05388*/ u64 msg_err2_mask; 2677 /*0x05390*/ u64 msg_err2_alarm; 2678 /*0x05398*/ u64 msg_err3_reg; 2679 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR0 vxge_mBIT(0) 2680 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR1 vxge_mBIT(1) 2681 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR2 vxge_mBIT(2) 2682 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR3 vxge_mBIT(3) 2683 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR4 vxge_mBIT(4) 2684 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR5 vxge_mBIT(5) 2685 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR6 vxge_mBIT(6) 2686 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR7 vxge_mBIT(7) 2687 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_SG_ERR0 vxge_mBIT(8) 2688 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_SG_ERR1 vxge_mBIT(9) 2689 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR0 vxge_mBIT(16) 2690 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR1 vxge_mBIT(17) 2691 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR2 vxge_mBIT(18) 2692 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR3 vxge_mBIT(19) 2693 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR4 vxge_mBIT(20) 2694 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR5 vxge_mBIT(21) 2695 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR6 vxge_mBIT(22) 2696 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR7 vxge_mBIT(23) 2697 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_SG_ERR0 vxge_mBIT(24) 2698 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_SG_ERR1 vxge_mBIT(25) 2699 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR0 vxge_mBIT(32) 2700 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR1 vxge_mBIT(33) 2701 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR2 vxge_mBIT(34) 2702 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR3 vxge_mBIT(35) 2703 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR4 vxge_mBIT(36) 2704 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR5 vxge_mBIT(37) 2705 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR6 vxge_mBIT(38) 2706 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR7 vxge_mBIT(39) 2707 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR0 vxge_mBIT(40) 2708 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR1 vxge_mBIT(41) 2709 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR0 vxge_mBIT(48) 2710 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR1 vxge_mBIT(49) 2711 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR2 vxge_mBIT(50) 2712 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR3 vxge_mBIT(51) 2713 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR4 vxge_mBIT(52) 2714 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR5 vxge_mBIT(53) 2715 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR6 vxge_mBIT(54) 2716 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR7 vxge_mBIT(55) 2717 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR0 vxge_mBIT(56) 2718 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR1 vxge_mBIT(57) 2719 /*0x053a0*/ u64 msg_err3_mask; 2720 /*0x053a8*/ u64 msg_err3_alarm; 2721 u8 unused05600[0x05600-0x053b0]; 2722 2723 /*0x05600*/ u64 fau_gen_err_reg; 2724 #define VXGE_HW_FAU_GEN_ERR_REG_FMPF_PORT0_PERMANENT_STOP vxge_mBIT(3) 2725 #define VXGE_HW_FAU_GEN_ERR_REG_FMPF_PORT1_PERMANENT_STOP vxge_mBIT(7) 2726 #define VXGE_HW_FAU_GEN_ERR_REG_FMPF_PORT2_PERMANENT_STOP vxge_mBIT(11) 2727 #define VXGE_HW_FAU_GEN_ERR_REG_FALR_AUTO_LRO_NOTIFICATION vxge_mBIT(15) 2728 /*0x05608*/ u64 fau_gen_err_mask; 2729 /*0x05610*/ u64 fau_gen_err_alarm; 2730 /*0x05618*/ u64 fau_ecc_err_reg; 2731 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_SG_ERR vxge_mBIT(0) 2732 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_DB_ERR vxge_mBIT(1) 2733 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_SG_ERR(val) \ 2734 vxge_vBIT(val, 2, 2) 2735 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_DB_ERR(val) \ 2736 vxge_vBIT(val, 4, 2) 2737 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_SG_ERR vxge_mBIT(6) 2738 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_DB_ERR vxge_mBIT(7) 2739 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_SG_ERR(val) \ 2740 vxge_vBIT(val, 8, 2) 2741 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_DB_ERR(val) \ 2742 vxge_vBIT(val, 10, 2) 2743 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_SG_ERR vxge_mBIT(12) 2744 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_DB_ERR vxge_mBIT(13) 2745 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_SG_ERR(val) \ 2746 vxge_vBIT(val, 14, 2) 2747 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_DB_ERR(val) \ 2748 vxge_vBIT(val, 16, 2) 2749 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_SG_ERR(val) \ 2750 vxge_vBIT(val, 18, 2) 2751 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_DB_ERR(val) \ 2752 vxge_vBIT(val, 20, 2) 2753 #define VXGE_HW_FAU_ECC_ERR_REG_FAUJ_FAU_FSM_ERR vxge_mBIT(31) 2754 /*0x05620*/ u64 fau_ecc_err_mask; 2755 /*0x05628*/ u64 fau_ecc_err_alarm; 2756 u8 unused05658[0x05658-0x05630]; 2757 /*0x05658*/ u64 fau_pa_cfg; 2758 #define VXGE_HW_FAU_PA_CFG_REPL_L4_COMP_CSUM vxge_mBIT(3) 2759 #define VXGE_HW_FAU_PA_CFG_REPL_L3_INCL_CF vxge_mBIT(7) 2760 #define VXGE_HW_FAU_PA_CFG_REPL_L3_COMP_CSUM vxge_mBIT(11) 2761 u8 unused05668[0x05668-0x05660]; 2762 2763 /*0x05668*/ u64 dbg_stats_fau_rx_path; 2764 #define VXGE_HW_DBG_STATS_FAU_RX_PATH_RX_PERMITTED_FRMS(val) \ 2765 vxge_vBIT(val, 32, 32) 2766 u8 unused056c0[0x056c0-0x05670]; 2767 2768 /*0x056c0*/ u64 fau_lag_cfg; 2769 #define VXGE_HW_FAU_LAG_CFG_COLL_ALG(val) vxge_vBIT(val, 2, 2) 2770 #define VXGE_HW_FAU_LAG_CFG_INCR_RX_AGGR_STATS vxge_mBIT(7) 2771 u8 unused05800[0x05800-0x056c8]; 2772 2773 /*0x05800*/ u64 tpa_int_status; 2774 #define VXGE_HW_TPA_INT_STATUS_ORP_ERR_ORP_INT vxge_mBIT(15) 2775 #define VXGE_HW_TPA_INT_STATUS_PTM_ALARM_PTM_INT vxge_mBIT(23) 2776 #define VXGE_HW_TPA_INT_STATUS_TPA_ERROR_TPA_INT vxge_mBIT(31) 2777 /*0x05808*/ u64 tpa_int_mask; 2778 /*0x05810*/ u64 orp_err_reg; 2779 #define VXGE_HW_ORP_ERR_REG_ORP_FIFO_SG_ERR vxge_mBIT(3) 2780 #define VXGE_HW_ORP_ERR_REG_ORP_FIFO_DB_ERR vxge_mBIT(7) 2781 #define VXGE_HW_ORP_ERR_REG_ORP_XFMD_FIFO_UFLOW_ERR vxge_mBIT(11) 2782 #define VXGE_HW_ORP_ERR_REG_ORP_FRM_FIFO_UFLOW_ERR vxge_mBIT(15) 2783 #define VXGE_HW_ORP_ERR_REG_ORP_XFMD_RCV_FSM_ERR vxge_mBIT(19) 2784 #define VXGE_HW_ORP_ERR_REG_ORP_OUTREAD_FSM_ERR vxge_mBIT(23) 2785 #define VXGE_HW_ORP_ERR_REG_ORP_OUTQEM_FSM_ERR vxge_mBIT(27) 2786 #define VXGE_HW_ORP_ERR_REG_ORP_XFMD_RCV_SHADOW_ERR vxge_mBIT(31) 2787 #define VXGE_HW_ORP_ERR_REG_ORP_OUTREAD_SHADOW_ERR vxge_mBIT(35) 2788 #define VXGE_HW_ORP_ERR_REG_ORP_OUTQEM_SHADOW_ERR vxge_mBIT(39) 2789 #define VXGE_HW_ORP_ERR_REG_ORP_OUTFRM_SHADOW_ERR vxge_mBIT(43) 2790 #define VXGE_HW_ORP_ERR_REG_ORP_OPTPRS_SHADOW_ERR vxge_mBIT(47) 2791 /*0x05818*/ u64 orp_err_mask; 2792 /*0x05820*/ u64 orp_err_alarm; 2793 /*0x05828*/ u64 ptm_alarm_reg; 2794 #define VXGE_HW_PTM_ALARM_REG_PTM_RDCTRL_SYNC_ERR vxge_mBIT(3) 2795 #define VXGE_HW_PTM_ALARM_REG_PTM_RDCTRL_FIFO_ERR vxge_mBIT(7) 2796 #define VXGE_HW_PTM_ALARM_REG_XFMD_RD_FIFO_ERR vxge_mBIT(11) 2797 #define VXGE_HW_PTM_ALARM_REG_WDE2MSR_WR_FIFO_ERR vxge_mBIT(15) 2798 #define VXGE_HW_PTM_ALARM_REG_PTM_FRMM_ECC_DB_ERR(val) vxge_vBIT(val, 18, 2) 2799 #define VXGE_HW_PTM_ALARM_REG_PTM_FRMM_ECC_SG_ERR(val) vxge_vBIT(val, 22, 2) 2800 /*0x05830*/ u64 ptm_alarm_mask; 2801 /*0x05838*/ u64 ptm_alarm_alarm; 2802 /*0x05840*/ u64 tpa_error_reg; 2803 #define VXGE_HW_TPA_ERROR_REG_TPA_FSM_ERR_ALARM vxge_mBIT(3) 2804 #define VXGE_HW_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_DB_ERR vxge_mBIT(7) 2805 #define VXGE_HW_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_SG_ERR vxge_mBIT(11) 2806 /*0x05848*/ u64 tpa_error_mask; 2807 /*0x05850*/ u64 tpa_error_alarm; 2808 /*0x05858*/ u64 tpa_global_cfg; 2809 #define VXGE_HW_TPA_GLOBAL_CFG_SUPPORT_SNAP_AB_N vxge_mBIT(7) 2810 #define VXGE_HW_TPA_GLOBAL_CFG_ECC_ENABLE_N vxge_mBIT(35) 2811 u8 unused05868[0x05870-0x05860]; 2812 2813 /*0x05870*/ u64 ptm_ecc_cfg; 2814 #define VXGE_HW_PTM_ECC_CFG_PTM_FRMM_ECC_EN_N vxge_mBIT(3) 2815 /*0x05878*/ u64 ptm_phase_cfg; 2816 #define VXGE_HW_PTM_PHASE_CFG_FRMM_WR_PHASE_EN vxge_mBIT(3) 2817 #define VXGE_HW_PTM_PHASE_CFG_FRMM_RD_PHASE_EN vxge_mBIT(7) 2818 u8 unused05898[0x05898-0x05880]; 2819 2820 /*0x05898*/ u64 dbg_stats_tpa_tx_path; 2821 #define VXGE_HW_DBG_STATS_TPA_TX_PATH_TX_PERMITTED_FRMS(val) \ 2822 vxge_vBIT(val, 32, 32) 2823 u8 unused05900[0x05900-0x058a0]; 2824 2825 /*0x05900*/ u64 tmac_int_status; 2826 #define VXGE_HW_TMAC_INT_STATUS_TXMAC_GEN_ERR_TXMAC_GEN_INT vxge_mBIT(3) 2827 #define VXGE_HW_TMAC_INT_STATUS_TXMAC_ECC_ERR_TXMAC_ECC_INT vxge_mBIT(7) 2828 /*0x05908*/ u64 tmac_int_mask; 2829 /*0x05910*/ u64 txmac_gen_err_reg; 2830 #define VXGE_HW_TXMAC_GEN_ERR_REG_TMACJ_PERMANENT_STOP vxge_mBIT(3) 2831 #define VXGE_HW_TXMAC_GEN_ERR_REG_TMACJ_NO_VALID_VSPORT vxge_mBIT(7) 2832 /*0x05918*/ u64 txmac_gen_err_mask; 2833 /*0x05920*/ u64 txmac_gen_err_alarm; 2834 /*0x05928*/ u64 txmac_ecc_err_reg; 2835 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_SG_ERR vxge_mBIT(3) 2836 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_DB_ERR vxge_mBIT(7) 2837 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_SG_ERR vxge_mBIT(11) 2838 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_DB_ERR vxge_mBIT(15) 2839 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_SG_ERR vxge_mBIT(19) 2840 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_DB_ERR vxge_mBIT(23) 2841 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT0_FSM_ERR vxge_mBIT(27) 2842 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT1_FSM_ERR vxge_mBIT(31) 2843 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT2_FSM_ERR vxge_mBIT(35) 2844 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMACJ_FSM_ERR vxge_mBIT(39) 2845 /*0x05930*/ u64 txmac_ecc_err_mask; 2846 /*0x05938*/ u64 txmac_ecc_err_alarm; 2847 u8 unused05978[0x05978-0x05940]; 2848 2849 /*0x05978*/ u64 dbg_stat_tx_any_frms; 2850 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT0_TX_ANY_FRMS(val) vxge_vBIT(val, 0, 8) 2851 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT1_TX_ANY_FRMS(val) vxge_vBIT(val, 8, 8) 2852 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT2_TX_ANY_FRMS(val) \ 2853 vxge_vBIT(val, 16, 8) 2854 u8 unused059a0[0x059a0-0x05980]; 2855 2856 /*0x059a0*/ u64 txmac_link_util_port[3]; 2857 #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_UTILIZATION(val) \ 2858 vxge_vBIT(val, 1, 7) 2859 #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(val) vxge_vBIT(val, 8, 4) 2860 #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_FRAC_UTIL(val) \ 2861 vxge_vBIT(val, 12, 4) 2862 #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_PKT_WEIGHT(val) vxge_vBIT(val, 16, 4) 2863 #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_SCALE_FACTOR vxge_mBIT(23) 2864 /*0x059b8*/ u64 txmac_cfg0_port[3]; 2865 #define VXGE_HW_TXMAC_CFG0_PORT_TMAC_EN vxge_mBIT(3) 2866 #define VXGE_HW_TXMAC_CFG0_PORT_APPEND_PAD vxge_mBIT(7) 2867 #define VXGE_HW_TXMAC_CFG0_PORT_PAD_BYTE(val) vxge_vBIT(val, 8, 8) 2868 /*0x059d0*/ u64 txmac_cfg1_port[3]; 2869 #define VXGE_HW_TXMAC_CFG1_PORT_AVG_IPG(val) vxge_vBIT(val, 40, 8) 2870 /*0x059e8*/ u64 txmac_status_port[3]; 2871 #define VXGE_HW_TXMAC_STATUS_PORT_TMAC_TX_FRM_SENT vxge_mBIT(3) 2872 u8 unused05a20[0x05a20-0x05a00]; 2873 2874 /*0x05a20*/ u64 lag_distrib_dest; 2875 #define VXGE_HW_LAG_DISTRIB_DEST_MAP_VPATH(n) vxge_mBIT(n) 2876 /*0x05a28*/ u64 lag_marker_cfg; 2877 #define VXGE_HW_LAG_MARKER_CFG_GEN_RCVR_EN vxge_mBIT(3) 2878 #define VXGE_HW_LAG_MARKER_CFG_RESP_EN vxge_mBIT(7) 2879 #define VXGE_HW_LAG_MARKER_CFG_RESP_TIMEOUT(val) vxge_vBIT(val, 16, 16) 2880 #define VXGE_HW_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL(val) \ 2881 vxge_vBIT(val, 32, 16) 2882 #define VXGE_HW_LAG_MARKER_CFG_THROTTLE_MRKR_RESP vxge_mBIT(51) 2883 /*0x05a30*/ u64 lag_tx_cfg; 2884 #define VXGE_HW_LAG_TX_CFG_INCR_TX_AGGR_STATS vxge_mBIT(3) 2885 #define VXGE_HW_LAG_TX_CFG_DISTRIB_ALG_SEL(val) vxge_vBIT(val, 6, 2) 2886 #define VXGE_HW_LAG_TX_CFG_DISTRIB_REMAP_IF_FAIL vxge_mBIT(11) 2887 #define VXGE_HW_LAG_TX_CFG_COLL_MAX_DELAY(val) vxge_vBIT(val, 16, 16) 2888 /*0x05a38*/ u64 lag_tx_status; 2889 #define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_EMPTIED_LINK(val) \ 2890 vxge_vBIT(val, 0, 8) 2891 #define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKR(val) \ 2892 vxge_vBIT(val, 8, 8) 2893 #define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKRRESP(val) \ 2894 vxge_vBIT(val, 16, 8) 2895 u8 unused05d48[0x05d48-0x05a40]; 2896 2897 /*0x05d48*/ u64 srpcim_to_mrpcim_vplane_rmsg[17]; 2898 #define \ 2899 VXGE_HAL_SRPCIM_TO_MRPCIM_VPLANE_RMSG_SWIF_SRPCIM_TO_MRPCIM_VPLANE_RMSG(val)\ 2900 vxge_vBIT(val, 0, 64) 2901 u8 unused06420[0x06420-0x05dd0]; 2902 2903 /*0x06420*/ u64 mrpcim_to_srpcim_vplane_wmsg[17]; 2904 #define VXGE_HW_MRPCIM_TO_SRPCIM_VPLANE_WMSG_MRPCIM_TO_SRPCIM_VPLANE_WMSG(val) \ 2905 vxge_vBIT(val, 0, 64) 2906 /*0x064a8*/ u64 mrpcim_to_srpcim_vplane_wmsg_trig[17]; 2907 2908 /*0x06530*/ u64 debug_stats0; 2909 #define VXGE_HW_DEBUG_STATS0_RSTDROP_MSG(val) vxge_vBIT(val, 0, 32) 2910 #define VXGE_HW_DEBUG_STATS0_RSTDROP_CPL(val) vxge_vBIT(val, 32, 32) 2911 /*0x06538*/ u64 debug_stats1; 2912 #define VXGE_HW_DEBUG_STATS1_RSTDROP_CLIENT0(val) vxge_vBIT(val, 0, 32) 2913 #define VXGE_HW_DEBUG_STATS1_RSTDROP_CLIENT1(val) vxge_vBIT(val, 32, 32) 2914 /*0x06540*/ u64 debug_stats2; 2915 #define VXGE_HW_DEBUG_STATS2_RSTDROP_CLIENT2(val) vxge_vBIT(val, 0, 32) 2916 /*0x06548*/ u64 debug_stats3_vplane[17]; 2917 #define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_PH(val) vxge_vBIT(val, 0, 16) 2918 #define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_NPH(val) vxge_vBIT(val, 16, 16) 2919 #define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_CPLH(val) vxge_vBIT(val, 32, 16) 2920 /*0x065d0*/ u64 debug_stats4_vplane[17]; 2921 #define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_PD(val) vxge_vBIT(val, 0, 16) 2922 #define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_NPD(val) vxge_vBIT(val, 16, 16) 2923 #define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_CPLD(val) vxge_vBIT(val, 32, 16) 2924 2925 u8 unused07000[0x07000-0x06658]; 2926 2927 /*0x07000*/ u64 mrpcim_general_int_status; 2928 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PIC_INT vxge_mBIT(0) 2929 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCI_INT vxge_mBIT(1) 2930 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_RTDMA_INT vxge_mBIT(2) 2931 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_WRDMA_INT vxge_mBIT(3) 2932 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3CMCT_INT vxge_mBIT(4) 2933 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_GCMG1_INT vxge_mBIT(5) 2934 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_GCMG2_INT vxge_mBIT(6) 2935 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_GCMG3_INT vxge_mBIT(7) 2936 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3CMIFL_INT vxge_mBIT(8) 2937 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3CMIFU_INT vxge_mBIT(9) 2938 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCMG1_INT vxge_mBIT(10) 2939 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCMG2_INT vxge_mBIT(11) 2940 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCMG3_INT vxge_mBIT(12) 2941 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_XMAC_INT vxge_mBIT(13) 2942 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_RXMAC_INT vxge_mBIT(14) 2943 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_TMAC_INT vxge_mBIT(15) 2944 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3FBIF_INT vxge_mBIT(16) 2945 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_FBMC_INT vxge_mBIT(17) 2946 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3FBCT_INT vxge_mBIT(18) 2947 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_TPA_INT vxge_mBIT(19) 2948 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_DRBELL_INT vxge_mBIT(20) 2949 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_ONE_INT vxge_mBIT(21) 2950 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_MSG_INT vxge_mBIT(22) 2951 /*0x07008*/ u64 mrpcim_general_int_mask; 2952 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PIC_INT vxge_mBIT(0) 2953 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCI_INT vxge_mBIT(1) 2954 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_RTDMA_INT vxge_mBIT(2) 2955 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_WRDMA_INT vxge_mBIT(3) 2956 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3CMCT_INT vxge_mBIT(4) 2957 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_GCMG1_INT vxge_mBIT(5) 2958 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_GCMG2_INT vxge_mBIT(6) 2959 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_GCMG3_INT vxge_mBIT(7) 2960 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3CMIFL_INT vxge_mBIT(8) 2961 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3CMIFU_INT vxge_mBIT(9) 2962 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCMG1_INT vxge_mBIT(10) 2963 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCMG2_INT vxge_mBIT(11) 2964 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCMG3_INT vxge_mBIT(12) 2965 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_XMAC_INT vxge_mBIT(13) 2966 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_RXMAC_INT vxge_mBIT(14) 2967 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_TMAC_INT vxge_mBIT(15) 2968 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3FBIF_INT vxge_mBIT(16) 2969 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_FBMC_INT vxge_mBIT(17) 2970 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3FBCT_INT vxge_mBIT(18) 2971 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_TPA_INT vxge_mBIT(19) 2972 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_DRBELL_INT vxge_mBIT(20) 2973 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_ONE_INT vxge_mBIT(21) 2974 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_MSG_INT vxge_mBIT(22) 2975 /*0x07010*/ u64 mrpcim_ppif_int_status; 2976 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_INI_ERRORS_INI_INT vxge_mBIT(3) 2977 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_DMA_ERRORS_DMA_INT vxge_mBIT(7) 2978 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_TGT_ERRORS_TGT_INT vxge_mBIT(11) 2979 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CONFIG_ERRORS_CONFIG_INT vxge_mBIT(15) 2980 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_CRDT_INT vxge_mBIT(19) 2981 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_PLL_ERRORS_PLL_INT vxge_mBIT(27) 2982 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE0_CRD_INT_VPLANE0_INT\ 2983 vxge_mBIT(31) 2984 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE1_CRD_INT_VPLANE1_INT\ 2985 vxge_mBIT(32) 2986 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE2_CRD_INT_VPLANE2_INT\ 2987 vxge_mBIT(33) 2988 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE3_CRD_INT_VPLANE3_INT\ 2989 vxge_mBIT(34) 2990 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE4_CRD_INT_VPLANE4_INT\ 2991 vxge_mBIT(35) 2992 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE5_CRD_INT_VPLANE5_INT\ 2993 vxge_mBIT(36) 2994 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE6_CRD_INT_VPLANE6_INT\ 2995 vxge_mBIT(37) 2996 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE7_CRD_INT_VPLANE7_INT\ 2997 vxge_mBIT(38) 2998 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE8_CRD_INT_VPLANE8_INT\ 2999 vxge_mBIT(39) 3000 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE9_CRD_INT_VPLANE9_INT\ 3001 vxge_mBIT(40) 3002 #define \ 3003 VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE10_CRD_INT_VPLANE10_INT \ 3004 vxge_mBIT(41) 3005 #define \ 3006 VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE11_CRD_INT_VPLANE11_INT \ 3007 vxge_mBIT(42) 3008 #define \ 3009 VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE12_CRD_INT_VPLANE12_INT \ 3010 vxge_mBIT(43) 3011 #define \ 3012 VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE13_CRD_INT_VPLANE13_INT \ 3013 vxge_mBIT(44) 3014 #define \ 3015 VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE14_CRD_INT_VPLANE14_INT \ 3016 vxge_mBIT(45) 3017 #define \ 3018 VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE15_CRD_INT_VPLANE15_INT \ 3019 vxge_mBIT(46) 3020 #define \ 3021 VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE16_CRD_INT_VPLANE16_INT \ 3022 vxge_mBIT(47) 3023 #define \ 3024 VXGE_HW_MRPCIM_PPIF_INT_STATUS_VPATH_TO_MRPCIM_ALARM_VPATH_TO_MRPCIM_ALARM_INT \ 3025 vxge_mBIT(55) 3026 /*0x07018*/ u64 mrpcim_ppif_int_mask; 3027 u8 unused07028[0x07028-0x07020]; 3028 3029 /*0x07028*/ u64 ini_errors_reg; 3030 #define VXGE_HW_INI_ERRORS_REG_SCPL_CPL_TIMEOUT_UNUSED_TAG vxge_mBIT(3) 3031 #define VXGE_HW_INI_ERRORS_REG_SCPL_CPL_TIMEOUT vxge_mBIT(7) 3032 #define VXGE_HW_INI_ERRORS_REG_DCPL_FSM_ERR vxge_mBIT(11) 3033 #define VXGE_HW_INI_ERRORS_REG_DCPL_POISON vxge_mBIT(12) 3034 #define VXGE_HW_INI_ERRORS_REG_DCPL_UNSUPPORTED vxge_mBIT(15) 3035 #define VXGE_HW_INI_ERRORS_REG_DCPL_ABORT vxge_mBIT(19) 3036 #define VXGE_HW_INI_ERRORS_REG_INI_TLP_ABORT vxge_mBIT(23) 3037 #define VXGE_HW_INI_ERRORS_REG_INI_DLLP_ABORT vxge_mBIT(27) 3038 #define VXGE_HW_INI_ERRORS_REG_INI_ECRC_ERR vxge_mBIT(31) 3039 #define VXGE_HW_INI_ERRORS_REG_INI_BUF_DB_ERR vxge_mBIT(35) 3040 #define VXGE_HW_INI_ERRORS_REG_INI_BUF_SG_ERR vxge_mBIT(39) 3041 #define VXGE_HW_INI_ERRORS_REG_INI_DATA_OVERFLOW vxge_mBIT(43) 3042 #define VXGE_HW_INI_ERRORS_REG_INI_HDR_OVERFLOW vxge_mBIT(47) 3043 #define VXGE_HW_INI_ERRORS_REG_INI_MRD_SYS_DROP vxge_mBIT(51) 3044 #define VXGE_HW_INI_ERRORS_REG_INI_MWR_SYS_DROP vxge_mBIT(55) 3045 #define VXGE_HW_INI_ERRORS_REG_INI_MRD_CLIENT_DROP vxge_mBIT(59) 3046 #define VXGE_HW_INI_ERRORS_REG_INI_MWR_CLIENT_DROP vxge_mBIT(63) 3047 /*0x07030*/ u64 ini_errors_mask; 3048 /*0x07038*/ u64 ini_errors_alarm; 3049 /*0x07040*/ u64 dma_errors_reg; 3050 #define VXGE_HW_DMA_ERRORS_REG_RDARB_FSM_ERR vxge_mBIT(3) 3051 #define VXGE_HW_DMA_ERRORS_REG_WRARB_FSM_ERR vxge_mBIT(7) 3052 #define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_OVERFLOW vxge_mBIT(8) 3053 #define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_UNDERFLOW vxge_mBIT(9) 3054 #define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_OVERFLOW vxge_mBIT(10) 3055 #define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_UNDERFLOW vxge_mBIT(11) 3056 #define VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_HDR_OVERFLOW vxge_mBIT(12) 3057 #define VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_HDR_UNDERFLOW vxge_mBIT(13) 3058 #define VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_DATA_OVERFLOW vxge_mBIT(14) 3059 #define VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_DATA_UNDERFLOW vxge_mBIT(15) 3060 #define VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_HDR_OVERFLOW vxge_mBIT(16) 3061 #define VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_HDR_UNDERFLOW vxge_mBIT(17) 3062 #define VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_DATA_OVERFLOW vxge_mBIT(18) 3063 #define VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_DATA_UNDERFLOW vxge_mBIT(19) 3064 #define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_OVERFLOW vxge_mBIT(20) 3065 #define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_UNDERFLOW vxge_mBIT(21) 3066 #define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_OVERFLOW vxge_mBIT(22) 3067 #define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_UNDERFLOW vxge_mBIT(23) 3068 #define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_OVERFLOW vxge_mBIT(24) 3069 #define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_UNDERFLOW vxge_mBIT(25) 3070 #define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_OVERFLOW vxge_mBIT(28) 3071 #define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_UNDERFLOW vxge_mBIT(29) 3072 #define VXGE_HW_DMA_ERRORS_REG_DBLGEN_FSM_ERR vxge_mBIT(32) 3073 #define VXGE_HW_DMA_ERRORS_REG_DBLGEN_CREDIT_FSM_ERR vxge_mBIT(33) 3074 #define VXGE_HW_DMA_ERRORS_REG_DBLGEN_DMA_WRR_SM_ERR vxge_mBIT(34) 3075 /*0x07048*/ u64 dma_errors_mask; 3076 /*0x07050*/ u64 dma_errors_alarm; 3077 /*0x07058*/ u64 tgt_errors_reg; 3078 #define VXGE_HW_TGT_ERRORS_REG_TGT_VENDOR_MSG vxge_mBIT(0) 3079 #define VXGE_HW_TGT_ERRORS_REG_TGT_MSG_UNLOCK vxge_mBIT(1) 3080 #define VXGE_HW_TGT_ERRORS_REG_TGT_ILLEGAL_TLP_BE vxge_mBIT(2) 3081 #define VXGE_HW_TGT_ERRORS_REG_TGT_BOOT_WRITE vxge_mBIT(3) 3082 #define VXGE_HW_TGT_ERRORS_REG_TGT_PIF_WR_CROSS_QWRANGE vxge_mBIT(4) 3083 #define VXGE_HW_TGT_ERRORS_REG_TGT_PIF_READ_CROSS_QWRANGE vxge_mBIT(5) 3084 #define VXGE_HW_TGT_ERRORS_REG_TGT_KDFC_READ vxge_mBIT(6) 3085 #define VXGE_HW_TGT_ERRORS_REG_TGT_USDC_READ vxge_mBIT(7) 3086 #define VXGE_HW_TGT_ERRORS_REG_TGT_USDC_WR_CROSS_QWRANGE vxge_mBIT(8) 3087 #define VXGE_HW_TGT_ERRORS_REG_TGT_MSIX_BEYOND_RANGE vxge_mBIT(9) 3088 #define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_KDFC_POISON vxge_mBIT(10) 3089 #define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_USDC_POISON vxge_mBIT(11) 3090 #define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_PIF_POISON vxge_mBIT(12) 3091 #define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_MSIX_POISON vxge_mBIT(13) 3092 #define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_MRIOV_POISON vxge_mBIT(14) 3093 #define VXGE_HW_TGT_ERRORS_REG_TGT_NOT_MEM_TLP vxge_mBIT(15) 3094 #define VXGE_HW_TGT_ERRORS_REG_TGT_UNKNOWN_MEM_TLP vxge_mBIT(16) 3095 #define VXGE_HW_TGT_ERRORS_REG_TGT_REQ_FSM_ERR vxge_mBIT(17) 3096 #define VXGE_HW_TGT_ERRORS_REG_TGT_CPL_FSM_ERR vxge_mBIT(18) 3097 #define VXGE_HW_TGT_ERRORS_REG_TGT_KDFC_PROT_ERR vxge_mBIT(19) 3098 #define VXGE_HW_TGT_ERRORS_REG_TGT_SWIF_PROT_ERR vxge_mBIT(20) 3099 #define VXGE_HW_TGT_ERRORS_REG_TGT_MRIOV_MEM_MAP_CFG_ERR vxge_mBIT(21) 3100 /*0x07060*/ u64 tgt_errors_mask; 3101 /*0x07068*/ u64 tgt_errors_alarm; 3102 /*0x07070*/ u64 config_errors_reg; 3103 #define VXGE_HW_CONFIG_ERRORS_REG_I2C_ILLEGAL_STOP_COND vxge_mBIT(3) 3104 #define VXGE_HW_CONFIG_ERRORS_REG_I2C_ILLEGAL_START_COND vxge_mBIT(7) 3105 #define VXGE_HW_CONFIG_ERRORS_REG_I2C_EXP_RD_CNT vxge_mBIT(11) 3106 #define VXGE_HW_CONFIG_ERRORS_REG_I2C_EXTRA_CYCLE vxge_mBIT(15) 3107 #define VXGE_HW_CONFIG_ERRORS_REG_I2C_MAIN_FSM_ERR vxge_mBIT(19) 3108 #define VXGE_HW_CONFIG_ERRORS_REG_I2C_REQ_COLLISION vxge_mBIT(23) 3109 #define VXGE_HW_CONFIG_ERRORS_REG_I2C_REG_FSM_ERR vxge_mBIT(27) 3110 #define VXGE_HW_CONFIG_ERRORS_REG_CFGM_I2C_TIMEOUT vxge_mBIT(31) 3111 #define VXGE_HW_CONFIG_ERRORS_REG_RIC_I2C_TIMEOUT vxge_mBIT(35) 3112 #define VXGE_HW_CONFIG_ERRORS_REG_CFGM_FSM_ERR vxge_mBIT(39) 3113 #define VXGE_HW_CONFIG_ERRORS_REG_RIC_FSM_ERR vxge_mBIT(43) 3114 #define VXGE_HW_CONFIG_ERRORS_REG_PIFM_ILLEGAL_ACCESS vxge_mBIT(47) 3115 #define VXGE_HW_CONFIG_ERRORS_REG_PIFM_TIMEOUT vxge_mBIT(51) 3116 #define VXGE_HW_CONFIG_ERRORS_REG_PIFM_FSM_ERR vxge_mBIT(55) 3117 #define VXGE_HW_CONFIG_ERRORS_REG_PIFM_TO_FSM_ERR vxge_mBIT(59) 3118 #define VXGE_HW_CONFIG_ERRORS_REG_RIC_RIC_RD_TIMEOUT vxge_mBIT(63) 3119 /*0x07078*/ u64 config_errors_mask; 3120 /*0x07080*/ u64 config_errors_alarm; 3121 u8 unused07090[0x07090-0x07088]; 3122 3123 /*0x07090*/ u64 crdt_errors_reg; 3124 #define VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_FSM_ERR vxge_mBIT(11) 3125 #define VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_INTCTL_ILLEGAL_CRD_DEAL \ 3126 vxge_mBIT(15) 3127 #define VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_PDA_ILLEGAL_CRD_DEAL vxge_mBIT(19) 3128 #define VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_PCI_MSG_ILLEGAL_CRD_DEAL \ 3129 vxge_mBIT(23) 3130 #define VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_FSM_ERR vxge_mBIT(35) 3131 #define VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_RDA_ILLEGAL_CRD_DEAL vxge_mBIT(39) 3132 #define VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_PDA_ILLEGAL_CRD_DEAL vxge_mBIT(43) 3133 #define VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_DBLGEN_ILLEGAL_CRD_DEAL \ 3134 vxge_mBIT(47) 3135 /*0x07098*/ u64 crdt_errors_mask; 3136 /*0x070a0*/ u64 crdt_errors_alarm; 3137 u8 unused070b0[0x070b0-0x070a8]; 3138 3139 /*0x070b0*/ u64 mrpcim_general_errors_reg; 3140 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_STATSB_FSM_ERR vxge_mBIT(3) 3141 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_XGEN_FSM_ERR vxge_mBIT(7) 3142 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_XMEM_FSM_ERR vxge_mBIT(11) 3143 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_KDFCCTL_FSM_ERR vxge_mBIT(15) 3144 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_MRIOVCTL_FSM_ERR vxge_mBIT(19) 3145 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_SPI_FLSH_ERR vxge_mBIT(23) 3146 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_ACK_ERR vxge_mBIT(27) 3147 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_CHKSUM_ERR vxge_mBIT(31) 3148 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_INI_SERR_DET vxge_mBIT(35) 3149 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSIX_FSM_ERR vxge_mBIT(39) 3150 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSI_OVERFLOW vxge_mBIT(43) 3151 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_PPIF_PCI_NOT_FLUSH_DURING_SW_RESET \ 3152 vxge_mBIT(47) 3153 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_PPIF_SW_RESET_FSM_ERR vxge_mBIT(51) 3154 /*0x070b8*/ u64 mrpcim_general_errors_mask; 3155 /*0x070c0*/ u64 mrpcim_general_errors_alarm; 3156 u8 unused070d0[0x070d0-0x070c8]; 3157 3158 /*0x070d0*/ u64 pll_errors_reg; 3159 #define VXGE_HW_PLL_ERRORS_REG_CORE_CMG_PLL_OOL vxge_mBIT(3) 3160 #define VXGE_HW_PLL_ERRORS_REG_CORE_FB_PLL_OOL vxge_mBIT(7) 3161 #define VXGE_HW_PLL_ERRORS_REG_CORE_X_PLL_OOL vxge_mBIT(11) 3162 /*0x070d8*/ u64 pll_errors_mask; 3163 /*0x070e0*/ u64 pll_errors_alarm; 3164 /*0x070e8*/ u64 srpcim_to_mrpcim_alarm_reg; 3165 #define VXGE_HW_SRPCIM_TO_MRPCIM_ALARM_REG_PPIF_SRPCIM_TO_MRPCIM_ALARM(val) \ 3166 vxge_vBIT(val, 0, 17) 3167 /*0x070f0*/ u64 srpcim_to_mrpcim_alarm_mask; 3168 /*0x070f8*/ u64 srpcim_to_mrpcim_alarm_alarm; 3169 /*0x07100*/ u64 vpath_to_mrpcim_alarm_reg; 3170 #define VXGE_HW_VPATH_TO_MRPCIM_ALARM_REG_PPIF_VPATH_TO_MRPCIM_ALARM(val) \ 3171 vxge_vBIT(val, 0, 17) 3172 /*0x07108*/ u64 vpath_to_mrpcim_alarm_mask; 3173 /*0x07110*/ u64 vpath_to_mrpcim_alarm_alarm; 3174 u8 unused07128[0x07128-0x07118]; 3175 3176 /*0x07128*/ u64 crdt_errors_vplane_reg[17]; 3177 #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_H_CONSUME_CRDT_ERR \ 3178 vxge_mBIT(3) 3179 #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_D_CONSUME_CRDT_ERR \ 3180 vxge_mBIT(7) 3181 #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_H_RETURN_CRDT_ERR \ 3182 vxge_mBIT(11) 3183 #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_D_RETURN_CRDT_ERR \ 3184 vxge_mBIT(15) 3185 #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_NP_H_CONSUME_CRDT_ERR \ 3186 vxge_mBIT(19) 3187 #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_NP_H_RETURN_CRDT_ERR \ 3188 vxge_mBIT(23) 3189 #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_TAG_CONSUME_TAG_ERR \ 3190 vxge_mBIT(27) 3191 #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_TAG_RETURN_TAG_ERR \ 3192 vxge_mBIT(31) 3193 /*0x07130*/ u64 crdt_errors_vplane_mask[17]; 3194 /*0x07138*/ u64 crdt_errors_vplane_alarm[17]; 3195 u8 unused072f0[0x072f0-0x072c0]; 3196 3197 /*0x072f0*/ u64 mrpcim_rst_in_prog; 3198 #define VXGE_HW_MRPCIM_RST_IN_PROG_MRPCIM_RST_IN_PROG vxge_mBIT(7) 3199 /*0x072f8*/ u64 mrpcim_reg_modified; 3200 #define VXGE_HW_MRPCIM_REG_MODIFIED_MRPCIM_REG_MODIFIED vxge_mBIT(7) 3201 3202 u8 unused07378[0x07378-0x07300]; 3203 3204 /*0x07378*/ u64 write_arb_pending; 3205 #define VXGE_HW_WRITE_ARB_PENDING_WRARB_WRDMA vxge_mBIT(3) 3206 #define VXGE_HW_WRITE_ARB_PENDING_WRARB_RTDMA vxge_mBIT(7) 3207 #define VXGE_HW_WRITE_ARB_PENDING_WRARB_MSG vxge_mBIT(11) 3208 #define VXGE_HW_WRITE_ARB_PENDING_WRARB_STATSB vxge_mBIT(15) 3209 #define VXGE_HW_WRITE_ARB_PENDING_WRARB_INTCTL vxge_mBIT(19) 3210 /*0x07380*/ u64 read_arb_pending; 3211 #define VXGE_HW_READ_ARB_PENDING_RDARB_WRDMA vxge_mBIT(3) 3212 #define VXGE_HW_READ_ARB_PENDING_RDARB_RTDMA vxge_mBIT(7) 3213 #define VXGE_HW_READ_ARB_PENDING_RDARB_DBLGEN vxge_mBIT(11) 3214 /*0x07388*/ u64 dmaif_dmadbl_pending; 3215 #define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_WRDMA_WR vxge_mBIT(0) 3216 #define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_WRDMA_RD vxge_mBIT(1) 3217 #define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_RTDMA_WR vxge_mBIT(2) 3218 #define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_RTDMA_RD vxge_mBIT(3) 3219 #define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_MSG_WR vxge_mBIT(4) 3220 #define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_STATS_WR vxge_mBIT(5) 3221 #define VXGE_HW_DMAIF_DMADBL_PENDING_DBLGEN_IN_PROG(val) \ 3222 vxge_vBIT(val, 13, 51) 3223 /*0x07390*/ u64 wrcrdtarb_status0_vplane[17]; 3224 #define VXGE_HW_WRCRDTARB_STATUS0_VPLANE_WRCRDTARB_ABS_AVAIL_P_H(val) \ 3225 vxge_vBIT(val, 0, 8) 3226 /*0x07418*/ u64 wrcrdtarb_status1_vplane[17]; 3227 #define VXGE_HW_WRCRDTARB_STATUS1_VPLANE_WRCRDTARB_ABS_AVAIL_P_D(val) \ 3228 vxge_vBIT(val, 4, 12) 3229 u8 unused07500[0x07500-0x074a0]; 3230 3231 /*0x07500*/ u64 mrpcim_general_cfg1; 3232 #define VXGE_HW_MRPCIM_GENERAL_CFG1_CLEAR_SERR vxge_mBIT(7) 3233 /*0x07508*/ u64 mrpcim_general_cfg2; 3234 #define VXGE_HW_MRPCIM_GENERAL_CFG2_INS_TX_WR_TD vxge_mBIT(3) 3235 #define VXGE_HW_MRPCIM_GENERAL_CFG2_INS_TX_RD_TD vxge_mBIT(7) 3236 #define VXGE_HW_MRPCIM_GENERAL_CFG2_INS_TX_CPL_TD vxge_mBIT(11) 3237 #define VXGE_HW_MRPCIM_GENERAL_CFG2_INI_TIMEOUT_EN_MWR vxge_mBIT(15) 3238 #define VXGE_HW_MRPCIM_GENERAL_CFG2_INI_TIMEOUT_EN_MRD vxge_mBIT(19) 3239 #define VXGE_HW_MRPCIM_GENERAL_CFG2_IGNORE_VPATH_RST_FOR_MSIX vxge_mBIT(23) 3240 #define VXGE_HW_MRPCIM_GENERAL_CFG2_FLASH_READ_MSB vxge_mBIT(27) 3241 #define VXGE_HW_MRPCIM_GENERAL_CFG2_DIS_HOST_PIPELINE_WR vxge_mBIT(31) 3242 #define VXGE_HW_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE vxge_mBIT(43) 3243 #define VXGE_HW_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH(val) \ 3244 vxge_vBIT(val, 47, 5) 3245 #define VXGE_HW_MRPCIM_GENERAL_CFG2_EN_BLOCK_MSIX_DUE_TO_SERR vxge_mBIT(55) 3246 #define VXGE_HW_MRPCIM_GENERAL_CFG2_FORCE_SENDING_INTA vxge_mBIT(59) 3247 #define VXGE_HW_MRPCIM_GENERAL_CFG2_DIS_SWIF_PROT_ON_RDS vxge_mBIT(63) 3248 /*0x07510*/ u64 mrpcim_general_cfg3; 3249 #define VXGE_HW_MRPCIM_GENERAL_CFG3_PROTECTION_CA_OR_UNSUPN vxge_mBIT(0) 3250 #define VXGE_HW_MRPCIM_GENERAL_CFG3_ILLEGAL_RD_CA_OR_UNSUPN vxge_mBIT(3) 3251 #define VXGE_HW_MRPCIM_GENERAL_CFG3_RD_BYTE_SWAPEN vxge_mBIT(7) 3252 #define VXGE_HW_MRPCIM_GENERAL_CFG3_RD_BIT_FLIPEN vxge_mBIT(11) 3253 #define VXGE_HW_MRPCIM_GENERAL_CFG3_WR_BYTE_SWAPEN vxge_mBIT(15) 3254 #define VXGE_HW_MRPCIM_GENERAL_CFG3_WR_BIT_FLIPEN vxge_mBIT(19) 3255 #define VXGE_HW_MRPCIM_GENERAL_CFG3_MR_MAX_MVFS(val) vxge_vBIT(val, 20, 16) 3256 #define VXGE_HW_MRPCIM_GENERAL_CFG3_MR_MVF_TBL_SIZE(val) \ 3257 vxge_vBIT(val, 36, 16) 3258 #define VXGE_HW_MRPCIM_GENERAL_CFG3_PF0_SW_RESET_EN vxge_mBIT(55) 3259 #define VXGE_HW_MRPCIM_GENERAL_CFG3_REG_MODIFIED_CFG(val) vxge_vBIT(val, 56, 2) 3260 #define VXGE_HW_MRPCIM_GENERAL_CFG3_CPL_ECC_ENABLE_N vxge_mBIT(59) 3261 #define VXGE_HW_MRPCIM_GENERAL_CFG3_BYPASS_DAISY_CHAIN vxge_mBIT(63) 3262 /*0x07518*/ u64 mrpcim_stats_start_host_addr; 3263 #define VXGE_HW_MRPCIM_STATS_START_HOST_ADDR_MRPCIM_STATS_START_HOST_ADDR(val)\ 3264 vxge_vBIT(val, 0, 57) 3265 3266 u8 unused07950[0x07950-0x07520]; 3267 3268 /*0x07950*/ u64 rdcrdtarb_cfg0; 3269 #define VXGE_HW_RDCRDTARB_CFG0_RDA_MAX_OUTSTANDING_RDS(val) \ 3270 vxge_vBIT(val, 18, 6) 3271 #define VXGE_HW_RDCRDTARB_CFG0_PDA_MAX_OUTSTANDING_RDS(val) \ 3272 vxge_vBIT(val, 26, 6) 3273 #define VXGE_HW_RDCRDTARB_CFG0_DBLGEN_MAX_OUTSTANDING_RDS(val) \ 3274 vxge_vBIT(val, 34, 6) 3275 #define VXGE_HW_RDCRDTARB_CFG0_WAIT_CNT(val) vxge_vBIT(val, 48, 4) 3276 #define VXGE_HW_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(val) vxge_vBIT(val, 54, 6) 3277 #define VXGE_HW_RDCRDTARB_CFG0_EN_XON vxge_mBIT(63) 3278 u8 unused07be8[0x07be8-0x07958]; 3279 3280 /*0x07be8*/ u64 bf_sw_reset; 3281 #define VXGE_HW_BF_SW_RESET_BF_SW_RESET(val) vxge_vBIT(val, 0, 8) 3282 /*0x07bf0*/ u64 sw_reset_status; 3283 #define VXGE_HW_SW_RESET_STATUS_RESET_CMPLT vxge_mBIT(7) 3284 #define VXGE_HW_SW_RESET_STATUS_INIT_CMPLT vxge_mBIT(15) 3285 u8 unused07d30[0x07d30-0x07bf8]; 3286 3287 /*0x07d30*/ u64 mrpcim_debug_stats0; 3288 #define VXGE_HW_MRPCIM_DEBUG_STATS0_INI_WR_DROP(val) vxge_vBIT(val, 0, 32) 3289 #define VXGE_HW_MRPCIM_DEBUG_STATS0_INI_RD_DROP(val) vxge_vBIT(val, 32, 32) 3290 /*0x07d38*/ u64 mrpcim_debug_stats1_vplane[17]; 3291 #define VXGE_HW_MRPCIM_DEBUG_STATS1_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(val) \ 3292 vxge_vBIT(val, 32, 32) 3293 /*0x07dc0*/ u64 mrpcim_debug_stats2_vplane[17]; 3294 #define VXGE_HW_MRPCIM_DEBUG_STATS2_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(val) \ 3295 vxge_vBIT(val, 32, 32) 3296 /*0x07e48*/ u64 mrpcim_debug_stats3_vplane[17]; 3297 #define VXGE_HW_MRPCIM_DEBUG_STATS3_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(val) \ 3298 vxge_vBIT(val, 32, 32) 3299 /*0x07ed0*/ u64 mrpcim_debug_stats4; 3300 #define VXGE_HW_MRPCIM_DEBUG_STATS4_INI_WR_VPIN_DROP(val) vxge_vBIT(val, 0, 32) 3301 #define VXGE_HW_MRPCIM_DEBUG_STATS4_INI_RD_VPIN_DROP(val) \ 3302 vxge_vBIT(val, 32, 32) 3303 /*0x07ed8*/ u64 genstats_count01; 3304 #define VXGE_HW_GENSTATS_COUNT01_GENSTATS_COUNT1(val) vxge_vBIT(val, 0, 32) 3305 #define VXGE_HW_GENSTATS_COUNT01_GENSTATS_COUNT0(val) vxge_vBIT(val, 32, 32) 3306 /*0x07ee0*/ u64 genstats_count23; 3307 #define VXGE_HW_GENSTATS_COUNT23_GENSTATS_COUNT3(val) vxge_vBIT(val, 0, 32) 3308 #define VXGE_HW_GENSTATS_COUNT23_GENSTATS_COUNT2(val) vxge_vBIT(val, 32, 32) 3309 /*0x07ee8*/ u64 genstats_count4; 3310 #define VXGE_HW_GENSTATS_COUNT4_GENSTATS_COUNT4(val) vxge_vBIT(val, 32, 32) 3311 /*0x07ef0*/ u64 genstats_count5; 3312 #define VXGE_HW_GENSTATS_COUNT5_GENSTATS_COUNT5(val) vxge_vBIT(val, 32, 32) 3313 3314 u8 unused07f08[0x07f08-0x07ef8]; 3315 3316 /*0x07f08*/ u64 genstats_cfg[6]; 3317 #define VXGE_HW_GENSTATS_CFG_DTYPE_SEL(val) vxge_vBIT(val, 3, 5) 3318 #define VXGE_HW_GENSTATS_CFG_CLIENT_NO_SEL(val) vxge_vBIT(val, 9, 3) 3319 #define VXGE_HW_GENSTATS_CFG_WR_RD_CPL_SEL(val) vxge_vBIT(val, 14, 2) 3320 #define VXGE_HW_GENSTATS_CFG_VPATH_SEL(val) vxge_vBIT(val, 31, 17) 3321 /*0x07f38*/ u64 genstat_64bit_cfg; 3322 #define VXGE_HW_GENSTAT_64BIT_CFG_EN_FOR_GENSTATS0 vxge_mBIT(3) 3323 #define VXGE_HW_GENSTAT_64BIT_CFG_EN_FOR_GENSTATS2 vxge_mBIT(7) 3324 u8 unused08000[0x08000-0x07f40]; 3325 /*0x08000*/ u64 gcmg3_int_status; 3326 #define VXGE_HW_GCMG3_INT_STATUS_GSTC_ERR0_GSTC0_INT vxge_mBIT(0) 3327 #define VXGE_HW_GCMG3_INT_STATUS_GSTC_ERR1_GSTC1_INT vxge_mBIT(1) 3328 #define VXGE_HW_GCMG3_INT_STATUS_GH2L_ERR0_GH2L0_INT vxge_mBIT(2) 3329 #define VXGE_HW_GCMG3_INT_STATUS_GHSQ_ERR_GH2L1_INT vxge_mBIT(3) 3330 #define VXGE_HW_GCMG3_INT_STATUS_GHSQ_ERR2_GH2L2_INT vxge_mBIT(4) 3331 #define VXGE_HW_GCMG3_INT_STATUS_GH2L_SMERR0_GH2L3_INT vxge_mBIT(5) 3332 #define VXGE_HW_GCMG3_INT_STATUS_GHSQ_ERR3_GH2L4_INT vxge_mBIT(6) 3333 /*0x08008*/ u64 gcmg3_int_mask; 3334 u8 unused09000[0x09000-0x8010]; 3335 3336 /*0x09000*/ u64 g3ifcmd_fb_int_status; 3337 #define VXGE_HW_G3IFCMD_FB_INT_STATUS_ERR_G3IF_INT vxge_mBIT(0) 3338 /*0x09008*/ u64 g3ifcmd_fb_int_mask; 3339 /*0x09010*/ u64 g3ifcmd_fb_err_reg; 3340 #define VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_CK_DLL_LOCK vxge_mBIT(6) 3341 #define VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_SM_ERR vxge_mBIT(7) 3342 #define VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) \ 3343 vxge_vBIT(val, 24, 8) 3344 #define VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_IOCAL_FAULT vxge_mBIT(55) 3345 /*0x09018*/ u64 g3ifcmd_fb_err_mask; 3346 /*0x09020*/ u64 g3ifcmd_fb_err_alarm; 3347 3348 u8 unused09400[0x09400-0x09028]; 3349 3350 /*0x09400*/ u64 g3ifcmd_cmu_int_status; 3351 #define VXGE_HW_G3IFCMD_CMU_INT_STATUS_ERR_G3IF_INT vxge_mBIT(0) 3352 /*0x09408*/ u64 g3ifcmd_cmu_int_mask; 3353 /*0x09410*/ u64 g3ifcmd_cmu_err_reg; 3354 #define VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_CK_DLL_LOCK vxge_mBIT(6) 3355 #define VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_SM_ERR vxge_mBIT(7) 3356 #define VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) \ 3357 vxge_vBIT(val, 24, 8) 3358 #define VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_IOCAL_FAULT vxge_mBIT(55) 3359 /*0x09418*/ u64 g3ifcmd_cmu_err_mask; 3360 /*0x09420*/ u64 g3ifcmd_cmu_err_alarm; 3361 3362 u8 unused09800[0x09800-0x09428]; 3363 3364 /*0x09800*/ u64 g3ifcmd_cml_int_status; 3365 #define VXGE_HW_G3IFCMD_CML_INT_STATUS_ERR_G3IF_INT vxge_mBIT(0) 3366 /*0x09808*/ u64 g3ifcmd_cml_int_mask; 3367 /*0x09810*/ u64 g3ifcmd_cml_err_reg; 3368 #define VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_CK_DLL_LOCK vxge_mBIT(6) 3369 #define VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_SM_ERR vxge_mBIT(7) 3370 #define VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) \ 3371 vxge_vBIT(val, 24, 8) 3372 #define VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_IOCAL_FAULT vxge_mBIT(55) 3373 /*0x09818*/ u64 g3ifcmd_cml_err_mask; 3374 /*0x09820*/ u64 g3ifcmd_cml_err_alarm; 3375 u8 unused09b00[0x09b00-0x09828]; 3376 3377 /*0x09b00*/ u64 vpath_to_vplane_map[17]; 3378 #define VXGE_HW_VPATH_TO_VPLANE_MAP_VPATH_TO_VPLANE_MAP(val) \ 3379 vxge_vBIT(val, 3, 5) 3380 u8 unused09c30[0x09c30-0x09b88]; 3381 3382 /*0x09c30*/ u64 xgxs_cfg_port[2]; 3383 #define VXGE_HW_XGXS_CFG_PORT_SIG_DETECT_FORCE_LOS(val) vxge_vBIT(val, 16, 4) 3384 #define VXGE_HW_XGXS_CFG_PORT_SIG_DETECT_FORCE_VALID(val) vxge_vBIT(val, 20, 4) 3385 #define VXGE_HW_XGXS_CFG_PORT_SEL_INFO_0 vxge_mBIT(27) 3386 #define VXGE_HW_XGXS_CFG_PORT_SEL_INFO_1(val) vxge_vBIT(val, 29, 3) 3387 #define VXGE_HW_XGXS_CFG_PORT_TX_LANE0_SKEW(val) vxge_vBIT(val, 32, 4) 3388 #define VXGE_HW_XGXS_CFG_PORT_TX_LANE1_SKEW(val) vxge_vBIT(val, 36, 4) 3389 #define VXGE_HW_XGXS_CFG_PORT_TX_LANE2_SKEW(val) vxge_vBIT(val, 40, 4) 3390 #define VXGE_HW_XGXS_CFG_PORT_TX_LANE3_SKEW(val) vxge_vBIT(val, 44, 4) 3391 /*0x09c40*/ u64 xgxs_rxber_cfg_port[2]; 3392 #define VXGE_HW_XGXS_RXBER_CFG_PORT_INTERVAL_DUR(val) vxge_vBIT(val, 0, 4) 3393 #define VXGE_HW_XGXS_RXBER_CFG_PORT_RXGXS_INTERVAL_CNT(val) \ 3394 vxge_vBIT(val, 16, 48) 3395 /*0x09c50*/ u64 xgxs_rxber_status_port[2]; 3396 #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_A_ERR_CNT(val) \ 3397 vxge_vBIT(val, 0, 16) 3398 #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_B_ERR_CNT(val) \ 3399 vxge_vBIT(val, 16, 16) 3400 #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_C_ERR_CNT(val) \ 3401 vxge_vBIT(val, 32, 16) 3402 #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_D_ERR_CNT(val) \ 3403 vxge_vBIT(val, 48, 16) 3404 /*0x09c60*/ u64 xgxs_status_port[2]; 3405 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_TX_ACTIVITY(val) vxge_vBIT(val, 0, 4) 3406 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_RX_ACTIVITY(val) vxge_vBIT(val, 4, 4) 3407 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_CTC_FIFO_ERR BIT(11) 3408 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_BYTE_SYNC_LOST(val) \ 3409 vxge_vBIT(val, 12, 4) 3410 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_CTC_ERR(val) vxge_vBIT(val, 16, 4) 3411 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_ALIGNMENT_ERR vxge_mBIT(23) 3412 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_DEC_ERR(val) vxge_vBIT(val, 24, 8) 3413 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_INS_REQ(val) \ 3414 vxge_vBIT(val, 32, 4) 3415 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_DEL_REQ(val) \ 3416 vxge_vBIT(val, 36, 4) 3417 /*0x09c70*/ u64 xgxs_pma_reset_port[2]; 3418 #define VXGE_HW_XGXS_PMA_RESET_PORT_SERDES_RESET(val) vxge_vBIT(val, 0, 8) 3419 u8 unused09c90[0x09c90-0x09c80]; 3420 3421 /*0x09c90*/ u64 xgxs_static_cfg_port[2]; 3422 #define VXGE_HW_XGXS_STATIC_CFG_PORT_FW_CTRL_SERDES vxge_mBIT(3) 3423 u8 unused09d40[0x09d40-0x09ca0]; 3424 3425 /*0x09d40*/ u64 xgxs_info_port[2]; 3426 #define VXGE_HW_XGXS_INFO_PORT_XMACJ_INFO_0(val) vxge_vBIT(val, 0, 32) 3427 #define VXGE_HW_XGXS_INFO_PORT_XMACJ_INFO_1(val) vxge_vBIT(val, 32, 32) 3428 /*0x09d50*/ u64 ratemgmt_cfg_port[2]; 3429 #define VXGE_HW_RATEMGMT_CFG_PORT_MODE(val) vxge_vBIT(val, 2, 2) 3430 #define VXGE_HW_RATEMGMT_CFG_PORT_RATE vxge_mBIT(7) 3431 #define VXGE_HW_RATEMGMT_CFG_PORT_FIXED_USE_FSM vxge_mBIT(11) 3432 #define VXGE_HW_RATEMGMT_CFG_PORT_ANTP_USE_FSM vxge_mBIT(15) 3433 #define VXGE_HW_RATEMGMT_CFG_PORT_ANBE_USE_FSM vxge_mBIT(19) 3434 /*0x09d60*/ u64 ratemgmt_status_port[2]; 3435 #define VXGE_HW_RATEMGMT_STATUS_PORT_RATEMGMT_COMPLETE vxge_mBIT(3) 3436 #define VXGE_HW_RATEMGMT_STATUS_PORT_RATEMGMT_RATE vxge_mBIT(7) 3437 #define VXGE_HW_RATEMGMT_STATUS_PORT_RATEMGMT_MAC_MATCHES_PHY vxge_mBIT(11) 3438 u8 unused09d80[0x09d80-0x09d70]; 3439 3440 /*0x09d80*/ u64 ratemgmt_fixed_cfg_port[2]; 3441 #define VXGE_HW_RATEMGMT_FIXED_CFG_PORT_RESTART vxge_mBIT(7) 3442 /*0x09d90*/ u64 ratemgmt_antp_cfg_port[2]; 3443 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_RESTART vxge_mBIT(7) 3444 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_USE_PREAMBLE_EXT_PHY vxge_mBIT(11) 3445 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_USE_ACT_SEL vxge_mBIT(15) 3446 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_RETRY_PHY_QUERY(val) \ 3447 vxge_vBIT(val, 16, 4) 3448 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_WAIT_MDIO_RESPONSE(val) \ 3449 vxge_vBIT(val, 20, 4) 3450 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_LDOWN_REAUTO_RESPONSE(val) \ 3451 vxge_vBIT(val, 24, 4) 3452 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_ADVERTISE_10G vxge_mBIT(31) 3453 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_ADVERTISE_1G vxge_mBIT(35) 3454 /*0x09da0*/ u64 ratemgmt_anbe_cfg_port[2]; 3455 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_RESTART vxge_mBIT(7) 3456 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_PARALLEL_DETECT_10G_KX4_ENABLE \ 3457 vxge_mBIT(11) 3458 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_PARALLEL_DETECT_1G_KX_ENABLE \ 3459 vxge_mBIT(15) 3460 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_SYNC_10G_KX4(val) vxge_vBIT(val, 16, 4) 3461 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_SYNC_1G_KX(val) vxge_vBIT(val, 20, 4) 3462 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_DME_EXCHANGE(val) vxge_vBIT(val, 24, 4) 3463 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_ADVERTISE_10G_KX4 vxge_mBIT(31) 3464 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_ADVERTISE_1G_KX vxge_mBIT(35) 3465 /*0x09db0*/ u64 anbe_cfg_port[2]; 3466 #define VXGE_HW_ANBE_CFG_PORT_RESET_CFG_REGS(val) vxge_vBIT(val, 0, 8) 3467 #define VXGE_HW_ANBE_CFG_PORT_ALIGN_10G_KX4_OVERRIDE(val) vxge_vBIT(val, 10, 2) 3468 #define VXGE_HW_ANBE_CFG_PORT_SYNC_1G_KX_OVERRIDE(val) vxge_vBIT(val, 14, 2) 3469 /*0x09dc0*/ u64 anbe_mgr_ctrl_port[2]; 3470 #define VXGE_HW_ANBE_MGR_CTRL_PORT_WE vxge_mBIT(3) 3471 #define VXGE_HW_ANBE_MGR_CTRL_PORT_STROBE vxge_mBIT(7) 3472 #define VXGE_HW_ANBE_MGR_CTRL_PORT_ADDR(val) vxge_vBIT(val, 15, 9) 3473 #define VXGE_HW_ANBE_MGR_CTRL_PORT_DATA(val) vxge_vBIT(val, 32, 32) 3474 u8 unused09de0[0x09de0-0x09dd0]; 3475 3476 /*0x09de0*/ u64 anbe_fw_mstr_port[2]; 3477 #define VXGE_HW_ANBE_FW_MSTR_PORT_CONNECT_BEAN_TO_SERDES vxge_mBIT(3) 3478 #define VXGE_HW_ANBE_FW_MSTR_PORT_TX_ZEROES_TO_SERDES vxge_mBIT(7) 3479 /*0x09df0*/ u64 anbe_hwfsm_gen_status_port[2]; 3480 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G_KX4_USING_PD \ 3481 vxge_mBIT(3) 3482 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G_KX4_USING_DME \ 3483 vxge_mBIT(7) 3484 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G_KX_USING_PD \ 3485 vxge_mBIT(11) 3486 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G_KX_USING_DME \ 3487 vxge_mBIT(15) 3488 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANBEFSM_STATE(val) \ 3489 vxge_vBIT(val, 18, 6) 3490 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_NEXT_PAGE_RECEIVED \ 3491 vxge_mBIT(27) 3492 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_BASE_PAGE_RECEIVED \ 3493 vxge_mBIT(35) 3494 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_AUTONEG_COMPLETE \ 3495 vxge_mBIT(39) 3496 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NP_BEFORE_BP \ 3497 vxge_mBIT(43) 3498 #define \ 3499 VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_AN_COMPLETE_BEFORE_BP \ 3500 vxge_mBIT(47) 3501 #define \ 3502 VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_AN_COMPLETE_BEFORE_NP \ 3503 vxge_mBIT(51) 3504 #define \ 3505 VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_MODE_WHEN_AN_COMPLETE \ 3506 vxge_mBIT(55) 3507 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_BP(val) \ 3508 vxge_vBIT(val, 56, 4) 3509 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_NP(val) \ 3510 vxge_vBIT(val, 60, 4) 3511 /*0x09e00*/ u64 anbe_hwfsm_bp_status_port[2]; 3512 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_FEC_ENABLE \ 3513 vxge_mBIT(32) 3514 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_FEC_ABILITY \ 3515 vxge_mBIT(33) 3516 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_10G_KR_CAPABLE \ 3517 vxge_mBIT(40) 3518 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_10G_KX4_CAPABLE \ 3519 vxge_mBIT(41) 3520 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_1G_KX_CAPABLE \ 3521 vxge_mBIT(42) 3522 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_TX_NONCE(val) \ 3523 vxge_vBIT(val, 43, 5) 3524 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_NP vxge_mBIT(48) 3525 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ACK vxge_mBIT(49) 3526 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_REMOTE_FAULT \ 3527 vxge_mBIT(50) 3528 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ASM_DIR vxge_mBIT(51) 3529 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_PAUSE vxge_mBIT(53) 3530 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ECHOED_NONCE(val) \ 3531 vxge_vBIT(val, 54, 5) 3532 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val) \ 3533 vxge_vBIT(val, 59, 5) 3534 /*0x09e10*/ u64 anbe_hwfsm_np_status_port[2]; 3535 #define VXGE_HW_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_47_TO_32(val) \ 3536 vxge_vBIT(val, 16, 16) 3537 #define VXGE_HW_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_31_TO_0(val) \ 3538 vxge_vBIT(val, 32, 32) 3539 u8 unused09e30[0x09e30-0x09e20]; 3540 3541 /*0x09e30*/ u64 antp_gen_cfg_port[2]; 3542 /*0x09e40*/ u64 antp_hwfsm_gen_status_port[2]; 3543 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G vxge_mBIT(3) 3544 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G vxge_mBIT(7) 3545 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANTPFSM_STATE(val) \ 3546 vxge_vBIT(val, 10, 6) 3547 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_AUTONEG_COMPLETE \ 3548 vxge_mBIT(23) 3549 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NO_LP_XNP \ 3550 vxge_mBIT(27) 3551 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_GOT_LP_XNP vxge_mBIT(31) 3552 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_MESSAGE_CODE \ 3553 vxge_mBIT(35) 3554 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NO_HCD \ 3555 vxge_mBIT(43) 3556 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_FOUND_HCD vxge_mBIT(47) 3557 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_INVALID_RATE \ 3558 vxge_mBIT(51) 3559 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_VALID_RATE vxge_mBIT(55) 3560 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_PERSISTENT_LDOWN \ 3561 vxge_mBIT(59) 3562 /*0x09e50*/ u64 antp_hwfsm_bp_status_port[2]; 3563 #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_NP vxge_mBIT(0) 3564 #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ACK vxge_mBIT(1) 3565 #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_RF vxge_mBIT(2) 3566 #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_XNP vxge_mBIT(3) 3567 #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ABILITY_FIELD(val) \ 3568 vxge_vBIT(val, 4, 7) 3569 #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val) \ 3570 vxge_vBIT(val, 11, 5) 3571 /*0x09e60*/ u64 antp_hwfsm_xnp_status_port[2]; 3572 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_NP vxge_mBIT(0) 3573 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_ACK vxge_mBIT(1) 3574 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MP vxge_mBIT(2) 3575 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_ACK2 vxge_mBIT(3) 3576 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_TOGGLE vxge_mBIT(4) 3577 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MESSAGE_CODE(val) \ 3578 vxge_vBIT(val, 5, 11) 3579 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD1(val) \ 3580 vxge_vBIT(val, 16, 16) 3581 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD2(val) \ 3582 vxge_vBIT(val, 32, 16) 3583 /*0x09e70*/ u64 mdio_mgr_access_port[2]; 3584 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_STROBE_ONE BIT(3) 3585 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_OP_TYPE(val) vxge_vBIT(val, 5, 3) 3586 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_DEVAD(val) vxge_vBIT(val, 11, 5) 3587 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_ADDR(val) vxge_vBIT(val, 16, 16) 3588 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_DATA(val) vxge_vBIT(val, 32, 16) 3589 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_ST_PATTERN(val) vxge_vBIT(val, 49, 2) 3590 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_PREAMBLE vxge_mBIT(51) 3591 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_PRTAD(val) vxge_vBIT(val, 55, 5) 3592 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_STROBE_TWO vxge_mBIT(63) 3593 u8 unused0a200[0x0a200-0x09e80]; 3594 /*0x0a200*/ u64 xmac_vsport_choices_vh[17]; 3595 #define VXGE_HW_XMAC_VSPORT_CHOICES_VH_VSPORT_VECTOR(val) vxge_vBIT(val, 0, 17) 3596 u8 unused0a400[0x0a400-0x0a288]; 3597 3598 /*0x0a400*/ u64 rx_thresh_cfg_vp[17]; 3599 #define VXGE_HW_RX_THRESH_CFG_VP_PAUSE_LOW_THR(val) vxge_vBIT(val, 0, 8) 3600 #define VXGE_HW_RX_THRESH_CFG_VP_PAUSE_HIGH_THR(val) vxge_vBIT(val, 8, 8) 3601 #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_0(val) vxge_vBIT(val, 16, 8) 3602 #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_1(val) vxge_vBIT(val, 24, 8) 3603 #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_2(val) vxge_vBIT(val, 32, 8) 3604 #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_3(val) vxge_vBIT(val, 40, 8) 3605 u8 unused0ac90[0x0ac90-0x0a488]; 3606 } __packed; 3607 3608 /*VXGE_HW_SRPCIM_REGS_H*/ 3609 struct vxge_hw_srpcim_reg { 3610 3611 /*0x00000*/ u64 tim_mr2sr_resource_assignment_vh; 3612 #define VXGE_HW_TIM_MR2SR_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val) \ 3613 vxge_vBIT(val, 0, 32) 3614 u8 unused00100[0x00100-0x00008]; 3615 3616 /*0x00100*/ u64 srpcim_pcipif_int_status; 3617 #define VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_MRPCIM_MSG_MRPCIM_MSG_INT BIT(3) 3618 #define VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_VPATH_MSG_VPATH_MSG_INT BIT(7) 3619 #define VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_SRPCIM_SPARE_R1_SRPCIM_SPARE_R1_INT \ 3620 BIT(11) 3621 /*0x00108*/ u64 srpcim_pcipif_int_mask; 3622 /*0x00110*/ u64 mrpcim_msg_reg; 3623 #define VXGE_HW_MRPCIM_MSG_REG_SWIF_MRPCIM_TO_SRPCIM_RMSG_INT BIT(3) 3624 /*0x00118*/ u64 mrpcim_msg_mask; 3625 /*0x00120*/ u64 mrpcim_msg_alarm; 3626 /*0x00128*/ u64 vpath_msg_reg; 3627 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH0_TO_SRPCIM_RMSG_INT BIT(0) 3628 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH1_TO_SRPCIM_RMSG_INT BIT(1) 3629 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH2_TO_SRPCIM_RMSG_INT BIT(2) 3630 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH3_TO_SRPCIM_RMSG_INT BIT(3) 3631 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH4_TO_SRPCIM_RMSG_INT BIT(4) 3632 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH5_TO_SRPCIM_RMSG_INT BIT(5) 3633 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH6_TO_SRPCIM_RMSG_INT BIT(6) 3634 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH7_TO_SRPCIM_RMSG_INT BIT(7) 3635 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH8_TO_SRPCIM_RMSG_INT BIT(8) 3636 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH9_TO_SRPCIM_RMSG_INT BIT(9) 3637 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH10_TO_SRPCIM_RMSG_INT BIT(10) 3638 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH11_TO_SRPCIM_RMSG_INT BIT(11) 3639 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH12_TO_SRPCIM_RMSG_INT BIT(12) 3640 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH13_TO_SRPCIM_RMSG_INT BIT(13) 3641 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH14_TO_SRPCIM_RMSG_INT BIT(14) 3642 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH15_TO_SRPCIM_RMSG_INT BIT(15) 3643 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH16_TO_SRPCIM_RMSG_INT BIT(16) 3644 /*0x00130*/ u64 vpath_msg_mask; 3645 /*0x00138*/ u64 vpath_msg_alarm; 3646 u8 unused00160[0x00160-0x00140]; 3647 3648 /*0x00160*/ u64 srpcim_to_mrpcim_wmsg; 3649 #define VXGE_HW_SRPCIM_TO_MRPCIM_WMSG_SRPCIM_TO_MRPCIM_WMSG(val) \ 3650 vxge_vBIT(val, 0, 64) 3651 /*0x00168*/ u64 srpcim_to_mrpcim_wmsg_trig; 3652 #define VXGE_HW_SRPCIM_TO_MRPCIM_WMSG_TRIG_SRPCIM_TO_MRPCIM_WMSG_TRIG BIT(0) 3653 /*0x00170*/ u64 mrpcim_to_srpcim_rmsg; 3654 #define VXGE_HW_MRPCIM_TO_SRPCIM_RMSG_SWIF_MRPCIM_TO_SRPCIM_RMSG(val) \ 3655 vxge_vBIT(val, 0, 64) 3656 /*0x00178*/ u64 vpath_to_srpcim_rmsg_sel; 3657 #define VXGE_HW_VPATH_TO_SRPCIM_RMSG_SEL_VPATH_TO_SRPCIM_RMSG_SEL(val) \ 3658 vxge_vBIT(val, 0, 5) 3659 /*0x00180*/ u64 vpath_to_srpcim_rmsg; 3660 #define VXGE_HW_VPATH_TO_SRPCIM_RMSG_SWIF_VPATH_TO_SRPCIM_RMSG(val) \ 3661 vxge_vBIT(val, 0, 64) 3662 u8 unused00200[0x00200-0x00188]; 3663 3664 /*0x00200*/ u64 srpcim_general_int_status; 3665 #define VXGE_HW_SRPCIM_GENERAL_INT_STATUS_PIC_INT BIT(0) 3666 #define VXGE_HW_SRPCIM_GENERAL_INT_STATUS_PCI_INT BIT(3) 3667 #define VXGE_HW_SRPCIM_GENERAL_INT_STATUS_XMAC_INT BIT(7) 3668 u8 unused00210[0x00210-0x00208]; 3669 3670 /*0x00210*/ u64 srpcim_general_int_mask; 3671 #define VXGE_HW_SRPCIM_GENERAL_INT_MASK_PIC_INT BIT(0) 3672 #define VXGE_HW_SRPCIM_GENERAL_INT_MASK_PCI_INT BIT(3) 3673 #define VXGE_HW_SRPCIM_GENERAL_INT_MASK_XMAC_INT BIT(7) 3674 u8 unused00220[0x00220-0x00218]; 3675 3676 /*0x00220*/ u64 srpcim_ppif_int_status; 3677 3678 /*0x00228*/ u64 srpcim_ppif_int_mask; 3679 /*0x00230*/ u64 srpcim_gen_errors_reg; 3680 #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_STATUS_ERR BIT(3) 3681 #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_UNCOR_ERR BIT(7) 3682 #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_COR_ERR BIT(11) 3683 #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_INTCTRL_SCHED_INT BIT(15) 3684 #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_INI_SERR_DET BIT(19) 3685 #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_TGT_PF_ILLEGAL_ACCESS BIT(23) 3686 /*0x00238*/ u64 srpcim_gen_errors_mask; 3687 /*0x00240*/ u64 srpcim_gen_errors_alarm; 3688 /*0x00248*/ u64 mrpcim_to_srpcim_alarm_reg; 3689 #define VXGE_HW_MRPCIM_TO_SRPCIM_ALARM_REG_PPIF_MRPCIM_TO_SRPCIM_ALARM BIT(3) 3690 /*0x00250*/ u64 mrpcim_to_srpcim_alarm_mask; 3691 /*0x00258*/ u64 mrpcim_to_srpcim_alarm_alarm; 3692 /*0x00260*/ u64 vpath_to_srpcim_alarm_reg; 3693 3694 /*0x00268*/ u64 vpath_to_srpcim_alarm_mask; 3695 /*0x00270*/ u64 vpath_to_srpcim_alarm_alarm; 3696 u8 unused00280[0x00280-0x00278]; 3697 3698 /*0x00280*/ u64 pf_sw_reset; 3699 #define VXGE_HW_PF_SW_RESET_PF_SW_RESET(val) vxge_vBIT(val, 0, 8) 3700 /*0x00288*/ u64 srpcim_general_cfg1; 3701 #define VXGE_HW_SRPCIM_GENERAL_CFG1_BOOT_BYTE_SWAPEN BIT(19) 3702 #define VXGE_HW_SRPCIM_GENERAL_CFG1_BOOT_BIT_FLIPEN BIT(23) 3703 #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_ADDR_SWAPEN BIT(27) 3704 #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_ADDR_FLIPEN BIT(31) 3705 #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_DATA_SWAPEN BIT(35) 3706 #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_DATA_FLIPEN BIT(39) 3707 /*0x00290*/ u64 srpcim_interrupt_cfg1; 3708 #define VXGE_HW_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG(val) vxge_vBIT(val, 1, 7) 3709 #define VXGE_HW_SRPCIM_INTERRUPT_CFG1_TRAFFIC_CLASS(val) vxge_vBIT(val, 9, 3) 3710 u8 unused002a8[0x002a8-0x00298]; 3711 3712 /*0x002a8*/ u64 srpcim_clear_msix_mask; 3713 #define VXGE_HW_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK BIT(0) 3714 /*0x002b0*/ u64 srpcim_set_msix_mask; 3715 #define VXGE_HW_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK BIT(0) 3716 /*0x002b8*/ u64 srpcim_clr_msix_one_shot; 3717 #define VXGE_HW_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT BIT(0) 3718 /*0x002c0*/ u64 srpcim_rst_in_prog; 3719 #define VXGE_HW_SRPCIM_RST_IN_PROG_SRPCIM_RST_IN_PROG BIT(7) 3720 /*0x002c8*/ u64 srpcim_reg_modified; 3721 #define VXGE_HW_SRPCIM_REG_MODIFIED_SRPCIM_REG_MODIFIED BIT(7) 3722 /*0x002d0*/ u64 tgt_pf_illegal_access; 3723 #define VXGE_HW_TGT_PF_ILLEGAL_ACCESS_SWIF_REGION(val) vxge_vBIT(val, 1, 7) 3724 /*0x002d8*/ u64 srpcim_msix_status; 3725 #define VXGE_HW_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_MASK BIT(3) 3726 #define VXGE_HW_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_PENDING_VECTOR BIT(7) 3727 u8 unused00880[0x00880-0x002e0]; 3728 3729 /*0x00880*/ u64 xgmac_sr_int_status; 3730 #define VXGE_HW_XGMAC_SR_INT_STATUS_ASIC_NTWK_SR_ERR_ASIC_NTWK_SR_INT BIT(3) 3731 /*0x00888*/ u64 xgmac_sr_int_mask; 3732 /*0x00890*/ u64 asic_ntwk_sr_err_reg; 3733 #define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT BIT(3) 3734 #define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK BIT(7) 3735 #define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT_OCCURRED \ 3736 BIT(11) 3737 #define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK_OCCURRED BIT(15) 3738 /*0x00898*/ u64 asic_ntwk_sr_err_mask; 3739 /*0x008a0*/ u64 asic_ntwk_sr_err_alarm; 3740 u8 unused008c0[0x008c0-0x008a8]; 3741 3742 /*0x008c0*/ u64 xmac_vsport_choices_sr_clone; 3743 #define VXGE_HW_XMAC_VSPORT_CHOICES_SR_CLONE_VSPORT_VECTOR(val) \ 3744 vxge_vBIT(val, 0, 17) 3745 u8 unused00900[0x00900-0x008c8]; 3746 3747 /*0x00900*/ u64 mr_rqa_top_prty_for_vh; 3748 #define VXGE_HW_MR_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val) \ 3749 vxge_vBIT(val, 59, 5) 3750 /*0x00908*/ u64 umq_vh_data_list_empty; 3751 #define VXGE_HW_UMQ_VH_DATA_LIST_EMPTY_ROCRC_UMQ_VH_DATA_LIST_EMPTY \ 3752 BIT(0) 3753 /*0x00910*/ u64 wde_cfg; 3754 #define VXGE_HW_WDE_CFG_NS0_FORCE_MWB_START BIT(0) 3755 #define VXGE_HW_WDE_CFG_NS0_FORCE_MWB_END BIT(1) 3756 #define VXGE_HW_WDE_CFG_NS0_FORCE_QB_START BIT(2) 3757 #define VXGE_HW_WDE_CFG_NS0_FORCE_QB_END BIT(3) 3758 #define VXGE_HW_WDE_CFG_NS0_FORCE_MPSB_START BIT(4) 3759 #define VXGE_HW_WDE_CFG_NS0_FORCE_MPSB_END BIT(5) 3760 #define VXGE_HW_WDE_CFG_NS0_MWB_OPT_EN BIT(6) 3761 #define VXGE_HW_WDE_CFG_NS0_QB_OPT_EN BIT(7) 3762 #define VXGE_HW_WDE_CFG_NS0_MPSB_OPT_EN BIT(8) 3763 #define VXGE_HW_WDE_CFG_NS1_FORCE_MWB_START BIT(9) 3764 #define VXGE_HW_WDE_CFG_NS1_FORCE_MWB_END BIT(10) 3765 #define VXGE_HW_WDE_CFG_NS1_FORCE_QB_START BIT(11) 3766 #define VXGE_HW_WDE_CFG_NS1_FORCE_QB_END BIT(12) 3767 #define VXGE_HW_WDE_CFG_NS1_FORCE_MPSB_START BIT(13) 3768 #define VXGE_HW_WDE_CFG_NS1_FORCE_MPSB_END BIT(14) 3769 #define VXGE_HW_WDE_CFG_NS1_MWB_OPT_EN BIT(15) 3770 #define VXGE_HW_WDE_CFG_NS1_QB_OPT_EN BIT(16) 3771 #define VXGE_HW_WDE_CFG_NS1_MPSB_OPT_EN BIT(17) 3772 #define VXGE_HW_WDE_CFG_DISABLE_QPAD_FOR_UNALIGNED_ADDR BIT(19) 3773 #define VXGE_HW_WDE_CFG_ALIGNMENT_PREFERENCE(val) vxge_vBIT(val, 30, 2) 3774 #define VXGE_HW_WDE_CFG_MEM_WORD_SIZE(val) vxge_vBIT(val, 46, 2) 3775 3776 } __packed; 3777 3778 /*VXGE_HW_VPMGMT_REGS_H*/ 3779 struct vxge_hw_vpmgmt_reg { 3780 3781 u8 unused00040[0x00040-0x00000]; 3782 3783 /*0x00040*/ u64 vpath_to_func_map_cfg1; 3784 #define VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_VPATH_TO_FUNC_MAP_CFG1(val) \ 3785 vxge_vBIT(val, 3, 5) 3786 /*0x00048*/ u64 vpath_is_first; 3787 #define VXGE_HW_VPATH_IS_FIRST_VPATH_IS_FIRST vxge_mBIT(3) 3788 /*0x00050*/ u64 srpcim_to_vpath_wmsg; 3789 #define VXGE_HW_SRPCIM_TO_VPATH_WMSG_SRPCIM_TO_VPATH_WMSG(val) \ 3790 vxge_vBIT(val, 0, 64) 3791 /*0x00058*/ u64 srpcim_to_vpath_wmsg_trig; 3792 #define VXGE_HW_SRPCIM_TO_VPATH_WMSG_TRIG_SRPCIM_TO_VPATH_WMSG_TRIG \ 3793 vxge_mBIT(0) 3794 u8 unused00100[0x00100-0x00060]; 3795 3796 /*0x00100*/ u64 tim_vpath_assignment; 3797 #define VXGE_HW_TIM_VPATH_ASSIGNMENT_BMAP_ROOT(val) vxge_vBIT(val, 0, 32) 3798 u8 unused00140[0x00140-0x00108]; 3799 3800 /*0x00140*/ u64 rqa_top_prty_for_vp; 3801 #define VXGE_HW_RQA_TOP_PRTY_FOR_VP_RQA_TOP_PRTY_FOR_VP(val) \ 3802 vxge_vBIT(val, 59, 5) 3803 u8 unused001c0[0x001c0-0x00148]; 3804 3805 /*0x001c0*/ u64 rxmac_rx_pa_cfg0_vpmgmt_clone; 3806 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_IGNORE_FRAME_ERR vxge_mBIT(3) 3807 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SUPPORT_SNAP_AB_N vxge_mBIT(7) 3808 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SEARCH_FOR_HAO vxge_mBIT(18) 3809 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SUPPORT_MOBILE_IPV6_HDRS \ 3810 vxge_mBIT(19) 3811 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_IPV6_STOP_SEARCHING \ 3812 vxge_mBIT(23) 3813 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_NO_PS_IF_UNKNOWN vxge_mBIT(27) 3814 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SEARCH_FOR_ETYPE vxge_mBIT(35) 3815 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_L3_CSUM_ERR \ 3816 vxge_mBIT(39) 3817 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_L3_CSUM_ERR \ 3818 vxge_mBIT(43) 3819 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_L4_CSUM_ERR \ 3820 vxge_mBIT(47) 3821 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_L4_CSUM_ERR \ 3822 vxge_mBIT(51) 3823 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_RPA_ERR \ 3824 vxge_mBIT(55) 3825 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_RPA_ERR \ 3826 vxge_mBIT(59) 3827 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_JUMBO_SNAP_EN vxge_mBIT(63) 3828 /*0x001c8*/ u64 rts_mgr_cfg0_vpmgmt_clone; 3829 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_RTS_DP_SP_PRIORITY vxge_mBIT(3) 3830 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_FLEX_L4PRTCL_VALUE(val) \ 3831 vxge_vBIT(val, 24, 8) 3832 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_ICMP_TRASH vxge_mBIT(35) 3833 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_TCPSYN_TRASH vxge_mBIT(39) 3834 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_ZL4PYLD_TRASH vxge_mBIT(43) 3835 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_TCP_TRASH vxge_mBIT(47) 3836 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_UDP_TRASH vxge_mBIT(51) 3837 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_FLEX_TRASH vxge_mBIT(55) 3838 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_IPFRAG_TRASH vxge_mBIT(59) 3839 /*0x001d0*/ u64 rts_mgr_criteria_priority_vpmgmt_clone; 3840 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ETYPE(val) \ 3841 vxge_vBIT(val, 5, 3) 3842 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ICMP_TCPSYN(val) \ 3843 vxge_vBIT(val, 9, 3) 3844 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_L4PN(val) \ 3845 vxge_vBIT(val, 13, 3) 3846 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RANGE_L4PN(val) \ 3847 vxge_vBIT(val, 17, 3) 3848 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RTH_IT(val) \ 3849 vxge_vBIT(val, 21, 3) 3850 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_DS(val) \ 3851 vxge_vBIT(val, 25, 3) 3852 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_QOS(val) \ 3853 vxge_vBIT(val, 29, 3) 3854 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ZL4PYLD(val) \ 3855 vxge_vBIT(val, 33, 3) 3856 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_L4PRTCL(val) \ 3857 vxge_vBIT(val, 37, 3) 3858 /*0x001d8*/ u64 rxmac_cfg0_port_vpmgmt_clone[3]; 3859 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_RMAC_EN vxge_mBIT(3) 3860 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS vxge_mBIT(7) 3861 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_DISCARD_PFRM vxge_mBIT(11) 3862 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_FCS_ERR vxge_mBIT(15) 3863 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_LONG_ERR vxge_mBIT(19) 3864 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_USIZED_ERR vxge_mBIT(23) 3865 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_LEN_MISMATCH \ 3866 vxge_mBIT(27) 3867 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_MAX_PYLD_LEN(val) \ 3868 vxge_vBIT(val, 50, 14) 3869 /*0x001f0*/ u64 rxmac_pause_cfg_port_vpmgmt_clone[3]; 3870 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_GEN_EN vxge_mBIT(3) 3871 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_RCV_EN vxge_mBIT(7) 3872 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_ACCEL_SEND(val) \ 3873 vxge_vBIT(val, 9, 3) 3874 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_DUAL_THR vxge_mBIT(15) 3875 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_HIGH_PTIME(val) \ 3876 vxge_vBIT(val, 20, 16) 3877 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_IGNORE_PF_FCS_ERR \ 3878 vxge_mBIT(39) 3879 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_IGNORE_PF_LEN_ERR \ 3880 vxge_mBIT(43) 3881 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_LIMITER_EN vxge_mBIT(47) 3882 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_MAX_LIMIT(val) \ 3883 vxge_vBIT(val, 48, 8) 3884 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_PERMIT_RATEMGMT_CTRL \ 3885 vxge_mBIT(59) 3886 u8 unused00240[0x00240-0x00208]; 3887 3888 /*0x00240*/ u64 xmac_vsport_choices_vp; 3889 #define VXGE_HW_XMAC_VSPORT_CHOICES_VP_VSPORT_VECTOR(val) vxge_vBIT(val, 0, 17) 3890 u8 unused00260[0x00260-0x00248]; 3891 3892 /*0x00260*/ u64 xgmac_gen_status_vpmgmt_clone; 3893 #define VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK vxge_mBIT(3) 3894 #define VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_DATA_RATE \ 3895 vxge_mBIT(11) 3896 /*0x00268*/ u64 xgmac_status_port_vpmgmt_clone[2]; 3897 #define VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_RMAC_REMOTE_FAULT \ 3898 vxge_mBIT(3) 3899 #define VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_RMAC_LOCAL_FAULT vxge_mBIT(7) 3900 #define VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_XMACJ_MAC_PHY_LAYER_AVAIL \ 3901 vxge_mBIT(11) 3902 #define VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_XMACJ_PORT_OK vxge_mBIT(15) 3903 /*0x00278*/ u64 xmac_gen_cfg_vpmgmt_clone; 3904 #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_RATEMGMT_MAC_RATE_SEL(val) \ 3905 vxge_vBIT(val, 2, 2) 3906 #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_TX_HEAD_DROP_WHEN_FAULT \ 3907 vxge_mBIT(7) 3908 #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_FAULT_BEHAVIOUR vxge_mBIT(27) 3909 #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_UP(val) \ 3910 vxge_vBIT(val, 28, 4) 3911 #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_DOWN(val) \ 3912 vxge_vBIT(val, 32, 4) 3913 /*0x00280*/ u64 xmac_timestamp_vpmgmt_clone; 3914 #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_EN vxge_mBIT(3) 3915 #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_USE_LINK_ID(val) \ 3916 vxge_vBIT(val, 6, 2) 3917 #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_INTERVAL(val) vxge_vBIT(val, 12, 4) 3918 #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_TIMER_RESTART vxge_mBIT(19) 3919 #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_XMACJ_ROLLOVER_CNT(val) \ 3920 vxge_vBIT(val, 32, 16) 3921 /*0x00288*/ u64 xmac_stats_gen_cfg_vpmgmt_clone; 3922 #define VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_PRTAGGR_CUM_TIMER(val) \ 3923 vxge_vBIT(val, 4, 4) 3924 #define VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_VPATH_CUM_TIMER(val) \ 3925 vxge_vBIT(val, 8, 4) 3926 #define VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_VLAN_HANDLING vxge_mBIT(15) 3927 /*0x00290*/ u64 xmac_cfg_port_vpmgmt_clone[3]; 3928 #define VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_LOOPBACK vxge_mBIT(3) 3929 #define VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_REVERSE_LOOPBACK \ 3930 vxge_mBIT(7) 3931 #define VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_TX_BEHAV vxge_mBIT(11) 3932 #define VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_RX_BEHAV vxge_mBIT(15) 3933 u8 unused002c0[0x002c0-0x002a8]; 3934 3935 /*0x002c0*/ u64 txmac_gen_cfg0_vpmgmt_clone; 3936 #define VXGE_HW_TXMAC_GEN_CFG0_VPMGMT_CLONE_CHOSEN_TX_PORT vxge_mBIT(7) 3937 /*0x002c8*/ u64 txmac_cfg0_port_vpmgmt_clone[3]; 3938 #define VXGE_HW_TXMAC_CFG0_PORT_VPMGMT_CLONE_TMAC_EN vxge_mBIT(3) 3939 #define VXGE_HW_TXMAC_CFG0_PORT_VPMGMT_CLONE_APPEND_PAD vxge_mBIT(7) 3940 #define VXGE_HW_TXMAC_CFG0_PORT_VPMGMT_CLONE_PAD_BYTE(val) vxge_vBIT(val, 8, 8) 3941 u8 unused00300[0x00300-0x002e0]; 3942 3943 /*0x00300*/ u64 wol_mp_crc; 3944 #define VXGE_HW_WOL_MP_CRC_CRC(val) vxge_vBIT(val, 0, 32) 3945 #define VXGE_HW_WOL_MP_CRC_RC_EN vxge_mBIT(63) 3946 /*0x00308*/ u64 wol_mp_mask_a; 3947 #define VXGE_HW_WOL_MP_MASK_A_MASK(val) vxge_vBIT(val, 0, 64) 3948 /*0x00310*/ u64 wol_mp_mask_b; 3949 #define VXGE_HW_WOL_MP_MASK_B_MASK(val) vxge_vBIT(val, 0, 64) 3950 u8 unused00360[0x00360-0x00318]; 3951 3952 /*0x00360*/ u64 fau_pa_cfg_vpmgmt_clone; 3953 #define VXGE_HW_FAU_PA_CFG_VPMGMT_CLONE_REPL_L4_COMP_CSUM vxge_mBIT(3) 3954 #define VXGE_HW_FAU_PA_CFG_VPMGMT_CLONE_REPL_L3_INCL_CF vxge_mBIT(7) 3955 #define VXGE_HW_FAU_PA_CFG_VPMGMT_CLONE_REPL_L3_COMP_CSUM vxge_mBIT(11) 3956 /*0x00368*/ u64 rx_datapath_util_vp_clone; 3957 #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_UTILIZATION(val) \ 3958 vxge_vBIT(val, 7, 9) 3959 #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_RX_UTIL_CFG(val) \ 3960 vxge_vBIT(val, 16, 4) 3961 #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_FRAC_UTIL(val) \ 3962 vxge_vBIT(val, 20, 4) 3963 #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_RX_PKT_WEIGHT(val) \ 3964 vxge_vBIT(val, 24, 4) 3965 u8 unused00380[0x00380-0x00370]; 3966 3967 /*0x00380*/ u64 tx_datapath_util_vp_clone; 3968 #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_UTILIZATION(val) \ 3969 vxge_vBIT(val, 7, 9) 3970 #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TX_UTIL_CFG(val) \ 3971 vxge_vBIT(val, 16, 4) 3972 #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_FRAC_UTIL(val) \ 3973 vxge_vBIT(val, 20, 4) 3974 #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TX_PKT_WEIGHT(val) \ 3975 vxge_vBIT(val, 24, 4) 3976 3977 } __packed; 3978 3979 struct vxge_hw_vpath_reg { 3980 3981 u8 unused00300[0x00300]; 3982 3983 /*0x00300*/ u64 usdc_vpath; 3984 #define VXGE_HW_USDC_VPATH_SGRP_ASSIGN(val) vxge_vBIT(val, 0, 32) 3985 u8 unused00a00[0x00a00-0x00308]; 3986 3987 /*0x00a00*/ u64 wrdma_alarm_status; 3988 #define VXGE_HW_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT vxge_mBIT(1) 3989 /*0x00a08*/ u64 wrdma_alarm_mask; 3990 u8 unused00a30[0x00a30-0x00a10]; 3991 3992 /*0x00a30*/ u64 prc_alarm_reg; 3993 #define VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP vxge_mBIT(0) 3994 #define VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ERR vxge_mBIT(1) 3995 #define VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT vxge_mBIT(2) 3996 #define VXGE_HW_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR vxge_mBIT(3) 3997 /*0x00a38*/ u64 prc_alarm_mask; 3998 /*0x00a40*/ u64 prc_alarm_alarm; 3999 /*0x00a48*/ u64 prc_cfg1; 4000 #define VXGE_HW_PRC_CFG1_RX_TIMER_VAL(val) vxge_vBIT(val, 3, 29) 4001 #define VXGE_HW_PRC_CFG1_TIM_RING_BUMP_INT_ENABLE vxge_mBIT(34) 4002 #define VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE vxge_mBIT(35) 4003 #define VXGE_HW_PRC_CFG1_GREEDY_RETURN vxge_mBIT(36) 4004 #define VXGE_HW_PRC_CFG1_QUICK_SHOT vxge_mBIT(37) 4005 #define VXGE_HW_PRC_CFG1_RX_TIMER_CI vxge_mBIT(39) 4006 #define VXGE_HW_PRC_CFG1_RESET_TIMER_ON_RXD_RET(val) vxge_vBIT(val, 40, 2) 4007 u8 unused00a60[0x00a60-0x00a50]; 4008 4009 /*0x00a60*/ u64 prc_cfg4; 4010 #define VXGE_HW_PRC_CFG4_IN_SVC vxge_mBIT(7) 4011 #define VXGE_HW_PRC_CFG4_RING_MODE(val) vxge_vBIT(val, 14, 2) 4012 #define VXGE_HW_PRC_CFG4_RXD_NO_SNOOP vxge_mBIT(22) 4013 #define VXGE_HW_PRC_CFG4_FRM_NO_SNOOP vxge_mBIT(23) 4014 #define VXGE_HW_PRC_CFG4_RTH_DISABLE vxge_mBIT(31) 4015 #define VXGE_HW_PRC_CFG4_IGNORE_OWNERSHIP vxge_mBIT(32) 4016 #define VXGE_HW_PRC_CFG4_SIGNAL_BENIGN_OVFLW vxge_mBIT(36) 4017 #define VXGE_HW_PRC_CFG4_BIMODAL_INTERRUPT vxge_mBIT(37) 4018 #define VXGE_HW_PRC_CFG4_BACKOFF_INTERVAL(val) vxge_vBIT(val, 40, 24) 4019 /*0x00a68*/ u64 prc_cfg5; 4020 #define VXGE_HW_PRC_CFG5_RXD0_ADD(val) vxge_vBIT(val, 0, 61) 4021 /*0x00a70*/ u64 prc_cfg6; 4022 #define VXGE_HW_PRC_CFG6_FRM_PAD_EN vxge_mBIT(0) 4023 #define VXGE_HW_PRC_CFG6_QSIZE_ALIGNED_RXD vxge_mBIT(2) 4024 #define VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN vxge_mBIT(5) 4025 #define VXGE_HW_PRC_CFG6_L3_CPC_TRSFR_CODE_EN vxge_mBIT(8) 4026 #define VXGE_HW_PRC_CFG6_L4_CPC_TRSFR_CODE_EN vxge_mBIT(9) 4027 #define VXGE_HW_PRC_CFG6_RXD_CRXDT(val) vxge_vBIT(val, 23, 9) 4028 #define VXGE_HW_PRC_CFG6_RXD_SPAT(val) vxge_vBIT(val, 36, 9) 4029 #define VXGE_HW_PRC_CFG6_GET_RXD_SPAT(val) vxge_bVALn(val, 36, 9) 4030 /*0x00a78*/ u64 prc_cfg7; 4031 #define VXGE_HW_PRC_CFG7_SCATTER_MODE(val) vxge_vBIT(val, 6, 2) 4032 #define VXGE_HW_PRC_CFG7_SMART_SCAT_EN vxge_mBIT(11) 4033 #define VXGE_HW_PRC_CFG7_RXD_NS_CHG_EN vxge_mBIT(12) 4034 #define VXGE_HW_PRC_CFG7_NO_HDR_SEPARATION vxge_mBIT(14) 4035 #define VXGE_HW_PRC_CFG7_RXD_BUFF_SIZE_MASK(val) vxge_vBIT(val, 20, 4) 4036 #define VXGE_HW_PRC_CFG7_BUFF_SIZE0_MASK(val) vxge_vBIT(val, 27, 5) 4037 /*0x00a80*/ u64 tim_dest_addr; 4038 #define VXGE_HW_TIM_DEST_ADDR_TIM_DEST_ADDR(val) vxge_vBIT(val, 0, 64) 4039 /*0x00a88*/ u64 prc_rxd_doorbell; 4040 #define VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val) vxge_vBIT(val, 48, 16) 4041 /*0x00a90*/ u64 rqa_prty_for_vp; 4042 #define VXGE_HW_RQA_PRTY_FOR_VP_RQA_PRTY_FOR_VP(val) vxge_vBIT(val, 59, 5) 4043 /*0x00a98*/ u64 rxdmem_size; 4044 #define VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(val) vxge_vBIT(val, 51, 13) 4045 /*0x00aa0*/ u64 frm_in_progress_cnt; 4046 #define VXGE_HW_FRM_IN_PROGRESS_CNT_PRC_FRM_IN_PROGRESS_CNT(val) \ 4047 vxge_vBIT(val, 59, 5) 4048 /*0x00aa8*/ u64 rx_multi_cast_stats; 4049 #define VXGE_HW_RX_MULTI_CAST_STATS_FRAME_DISCARD(val) vxge_vBIT(val, 48, 16) 4050 /*0x00ab0*/ u64 rx_frm_transferred; 4051 #define VXGE_HW_RX_FRM_TRANSFERRED_RX_FRM_TRANSFERRED(val) \ 4052 vxge_vBIT(val, 32, 32) 4053 /*0x00ab8*/ u64 rxd_returned; 4054 #define VXGE_HW_RXD_RETURNED_RXD_RETURNED(val) vxge_vBIT(val, 48, 16) 4055 u8 unused00c00[0x00c00-0x00ac0]; 4056 4057 /*0x00c00*/ u64 kdfc_fifo_trpl_partition; 4058 #define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(val) vxge_vBIT(val, 17, 15) 4059 #define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_1(val) vxge_vBIT(val, 33, 15) 4060 #define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_2(val) vxge_vBIT(val, 49, 15) 4061 /*0x00c08*/ u64 kdfc_fifo_trpl_ctrl; 4062 #define VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE vxge_mBIT(7) 4063 /*0x00c10*/ u64 kdfc_trpl_fifo_0_ctrl; 4064 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(val) vxge_vBIT(val, 14, 2) 4065 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_FLIP_EN vxge_mBIT(22) 4066 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN vxge_mBIT(23) 4067 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_INT_CTRL(val) vxge_vBIT(val, 26, 2) 4068 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_CTRL_STRUC vxge_mBIT(28) 4069 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_ADD_PAD vxge_mBIT(29) 4070 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_NO_SNOOP vxge_mBIT(30) 4071 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_RLX_ORD vxge_mBIT(31) 4072 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(val) vxge_vBIT(val, 32, 8) 4073 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_INT_NO(val) vxge_vBIT(val, 41, 7) 4074 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_BIT_MAP(val) vxge_vBIT(val, 48, 16) 4075 /*0x00c18*/ u64 kdfc_trpl_fifo_1_ctrl; 4076 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE(val) vxge_vBIT(val, 14, 2) 4077 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_FLIP_EN vxge_mBIT(22) 4078 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_SWAP_EN vxge_mBIT(23) 4079 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_INT_CTRL(val) vxge_vBIT(val, 26, 2) 4080 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_CTRL_STRUC vxge_mBIT(28) 4081 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_ADD_PAD vxge_mBIT(29) 4082 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_NO_SNOOP vxge_mBIT(30) 4083 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_RLX_ORD vxge_mBIT(31) 4084 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_SELECT(val) vxge_vBIT(val, 32, 8) 4085 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_INT_NO(val) vxge_vBIT(val, 41, 7) 4086 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_BIT_MAP(val) vxge_vBIT(val, 48, 16) 4087 /*0x00c20*/ u64 kdfc_trpl_fifo_2_ctrl; 4088 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_FLIP_EN vxge_mBIT(22) 4089 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_SWAP_EN vxge_mBIT(23) 4090 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_INT_CTRL(val) vxge_vBIT(val, 26, 2) 4091 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_CTRL_STRUC vxge_mBIT(28) 4092 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_ADD_PAD vxge_mBIT(29) 4093 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_NO_SNOOP vxge_mBIT(30) 4094 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_RLX_ORD vxge_mBIT(31) 4095 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_SELECT(val) vxge_vBIT(val, 32, 8) 4096 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_INT_NO(val) vxge_vBIT(val, 41, 7) 4097 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_BIT_MAP(val) vxge_vBIT(val, 48, 16) 4098 /*0x00c28*/ u64 kdfc_trpl_fifo_0_wb_address; 4099 #define VXGE_HW_KDFC_TRPL_FIFO_0_WB_ADDRESS_ADD(val) vxge_vBIT(val, 0, 64) 4100 /*0x00c30*/ u64 kdfc_trpl_fifo_1_wb_address; 4101 #define VXGE_HW_KDFC_TRPL_FIFO_1_WB_ADDRESS_ADD(val) vxge_vBIT(val, 0, 64) 4102 /*0x00c38*/ u64 kdfc_trpl_fifo_2_wb_address; 4103 #define VXGE_HW_KDFC_TRPL_FIFO_2_WB_ADDRESS_ADD(val) vxge_vBIT(val, 0, 64) 4104 /*0x00c40*/ u64 kdfc_trpl_fifo_offset; 4105 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR0(val) vxge_vBIT(val, 1, 15) 4106 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR1(val) vxge_vBIT(val, 17, 15) 4107 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR2(val) vxge_vBIT(val, 33, 15) 4108 /*0x00c48*/ u64 kdfc_drbl_triplet_total; 4109 #define VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_KDFC_MAX_SIZE(val) \ 4110 vxge_vBIT(val, 17, 15) 4111 u8 unused00c60[0x00c60-0x00c50]; 4112 4113 /*0x00c60*/ u64 usdc_drbl_ctrl; 4114 #define VXGE_HW_USDC_DRBL_CTRL_FLIP_EN vxge_mBIT(22) 4115 #define VXGE_HW_USDC_DRBL_CTRL_SWAP_EN vxge_mBIT(23) 4116 /*0x00c68*/ u64 usdc_vp_ready; 4117 #define VXGE_HW_USDC_VP_READY_USDC_HTN_READY vxge_mBIT(7) 4118 #define VXGE_HW_USDC_VP_READY_USDC_SRQ_READY vxge_mBIT(15) 4119 #define VXGE_HW_USDC_VP_READY_USDC_CQRQ_READY vxge_mBIT(23) 4120 /*0x00c70*/ u64 kdfc_status; 4121 #define VXGE_HW_KDFC_STATUS_KDFC_WRR_0_READY vxge_mBIT(0) 4122 #define VXGE_HW_KDFC_STATUS_KDFC_WRR_1_READY vxge_mBIT(1) 4123 #define VXGE_HW_KDFC_STATUS_KDFC_WRR_2_READY vxge_mBIT(2) 4124 u8 unused00c80[0x00c80-0x00c78]; 4125 4126 /*0x00c80*/ u64 xmac_rpa_vcfg; 4127 #define VXGE_HW_XMAC_RPA_VCFG_IPV4_TCP_INCL_PH vxge_mBIT(3) 4128 #define VXGE_HW_XMAC_RPA_VCFG_IPV6_TCP_INCL_PH vxge_mBIT(7) 4129 #define VXGE_HW_XMAC_RPA_VCFG_IPV4_UDP_INCL_PH vxge_mBIT(11) 4130 #define VXGE_HW_XMAC_RPA_VCFG_IPV6_UDP_INCL_PH vxge_mBIT(15) 4131 #define VXGE_HW_XMAC_RPA_VCFG_L4_INCL_CF vxge_mBIT(19) 4132 #define VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG vxge_mBIT(23) 4133 /*0x00c88*/ u64 rxmac_vcfg0; 4134 #define VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(val) vxge_vBIT(val, 2, 14) 4135 #define VXGE_HW_RXMAC_VCFG0_RTS_USE_MIN_LEN vxge_mBIT(19) 4136 #define VXGE_HW_RXMAC_VCFG0_RTS_MIN_FRM_LEN(val) vxge_vBIT(val, 26, 14) 4137 #define VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN vxge_mBIT(43) 4138 #define VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN vxge_mBIT(47) 4139 #define VXGE_HW_RXMAC_VCFG0_BCAST_EN vxge_mBIT(51) 4140 #define VXGE_HW_RXMAC_VCFG0_ALL_VID_EN vxge_mBIT(55) 4141 /*0x00c90*/ u64 rxmac_vcfg1; 4142 #define VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(val) vxge_vBIT(val, 42, 2) 4143 #define VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE vxge_mBIT(47) 4144 #define VXGE_HW_RXMAC_VCFG1_CONTRIB_L2_FLOW vxge_mBIT(51) 4145 /*0x00c98*/ u64 rts_access_steer_ctrl; 4146 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(val) vxge_vBIT(val, 1, 7) 4147 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(val) vxge_vBIT(val, 8, 4) 4148 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE vxge_mBIT(15) 4149 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_BEHAV_TBL_SEL vxge_mBIT(23) 4150 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL vxge_mBIT(27) 4151 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS vxge_mBIT(0) 4152 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(val) vxge_vBIT(val, 40, 8) 4153 /*0x00ca0*/ u64 rts_access_steer_data0; 4154 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_DATA(val) vxge_vBIT(val, 0, 64) 4155 /*0x00ca8*/ u64 rts_access_steer_data1; 4156 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_DATA(val) vxge_vBIT(val, 0, 64) 4157 u8 unused00d00[0x00d00-0x00cb0]; 4158 4159 /*0x00d00*/ u64 xmac_vsport_choice; 4160 #define VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(val) vxge_vBIT(val, 3, 5) 4161 /*0x00d08*/ u64 xmac_stats_cfg; 4162 /*0x00d10*/ u64 xmac_stats_access_cmd; 4163 #define VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(val) vxge_vBIT(val, 6, 2) 4164 #define VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE vxge_mBIT(15) 4165 #define VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(val) vxge_vBIT(val, 32, 8) 4166 /*0x00d18*/ u64 xmac_stats_access_data; 4167 #define VXGE_HW_XMAC_STATS_ACCESS_DATA_XSMGR_DATA(val) vxge_vBIT(val, 0, 64) 4168 /*0x00d20*/ u64 asic_ntwk_vp_ctrl; 4169 #define VXGE_HW_ASIC_NTWK_VP_CTRL_REQ_TEST_NTWK vxge_mBIT(3) 4170 #define VXGE_HW_ASIC_NTWK_VP_CTRL_XMACJ_SHOW_PORT_INFO vxge_mBIT(55) 4171 #define VXGE_HW_ASIC_NTWK_VP_CTRL_XMACJ_PORT_NUM vxge_mBIT(63) 4172 u8 unused00d30[0x00d30-0x00d28]; 4173 4174 /*0x00d30*/ u64 xgmac_vp_int_status; 4175 #define VXGE_HW_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_ASIC_NTWK_VP_INT \ 4176 vxge_mBIT(3) 4177 /*0x00d38*/ u64 xgmac_vp_int_mask; 4178 /*0x00d40*/ u64 asic_ntwk_vp_err_reg; 4179 #define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT vxge_mBIT(3) 4180 #define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK vxge_mBIT(7) 4181 #define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR \ 4182 vxge_mBIT(11) 4183 #define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR \ 4184 vxge_mBIT(15) 4185 #define VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT \ 4186 vxge_mBIT(19) 4187 #define VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK vxge_mBIT(23) 4188 /*0x00d48*/ u64 asic_ntwk_vp_err_mask; 4189 /*0x00d50*/ u64 asic_ntwk_vp_err_alarm; 4190 u8 unused00d80[0x00d80-0x00d58]; 4191 4192 /*0x00d80*/ u64 rtdma_bw_ctrl; 4193 #define VXGE_HW_RTDMA_BW_CTRL_BW_CTRL_EN vxge_mBIT(39) 4194 #define VXGE_HW_RTDMA_BW_CTRL_DESIRED_BW(val) vxge_vBIT(val, 46, 18) 4195 /*0x00d88*/ u64 rtdma_rd_optimization_ctrl; 4196 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_GEN_INT_AFTER_ABORT vxge_mBIT(3) 4197 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_PAD_MODE(val) vxge_vBIT(val, 6, 2) 4198 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_PAD_PATTERN(val) vxge_vBIT(val, 8, 8) 4199 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE vxge_mBIT(19) 4200 #define VXGE_HW_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ 4201 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val) \ 4202 vxge_vBIT(val, 21, 3) 4203 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK_EN vxge_mBIT(28) 4204 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK(val) \ 4205 vxge_vBIT(val, 29, 3) 4206 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN vxge_mBIT(35) 4207 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(val) \ 4208 vxge_vBIT(val, 37, 3) 4209 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_WAIT_FOR_SPACE vxge_mBIT(43) 4210 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_FILL_THRESH(val) \ 4211 vxge_vBIT(val, 51, 5) 4212 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY_EN vxge_mBIT(59) 4213 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY(val) \ 4214 vxge_vBIT(val, 61, 3) 4215 /*0x00d90*/ u64 pda_pcc_job_monitor; 4216 #define VXGE_HW_PDA_PCC_JOB_MONITOR_PDA_PCC_JOB_STATUS vxge_mBIT(7) 4217 /*0x00d98*/ u64 tx_protocol_assist_cfg; 4218 #define VXGE_HW_TX_PROTOCOL_ASSIST_CFG_LSOV2_EN vxge_mBIT(6) 4219 #define VXGE_HW_TX_PROTOCOL_ASSIST_CFG_IPV6_KEEP_SEARCHING vxge_mBIT(7) 4220 u8 unused01000[0x01000-0x00da0]; 4221 4222 /*0x01000*/ u64 tim_cfg1_int_num[4]; 4223 #define VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(val) vxge_vBIT(val, 6, 26) 4224 #define VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN vxge_mBIT(35) 4225 #define VXGE_HW_TIM_CFG1_INT_NUM_TXFRM_CNT_EN vxge_mBIT(36) 4226 #define VXGE_HW_TIM_CFG1_INT_NUM_TXD_CNT_EN vxge_mBIT(37) 4227 #define VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC vxge_mBIT(38) 4228 #define VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI vxge_mBIT(39) 4229 #define VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(val) vxge_vBIT(val, 41, 7) 4230 #define VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(val) vxge_vBIT(val, 49, 7) 4231 #define VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(val) vxge_vBIT(val, 57, 7) 4232 /*0x01020*/ u64 tim_cfg2_int_num[4]; 4233 #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(val) vxge_vBIT(val, 0, 16) 4234 #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(val) vxge_vBIT(val, 16, 16) 4235 #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(val) vxge_vBIT(val, 32, 16) 4236 #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(val) vxge_vBIT(val, 48, 16) 4237 /*0x01040*/ u64 tim_cfg3_int_num[4]; 4238 #define VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI vxge_mBIT(0) 4239 #define VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(val) vxge_vBIT(val, 1, 4) 4240 #define VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(val) vxge_vBIT(val, 6, 26) 4241 #define VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(val) vxge_vBIT(val, 32, 6) 4242 #define VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(val) vxge_vBIT(val, 38, 26) 4243 /*0x01060*/ u64 tim_wrkld_clc; 4244 #define VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(val) vxge_vBIT(val, 0, 32) 4245 #define VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(val) vxge_vBIT(val, 35, 5) 4246 #define VXGE_HW_TIM_WRKLD_CLC_CNT_FRM_BYTE vxge_mBIT(40) 4247 #define VXGE_HW_TIM_WRKLD_CLC_CNT_RX_TX(val) vxge_vBIT(val, 41, 2) 4248 #define VXGE_HW_TIM_WRKLD_CLC_CNT_LNK_EN vxge_mBIT(43) 4249 #define VXGE_HW_TIM_WRKLD_CLC_HOST_UTIL(val) vxge_vBIT(val, 57, 7) 4250 /*0x01068*/ u64 tim_bitmap; 4251 #define VXGE_HW_TIM_BITMAP_MASK(val) vxge_vBIT(val, 0, 32) 4252 #define VXGE_HW_TIM_BITMAP_LLROOT_RXD_EN vxge_mBIT(32) 4253 #define VXGE_HW_TIM_BITMAP_LLROOT_TXD_EN vxge_mBIT(33) 4254 /*0x01070*/ u64 tim_ring_assn; 4255 #define VXGE_HW_TIM_RING_ASSN_INT_NUM(val) vxge_vBIT(val, 6, 2) 4256 /*0x01078*/ u64 tim_remap; 4257 #define VXGE_HW_TIM_REMAP_TX_EN vxge_mBIT(5) 4258 #define VXGE_HW_TIM_REMAP_RX_EN vxge_mBIT(6) 4259 #define VXGE_HW_TIM_REMAP_OFFLOAD_EN vxge_mBIT(7) 4260 #define VXGE_HW_TIM_REMAP_TO_VPATH_NUM(val) vxge_vBIT(val, 11, 5) 4261 /*0x01080*/ u64 tim_vpath_map; 4262 #define VXGE_HW_TIM_VPATH_MAP_BMAP_ROOT(val) vxge_vBIT(val, 0, 32) 4263 /*0x01088*/ u64 tim_pci_cfg; 4264 #define VXGE_HW_TIM_PCI_CFG_ADD_PAD vxge_mBIT(7) 4265 #define VXGE_HW_TIM_PCI_CFG_NO_SNOOP vxge_mBIT(15) 4266 #define VXGE_HW_TIM_PCI_CFG_RELAXED vxge_mBIT(23) 4267 #define VXGE_HW_TIM_PCI_CFG_CTL_STR vxge_mBIT(31) 4268 u8 unused01100[0x01100-0x01090]; 4269 4270 /*0x01100*/ u64 sgrp_assign; 4271 #define VXGE_HW_SGRP_ASSIGN_SGRP_ASSIGN(val) vxge_vBIT(val, 0, 64) 4272 /*0x01108*/ u64 sgrp_aoa_and_result; 4273 #define VXGE_HW_SGRP_AOA_AND_RESULT_PET_SGRP_AOA_AND_RESULT(val) \ 4274 vxge_vBIT(val, 0, 64) 4275 /*0x01110*/ u64 rpe_pci_cfg; 4276 #define VXGE_HW_RPE_PCI_CFG_PAD_LRO_DATA_ENABLE vxge_mBIT(7) 4277 #define VXGE_HW_RPE_PCI_CFG_PAD_LRO_HDR_ENABLE vxge_mBIT(8) 4278 #define VXGE_HW_RPE_PCI_CFG_PAD_LRO_CQE_ENABLE vxge_mBIT(9) 4279 #define VXGE_HW_RPE_PCI_CFG_PAD_NONLL_CQE_ENABLE vxge_mBIT(10) 4280 #define VXGE_HW_RPE_PCI_CFG_PAD_BASE_LL_CQE_ENABLE vxge_mBIT(11) 4281 #define VXGE_HW_RPE_PCI_CFG_PAD_LL_CQE_IDATA_ENABLE vxge_mBIT(12) 4282 #define VXGE_HW_RPE_PCI_CFG_PAD_CQRQ_IR_ENABLE vxge_mBIT(13) 4283 #define VXGE_HW_RPE_PCI_CFG_PAD_CQSQ_IR_ENABLE vxge_mBIT(14) 4284 #define VXGE_HW_RPE_PCI_CFG_PAD_CQRR_IR_ENABLE vxge_mBIT(15) 4285 #define VXGE_HW_RPE_PCI_CFG_NOSNOOP_DATA vxge_mBIT(18) 4286 #define VXGE_HW_RPE_PCI_CFG_NOSNOOP_NONLL_CQE vxge_mBIT(19) 4287 #define VXGE_HW_RPE_PCI_CFG_NOSNOOP_LL_CQE vxge_mBIT(20) 4288 #define VXGE_HW_RPE_PCI_CFG_NOSNOOP_CQRQ_IR vxge_mBIT(21) 4289 #define VXGE_HW_RPE_PCI_CFG_NOSNOOP_CQSQ_IR vxge_mBIT(22) 4290 #define VXGE_HW_RPE_PCI_CFG_NOSNOOP_CQRR_IR vxge_mBIT(23) 4291 #define VXGE_HW_RPE_PCI_CFG_RELAXED_DATA vxge_mBIT(26) 4292 #define VXGE_HW_RPE_PCI_CFG_RELAXED_NONLL_CQE vxge_mBIT(27) 4293 #define VXGE_HW_RPE_PCI_CFG_RELAXED_LL_CQE vxge_mBIT(28) 4294 #define VXGE_HW_RPE_PCI_CFG_RELAXED_CQRQ_IR vxge_mBIT(29) 4295 #define VXGE_HW_RPE_PCI_CFG_RELAXED_CQSQ_IR vxge_mBIT(30) 4296 #define VXGE_HW_RPE_PCI_CFG_RELAXED_CQRR_IR vxge_mBIT(31) 4297 /*0x01118*/ u64 rpe_lro_cfg; 4298 #define VXGE_HW_RPE_LRO_CFG_SUPPRESS_LRO_ETH_TRLR vxge_mBIT(7) 4299 #define VXGE_HW_RPE_LRO_CFG_ALLOW_LRO_SNAP_SNAPJUMBO_MRG vxge_mBIT(11) 4300 #define VXGE_HW_RPE_LRO_CFG_ALLOW_LRO_LLC_LLCJUMBO_MRG vxge_mBIT(15) 4301 #define VXGE_HW_RPE_LRO_CFG_INCL_ACK_CNT_IN_CQE vxge_mBIT(23) 4302 /*0x01120*/ u64 pe_mr2vp_ack_blk_limit; 4303 #define VXGE_HW_PE_MR2VP_ACK_BLK_LIMIT_BLK_LIMIT(val) vxge_vBIT(val, 32, 32) 4304 /*0x01128*/ u64 pe_mr2vp_rirr_lirr_blk_limit; 4305 #define VXGE_HW_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_RIRR_BLK_LIMIT(val) \ 4306 vxge_vBIT(val, 0, 32) 4307 #define VXGE_HW_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_LIRR_BLK_LIMIT(val) \ 4308 vxge_vBIT(val, 32, 32) 4309 /*0x01130*/ u64 txpe_pci_nce_cfg; 4310 #define VXGE_HW_TXPE_PCI_NCE_CFG_NCE_THRESH(val) vxge_vBIT(val, 0, 32) 4311 #define VXGE_HW_TXPE_PCI_NCE_CFG_PAD_TOWI_ENABLE vxge_mBIT(55) 4312 #define VXGE_HW_TXPE_PCI_NCE_CFG_NOSNOOP_TOWI vxge_mBIT(63) 4313 u8 unused01180[0x01180-0x01138]; 4314 4315 /*0x01180*/ u64 msg_qpad_en_cfg; 4316 #define VXGE_HW_MSG_QPAD_EN_CFG_UMQ_BWR_READ vxge_mBIT(3) 4317 #define VXGE_HW_MSG_QPAD_EN_CFG_DMQ_BWR_READ vxge_mBIT(7) 4318 #define VXGE_HW_MSG_QPAD_EN_CFG_MXP_GENDMA_READ vxge_mBIT(11) 4319 #define VXGE_HW_MSG_QPAD_EN_CFG_UXP_GENDMA_READ vxge_mBIT(15) 4320 #define VXGE_HW_MSG_QPAD_EN_CFG_UMQ_MSG_WRITE vxge_mBIT(19) 4321 #define VXGE_HW_MSG_QPAD_EN_CFG_UMQDMQ_IR_WRITE vxge_mBIT(23) 4322 #define VXGE_HW_MSG_QPAD_EN_CFG_MXP_GENDMA_WRITE vxge_mBIT(27) 4323 #define VXGE_HW_MSG_QPAD_EN_CFG_UXP_GENDMA_WRITE vxge_mBIT(31) 4324 /*0x01188*/ u64 msg_pci_cfg; 4325 #define VXGE_HW_MSG_PCI_CFG_GENDMA_NO_SNOOP vxge_mBIT(3) 4326 #define VXGE_HW_MSG_PCI_CFG_UMQDMQ_IR_NO_SNOOP vxge_mBIT(7) 4327 #define VXGE_HW_MSG_PCI_CFG_UMQ_NO_SNOOP vxge_mBIT(11) 4328 #define VXGE_HW_MSG_PCI_CFG_DMQ_NO_SNOOP vxge_mBIT(15) 4329 /*0x01190*/ u64 umqdmq_ir_init; 4330 #define VXGE_HW_UMQDMQ_IR_INIT_HOST_WRITE_ADD(val) vxge_vBIT(val, 0, 64) 4331 /*0x01198*/ u64 dmq_ir_int; 4332 #define VXGE_HW_DMQ_IR_INT_IMMED_ENABLE vxge_mBIT(6) 4333 #define VXGE_HW_DMQ_IR_INT_EVENT_ENABLE vxge_mBIT(7) 4334 #define VXGE_HW_DMQ_IR_INT_NUMBER(val) vxge_vBIT(val, 9, 7) 4335 #define VXGE_HW_DMQ_IR_INT_BITMAP(val) vxge_vBIT(val, 16, 16) 4336 /*0x011a0*/ u64 dmq_bwr_init_add; 4337 #define VXGE_HW_DMQ_BWR_INIT_ADD_HOST(val) vxge_vBIT(val, 0, 64) 4338 /*0x011a8*/ u64 dmq_bwr_init_byte; 4339 #define VXGE_HW_DMQ_BWR_INIT_BYTE_COUNT(val) vxge_vBIT(val, 0, 32) 4340 /*0x011b0*/ u64 dmq_ir; 4341 #define VXGE_HW_DMQ_IR_POLICY(val) vxge_vBIT(val, 0, 8) 4342 /*0x011b8*/ u64 umq_int; 4343 #define VXGE_HW_UMQ_INT_IMMED_ENABLE vxge_mBIT(6) 4344 #define VXGE_HW_UMQ_INT_EVENT_ENABLE vxge_mBIT(7) 4345 #define VXGE_HW_UMQ_INT_NUMBER(val) vxge_vBIT(val, 9, 7) 4346 #define VXGE_HW_UMQ_INT_BITMAP(val) vxge_vBIT(val, 16, 16) 4347 /*0x011c0*/ u64 umq_mr2vp_bwr_pfch_init; 4348 #define VXGE_HW_UMQ_MR2VP_BWR_PFCH_INIT_NUMBER(val) vxge_vBIT(val, 0, 8) 4349 /*0x011c8*/ u64 umq_bwr_pfch_ctrl; 4350 #define VXGE_HW_UMQ_BWR_PFCH_CTRL_POLL_EN vxge_mBIT(3) 4351 /*0x011d0*/ u64 umq_mr2vp_bwr_eol; 4352 #define VXGE_HW_UMQ_MR2VP_BWR_EOL_POLL_LATENCY(val) vxge_vBIT(val, 32, 32) 4353 /*0x011d8*/ u64 umq_bwr_init_add; 4354 #define VXGE_HW_UMQ_BWR_INIT_ADD_HOST(val) vxge_vBIT(val, 0, 64) 4355 /*0x011e0*/ u64 umq_bwr_init_byte; 4356 #define VXGE_HW_UMQ_BWR_INIT_BYTE_COUNT(val) vxge_vBIT(val, 0, 32) 4357 /*0x011e8*/ u64 gendma_int; 4358 /*0x011f0*/ u64 umqdmq_ir_init_notify; 4359 #define VXGE_HW_UMQDMQ_IR_INIT_NOTIFY_PULSE vxge_mBIT(3) 4360 /*0x011f8*/ u64 dmq_init_notify; 4361 #define VXGE_HW_DMQ_INIT_NOTIFY_PULSE vxge_mBIT(3) 4362 /*0x01200*/ u64 umq_init_notify; 4363 #define VXGE_HW_UMQ_INIT_NOTIFY_PULSE vxge_mBIT(3) 4364 u8 unused01380[0x01380-0x01208]; 4365 4366 /*0x01380*/ u64 tpa_cfg; 4367 #define VXGE_HW_TPA_CFG_IGNORE_FRAME_ERR vxge_mBIT(3) 4368 #define VXGE_HW_TPA_CFG_IPV6_STOP_SEARCHING vxge_mBIT(7) 4369 #define VXGE_HW_TPA_CFG_L4_PSHDR_PRESENT vxge_mBIT(11) 4370 #define VXGE_HW_TPA_CFG_SUPPORT_MOBILE_IPV6_HDRS vxge_mBIT(15) 4371 u8 unused01400[0x01400-0x01388]; 4372 4373 /*0x01400*/ u64 tx_vp_reset_discarded_frms; 4374 #define VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_TX_VP_RESET_DISCARDED_FRMS(val) \ 4375 vxge_vBIT(val, 48, 16) 4376 u8 unused01480[0x01480-0x01408]; 4377 4378 /*0x01480*/ u64 fau_rpa_vcfg; 4379 #define VXGE_HW_FAU_RPA_VCFG_L4_COMP_CSUM vxge_mBIT(7) 4380 #define VXGE_HW_FAU_RPA_VCFG_L3_INCL_CF vxge_mBIT(11) 4381 #define VXGE_HW_FAU_RPA_VCFG_L3_COMP_CSUM vxge_mBIT(15) 4382 u8 unused014d0[0x014d0-0x01488]; 4383 4384 /*0x014d0*/ u64 dbg_stats_rx_mpa; 4385 #define VXGE_HW_DBG_STATS_RX_MPA_CRC_FAIL_FRMS(val) vxge_vBIT(val, 0, 16) 4386 #define VXGE_HW_DBG_STATS_RX_MPA_MRK_FAIL_FRMS(val) vxge_vBIT(val, 16, 16) 4387 #define VXGE_HW_DBG_STATS_RX_MPA_LEN_FAIL_FRMS(val) vxge_vBIT(val, 32, 16) 4388 /*0x014d8*/ u64 dbg_stats_rx_fau; 4389 #define VXGE_HW_DBG_STATS_RX_FAU_RX_WOL_FRMS(val) vxge_vBIT(val, 0, 16) 4390 #define VXGE_HW_DBG_STATS_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val) \ 4391 vxge_vBIT(val, 16, 16) 4392 #define VXGE_HW_DBG_STATS_RX_FAU_RX_PERMITTED_FRMS(val) \ 4393 vxge_vBIT(val, 32, 32) 4394 u8 unused014f0[0x014f0-0x014e0]; 4395 4396 /*0x014f0*/ u64 fbmc_vp_rdy; 4397 #define VXGE_HW_FBMC_VP_RDY_QUEUE_SPAV_FM vxge_mBIT(0) 4398 u8 unused01e00[0x01e00-0x014f8]; 4399 4400 /*0x01e00*/ u64 vpath_pcipif_int_status; 4401 #define \ 4402 VXGE_HW_VPATH_PCIPIF_INT_STATUS_SRPCIM_MSG_TO_VPATH_SRPCIM_MSG_TO_VPATH_INT \ 4403 vxge_mBIT(3) 4404 #define VXGE_HW_VPATH_PCIPIF_INT_STATUS_VPATH_SPARE_R1_VPATH_SPARE_R1_INT \ 4405 vxge_mBIT(7) 4406 /*0x01e08*/ u64 vpath_pcipif_int_mask; 4407 u8 unused01e20[0x01e20-0x01e10]; 4408 4409 /*0x01e20*/ u64 srpcim_msg_to_vpath_reg; 4410 #define VXGE_HW_SRPCIM_MSG_TO_VPATH_REG_SWIF_SRPCIM_TO_VPATH_RMSG_INT \ 4411 vxge_mBIT(3) 4412 /*0x01e28*/ u64 srpcim_msg_to_vpath_mask; 4413 /*0x01e30*/ u64 srpcim_msg_to_vpath_alarm; 4414 u8 unused01ea0[0x01ea0-0x01e38]; 4415 4416 /*0x01ea0*/ u64 vpath_to_srpcim_wmsg; 4417 #define VXGE_HW_VPATH_TO_SRPCIM_WMSG_VPATH_TO_SRPCIM_WMSG(val) \ 4418 vxge_vBIT(val, 0, 64) 4419 /*0x01ea8*/ u64 vpath_to_srpcim_wmsg_trig; 4420 #define VXGE_HW_VPATH_TO_SRPCIM_WMSG_TRIG_VPATH_TO_SRPCIM_WMSG_TRIG \ 4421 vxge_mBIT(0) 4422 u8 unused02000[0x02000-0x01eb0]; 4423 4424 /*0x02000*/ u64 vpath_general_int_status; 4425 #define VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT vxge_mBIT(3) 4426 #define VXGE_HW_VPATH_GENERAL_INT_STATUS_PCI_INT vxge_mBIT(7) 4427 #define VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT vxge_mBIT(15) 4428 #define VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT vxge_mBIT(19) 4429 /*0x02008*/ u64 vpath_general_int_mask; 4430 #define VXGE_HW_VPATH_GENERAL_INT_MASK_PIC_INT vxge_mBIT(3) 4431 #define VXGE_HW_VPATH_GENERAL_INT_MASK_PCI_INT vxge_mBIT(7) 4432 #define VXGE_HW_VPATH_GENERAL_INT_MASK_WRDMA_INT vxge_mBIT(15) 4433 #define VXGE_HW_VPATH_GENERAL_INT_MASK_XMAC_INT vxge_mBIT(19) 4434 /*0x02010*/ u64 vpath_ppif_int_status; 4435 #define VXGE_HW_VPATH_PPIF_INT_STATUS_KDFCCTL_ERRORS_KDFCCTL_INT \ 4436 vxge_mBIT(3) 4437 #define VXGE_HW_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_GENERAL_INT \ 4438 vxge_mBIT(7) 4439 #define VXGE_HW_VPATH_PPIF_INT_STATUS_PCI_CONFIG_ERRORS_PCI_CONFIG_INT \ 4440 vxge_mBIT(11) 4441 #define \ 4442 VXGE_HW_VPATH_PPIF_INT_STATUS_MRPCIM_TO_VPATH_ALARM_MRPCIM_TO_VPATH_ALARM_INT \ 4443 vxge_mBIT(15) 4444 #define \ 4445 VXGE_HW_VPATH_PPIF_INT_STATUS_SRPCIM_TO_VPATH_ALARM_SRPCIM_TO_VPATH_ALARM_INT \ 4446 vxge_mBIT(19) 4447 /*0x02018*/ u64 vpath_ppif_int_mask; 4448 /*0x02020*/ u64 kdfcctl_errors_reg; 4449 #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR vxge_mBIT(3) 4450 #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR vxge_mBIT(7) 4451 #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR vxge_mBIT(11) 4452 #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON vxge_mBIT(15) 4453 #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON vxge_mBIT(19) 4454 #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON vxge_mBIT(23) 4455 #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR vxge_mBIT(31) 4456 #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR vxge_mBIT(35) 4457 #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR vxge_mBIT(39) 4458 /*0x02028*/ u64 kdfcctl_errors_mask; 4459 /*0x02030*/ u64 kdfcctl_errors_alarm; 4460 u8 unused02040[0x02040-0x02038]; 4461 4462 /*0x02040*/ u64 general_errors_reg; 4463 #define VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW vxge_mBIT(3) 4464 #define VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW vxge_mBIT(7) 4465 #define VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW vxge_mBIT(11) 4466 #define VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR vxge_mBIT(15) 4467 #define VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ vxge_mBIT(19) 4468 #define VXGE_HW_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS vxge_mBIT(27) 4469 #define VXGE_HW_GENERAL_ERRORS_REG_INI_SERR_DET vxge_mBIT(31) 4470 /*0x02048*/ u64 general_errors_mask; 4471 /*0x02050*/ u64 general_errors_alarm; 4472 /*0x02058*/ u64 pci_config_errors_reg; 4473 #define VXGE_HW_PCI_CONFIG_ERRORS_REG_PCICONFIG_STATUS_ERR vxge_mBIT(3) 4474 #define VXGE_HW_PCI_CONFIG_ERRORS_REG_PCICONFIG_UNCOR_ERR vxge_mBIT(7) 4475 #define VXGE_HW_PCI_CONFIG_ERRORS_REG_PCICONFIG_COR_ERR vxge_mBIT(11) 4476 /*0x02060*/ u64 pci_config_errors_mask; 4477 /*0x02068*/ u64 pci_config_errors_alarm; 4478 /*0x02070*/ u64 mrpcim_to_vpath_alarm_reg; 4479 #define VXGE_HW_MRPCIM_TO_VPATH_ALARM_REG_PPIF_MRPCIM_TO_VPATH_ALARM \ 4480 vxge_mBIT(3) 4481 /*0x02078*/ u64 mrpcim_to_vpath_alarm_mask; 4482 /*0x02080*/ u64 mrpcim_to_vpath_alarm_alarm; 4483 /*0x02088*/ u64 srpcim_to_vpath_alarm_reg; 4484 #define VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_PPIF_SRPCIM_TO_VPATH_ALARM(val) \ 4485 vxge_vBIT(val, 0, 17) 4486 /*0x02090*/ u64 srpcim_to_vpath_alarm_mask; 4487 /*0x02098*/ u64 srpcim_to_vpath_alarm_alarm; 4488 u8 unused02108[0x02108-0x020a0]; 4489 4490 /*0x02108*/ u64 kdfcctl_status; 4491 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO0_PRES(val) vxge_vBIT(val, 0, 8) 4492 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO1_PRES(val) vxge_vBIT(val, 8, 8) 4493 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO2_PRES(val) vxge_vBIT(val, 16, 8) 4494 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO0_OVRWR(val) vxge_vBIT(val, 24, 8) 4495 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO1_OVRWR(val) vxge_vBIT(val, 32, 8) 4496 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO2_OVRWR(val) vxge_vBIT(val, 40, 8) 4497 /*0x02110*/ u64 rsthdlr_status; 4498 #define VXGE_HW_RSTHDLR_STATUS_RSTHDLR_CURRENT_RESET vxge_mBIT(3) 4499 #define VXGE_HW_RSTHDLR_STATUS_RSTHDLR_CURRENT_VPIN(val) vxge_vBIT(val, 6, 2) 4500 /*0x02118*/ u64 fifo0_status; 4501 #define VXGE_HW_FIFO0_STATUS_DBLGEN_FIFO0_RDIDX(val) vxge_vBIT(val, 0, 12) 4502 /*0x02120*/ u64 fifo1_status; 4503 #define VXGE_HW_FIFO1_STATUS_DBLGEN_FIFO1_RDIDX(val) vxge_vBIT(val, 0, 12) 4504 /*0x02128*/ u64 fifo2_status; 4505 #define VXGE_HW_FIFO2_STATUS_DBLGEN_FIFO2_RDIDX(val) vxge_vBIT(val, 0, 12) 4506 u8 unused02158[0x02158-0x02130]; 4507 4508 /*0x02158*/ u64 tgt_illegal_access; 4509 #define VXGE_HW_TGT_ILLEGAL_ACCESS_SWIF_REGION(val) vxge_vBIT(val, 1, 7) 4510 u8 unused02200[0x02200-0x02160]; 4511 4512 /*0x02200*/ u64 vpath_general_cfg1; 4513 #define VXGE_HW_VPATH_GENERAL_CFG1_TC_VALUE(val) vxge_vBIT(val, 1, 3) 4514 #define VXGE_HW_VPATH_GENERAL_CFG1_DATA_BYTE_SWAPEN vxge_mBIT(7) 4515 #define VXGE_HW_VPATH_GENERAL_CFG1_DATA_FLIPEN vxge_mBIT(11) 4516 #define VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN vxge_mBIT(15) 4517 #define VXGE_HW_VPATH_GENERAL_CFG1_CTL_FLIPEN vxge_mBIT(23) 4518 #define VXGE_HW_VPATH_GENERAL_CFG1_MSIX_ADDR_SWAPEN vxge_mBIT(51) 4519 #define VXGE_HW_VPATH_GENERAL_CFG1_MSIX_ADDR_FLIPEN vxge_mBIT(55) 4520 #define VXGE_HW_VPATH_GENERAL_CFG1_MSIX_DATA_SWAPEN vxge_mBIT(59) 4521 #define VXGE_HW_VPATH_GENERAL_CFG1_MSIX_DATA_FLIPEN vxge_mBIT(63) 4522 /*0x02208*/ u64 vpath_general_cfg2; 4523 #define VXGE_HW_VPATH_GENERAL_CFG2_SIZE_QUANTUM(val) vxge_vBIT(val, 1, 3) 4524 /*0x02210*/ u64 vpath_general_cfg3; 4525 #define VXGE_HW_VPATH_GENERAL_CFG3_IGNORE_VPATH_RST_FOR_INTA vxge_mBIT(3) 4526 u8 unused02220[0x02220-0x02218]; 4527 4528 /*0x02220*/ u64 kdfcctl_cfg0; 4529 #define VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 vxge_mBIT(1) 4530 #define VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1 vxge_mBIT(2) 4531 #define VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2 vxge_mBIT(3) 4532 #define VXGE_HW_KDFCCTL_CFG0_BIT_FLIPEN_FIFO0 vxge_mBIT(5) 4533 #define VXGE_HW_KDFCCTL_CFG0_BIT_FLIPEN_FIFO1 vxge_mBIT(6) 4534 #define VXGE_HW_KDFCCTL_CFG0_BIT_FLIPEN_FIFO2 vxge_mBIT(7) 4535 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO0 vxge_mBIT(9) 4536 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO1 vxge_mBIT(10) 4537 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO2 vxge_mBIT(11) 4538 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO0 vxge_mBIT(13) 4539 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO1 vxge_mBIT(14) 4540 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO2 vxge_mBIT(15) 4541 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO0 vxge_mBIT(17) 4542 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO1 vxge_mBIT(18) 4543 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO2 vxge_mBIT(19) 4544 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO0 vxge_mBIT(21) 4545 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO1 vxge_mBIT(22) 4546 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO2 vxge_mBIT(23) 4547 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO0 vxge_mBIT(25) 4548 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO1 vxge_mBIT(26) 4549 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO2 vxge_mBIT(27) 4550 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO0 vxge_mBIT(29) 4551 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO1 vxge_mBIT(30) 4552 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO2 vxge_mBIT(31) 4553 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO0 vxge_mBIT(33) 4554 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO1 vxge_mBIT(34) 4555 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO2 vxge_mBIT(35) 4556 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO0 vxge_mBIT(37) 4557 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO1 vxge_mBIT(38) 4558 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO2 vxge_mBIT(39) 4559 4560 u8 unused02268[0x02268-0x02228]; 4561 4562 /*0x02268*/ u64 stats_cfg; 4563 #define VXGE_HW_STATS_CFG_START_HOST_ADDR(val) vxge_vBIT(val, 0, 57) 4564 /*0x02270*/ u64 interrupt_cfg0; 4565 #define VXGE_HW_INTERRUPT_CFG0_MSIX_FOR_RXTI(val) vxge_vBIT(val, 1, 7) 4566 #define VXGE_HW_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(val) vxge_vBIT(val, 9, 7) 4567 #define VXGE_HW_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(val) vxge_vBIT(val, 17, 7) 4568 #define VXGE_HW_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI(val) vxge_vBIT(val, 25, 7) 4569 #define VXGE_HW_INTERRUPT_CFG0_GROUP3_MSIX_FOR_TXTI(val) vxge_vBIT(val, 33, 7) 4570 u8 unused02280[0x02280-0x02278]; 4571 4572 /*0x02280*/ u64 interrupt_cfg2; 4573 #define VXGE_HW_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(val) vxge_vBIT(val, 1, 7) 4574 /*0x02288*/ u64 one_shot_vect0_en; 4575 #define VXGE_HW_ONE_SHOT_VECT0_EN_ONE_SHOT_VECT0_EN vxge_mBIT(3) 4576 /*0x02290*/ u64 one_shot_vect1_en; 4577 #define VXGE_HW_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN vxge_mBIT(3) 4578 /*0x02298*/ u64 one_shot_vect2_en; 4579 #define VXGE_HW_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN vxge_mBIT(3) 4580 /*0x022a0*/ u64 one_shot_vect3_en; 4581 #define VXGE_HW_ONE_SHOT_VECT3_EN_ONE_SHOT_VECT3_EN vxge_mBIT(3) 4582 u8 unused022b0[0x022b0-0x022a8]; 4583 4584 /*0x022b0*/ u64 pci_config_access_cfg1; 4585 #define VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(val) vxge_vBIT(val, 0, 12) 4586 #define VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0 vxge_mBIT(15) 4587 /*0x022b8*/ u64 pci_config_access_cfg2; 4588 #define VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ vxge_mBIT(0) 4589 /*0x022c0*/ u64 pci_config_access_status; 4590 #define VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR vxge_mBIT(0) 4591 #define VXGE_HW_PCI_CONFIG_ACCESS_STATUS_DATA(val) vxge_vBIT(val, 32, 32) 4592 u8 unused02300[0x02300-0x022c8]; 4593 4594 /*0x02300*/ u64 vpath_debug_stats0; 4595 #define VXGE_HW_VPATH_DEBUG_STATS0_INI_NUM_MWR_SENT(val) vxge_vBIT(val, 0, 32) 4596 /*0x02308*/ u64 vpath_debug_stats1; 4597 #define VXGE_HW_VPATH_DEBUG_STATS1_INI_NUM_MRD_SENT(val) vxge_vBIT(val, 0, 32) 4598 /*0x02310*/ u64 vpath_debug_stats2; 4599 #define VXGE_HW_VPATH_DEBUG_STATS2_INI_NUM_CPL_RCVD(val) vxge_vBIT(val, 0, 32) 4600 /*0x02318*/ u64 vpath_debug_stats3; 4601 #define VXGE_HW_VPATH_DEBUG_STATS3_INI_NUM_MWR_BYTE_SENT(val) \ 4602 vxge_vBIT(val, 0, 64) 4603 /*0x02320*/ u64 vpath_debug_stats4; 4604 #define VXGE_HW_VPATH_DEBUG_STATS4_INI_NUM_CPL_BYTE_RCVD(val) \ 4605 vxge_vBIT(val, 0, 64) 4606 /*0x02328*/ u64 vpath_debug_stats5; 4607 #define VXGE_HW_VPATH_DEBUG_STATS5_WRCRDTARB_XOFF(val) vxge_vBIT(val, 32, 32) 4608 /*0x02330*/ u64 vpath_debug_stats6; 4609 #define VXGE_HW_VPATH_DEBUG_STATS6_RDCRDTARB_XOFF(val) vxge_vBIT(val, 32, 32) 4610 /*0x02338*/ u64 vpath_genstats_count01; 4611 #define VXGE_HW_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT1(val) \ 4612 vxge_vBIT(val, 0, 32) 4613 #define VXGE_HW_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT0(val) \ 4614 vxge_vBIT(val, 32, 32) 4615 /*0x02340*/ u64 vpath_genstats_count23; 4616 #define VXGE_HW_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT3(val) \ 4617 vxge_vBIT(val, 0, 32) 4618 #define VXGE_HW_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT2(val) \ 4619 vxge_vBIT(val, 32, 32) 4620 /*0x02348*/ u64 vpath_genstats_count4; 4621 #define VXGE_HW_VPATH_GENSTATS_COUNT4_PPIF_VPATH_GENSTATS_COUNT4(val) \ 4622 vxge_vBIT(val, 32, 32) 4623 /*0x02350*/ u64 vpath_genstats_count5; 4624 #define VXGE_HW_VPATH_GENSTATS_COUNT5_PPIF_VPATH_GENSTATS_COUNT5(val) \ 4625 vxge_vBIT(val, 32, 32) 4626 u8 unused02648[0x02648-0x02358]; 4627 } __packed; 4628 4629 #define VXGE_HW_EEPROM_SIZE (0x01 << 11) 4630 4631 /* Capability lists */ 4632 #define VXGE_HW_PCI_EXP_LNKCAP_LNK_SPEED 0xf /* Supported Link speeds */ 4633 #define VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH 0x3f0 /* Supported Link speeds. */ 4634 #define VXGE_HW_PCI_EXP_LNKCAP_LW_RES 0x0 /* Reserved. */ 4635 4636 #endif 4637
