1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Micrel KS8695 (Centaur) Ethernet. 4 * 5 * Copyright 2008 Simtec Electronics 6 * Daniel Silverstone <dsilvers@simtec.co.uk> 7 * Vincent Sanders <vince@simtec.co.uk> 8 */ 9 10 #ifndef KS8695NET_H 11 #define KS8695NET_H 12 13 /* Receive descriptor flags */ 14 #define RDES_OWN (1 << 31) /* Ownership */ 15 #define RDES_FS (1 << 30) /* First Descriptor */ 16 #define RDES_LS (1 << 29) /* Last Descriptor */ 17 #define RDES_IPE (1 << 28) /* IP Checksum error */ 18 #define RDES_TCPE (1 << 27) /* TCP Checksum error */ 19 #define RDES_UDPE (1 << 26) /* UDP Checksum error */ 20 #define RDES_ES (1 << 25) /* Error summary */ 21 #define RDES_MF (1 << 24) /* Multicast Frame */ 22 #define RDES_RE (1 << 19) /* MII Error reported */ 23 #define RDES_TL (1 << 18) /* Frame too Long */ 24 #define RDES_RF (1 << 17) /* Runt Frame */ 25 #define RDES_CE (1 << 16) /* CRC error */ 26 #define RDES_FT (1 << 15) /* Frame Type */ 27 #define RDES_FLEN (0x7ff) /* Frame Length */ 28 29 #define RDES_RER (1 << 25) /* Receive End of Ring */ 30 #define RDES_RBS (0x7ff) /* Receive Buffer Size */ 31 32 /* Transmit descriptor flags */ 33 34 #define TDES_OWN (1 << 31) /* Ownership */ 35 36 #define TDES_IC (1 << 31) /* Interrupt on Completion */ 37 #define TDES_FS (1 << 30) /* First Segment */ 38 #define TDES_LS (1 << 29) /* Last Segment */ 39 #define TDES_IPCKG (1 << 28) /* IP Checksum generate */ 40 #define TDES_TCPCKG (1 << 27) /* TCP Checksum generate */ 41 #define TDES_UDPCKG (1 << 26) /* UDP Checksum generate */ 42 #define TDES_TER (1 << 25) /* Transmit End of Ring */ 43 #define TDES_TBS (0x7ff) /* Transmit Buffer Size */ 44 45 /* 46 * Network controller register offsets 47 */ 48 #define KS8695_DTXC (0x00) /* DMA Transmit Control */ 49 #define KS8695_DRXC (0x04) /* DMA Receive Control */ 50 #define KS8695_DTSC (0x08) /* DMA Transmit Start Command */ 51 #define KS8695_DRSC (0x0c) /* DMA Receive Start Command */ 52 #define KS8695_TDLB (0x10) /* Transmit Descriptor List 53 * Base Address 54 */ 55 #define KS8695_RDLB (0x14) /* Receive Descriptor List 56 * Base Address 57 */ 58 #define KS8695_MAL (0x18) /* MAC Station Address Low */ 59 #define KS8695_MAH (0x1c) /* MAC Station Address High */ 60 #define KS8695_AAL_(n) (0x80 + ((n)*8)) /* MAC Additional 61 * Station Address 62 * (0..15) Low 63 */ 64 #define KS8695_AAH_(n) (0x84 + ((n)*8)) /* MAC Additional 65 * Station Address 66 * (0..15) High 67 */ 68 69 70 /* DMA Transmit Control Register */ 71 #define DTXC_TRST (1 << 31) /* Soft Reset */ 72 #define DTXC_TBS (0x3f << 24) /* Transmit Burst Size */ 73 #define DTXC_TUCG (1 << 18) /* Transmit UDP 74 * Checksum Generate 75 */ 76 #define DTXC_TTCG (1 << 17) /* Transmit TCP 77 * Checksum Generate 78 */ 79 #define DTXC_TICG (1 << 16) /* Transmit IP 80 * Checksum Generate 81 */ 82 #define DTXC_TFCE (1 << 9) /* Transmit Flow 83 * Control Enable 84 */ 85 #define DTXC_TLB (1 << 8) /* Loopback mode */ 86 #define DTXC_TEP (1 << 2) /* Transmit Enable Padding */ 87 #define DTXC_TAC (1 << 1) /* Transmit Add CRC */ 88 #define DTXC_TE (1 << 0) /* TX Enable */ 89 90 /* DMA Receive Control Register */ 91 #define DRXC_RBS (0x3f << 24) /* Receive Burst Size */ 92 #define DRXC_RUCC (1 << 18) /* Receive UDP Checksum check */ 93 #define DRXC_RTCG (1 << 17) /* Receive TCP Checksum check */ 94 #define DRXC_RICG (1 << 16) /* Receive IP Checksum check */ 95 #define DRXC_RFCE (1 << 9) /* Receive Flow Control 96 * Enable 97 */ 98 #define DRXC_RB (1 << 6) /* Receive Broadcast */ 99 #define DRXC_RM (1 << 5) /* Receive Multicast */ 100 #define DRXC_RU (1 << 4) /* Receive Unicast */ 101 #define DRXC_RERR (1 << 3) /* Receive Error Frame */ 102 #define DRXC_RA (1 << 2) /* Receive All */ 103 #define DRXC_RE (1 << 0) /* RX Enable */ 104 105 /* Additional Station Address High */ 106 #define AAH_E (1 << 31) /* Address Enabled */ 107 108 #endif /* KS8695NET_H */ 109
