1 /*
2  *  Copyright (C) 2017 Chelsio Communications.  All rights reserved.
3  *
4  *  This program is free software; you can redistribute it and/or modify it
5  *  under the terms and conditions of the GNU General Public License,
6  *  version 2, as published by the Free Software Foundation.
7  *
8  *  This program is distributed in the hope it will be useful, but WITHOUT
9  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  *  more details.
12  *
13  *  The full GNU General Public License is included in this distribution in
14  *  the file called "COPYING".
15  *
16  */
17 
18 #ifndef __CUDBG_ENTITY_H__
19 #define __CUDBG_ENTITY_H__
20 
21 #define EDC0_FLAG 0
22 #define EDC1_FLAG 1
23 #define MC_FLAG 2
24 #define MC0_FLAG 3
25 #define MC1_FLAG 4
26 #define HMA_FLAG 5
27 
28 #define CUDBG_ENTITY_SIGNATURE 0xCCEDB001
29 
30 struct cudbg_mbox_log {
31 	struct mbox_cmd entry;
32 	u32 hi[MBOX_LEN / 8];
33 	u32 lo[MBOX_LEN / 8];
34 };
35 
36 struct cudbg_cim_qcfg {
37 	u8 chip;
38 	u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
39 	u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
40 	u16 thres[CIM_NUM_IBQ];
41 	u32 obq_wr[2 * CIM_NUM_OBQ_T5];
42 	u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)];
43 };
44 
45 struct cudbg_rss_vf_conf {
46 	u32 rss_vf_vfl;
47 	u32 rss_vf_vfh;
48 };
49 
50 struct cudbg_pm_stats {
51 	u32 tx_cnt[T6_PM_NSTATS];
52 	u32 rx_cnt[T6_PM_NSTATS];
53 	u64 tx_cyc[T6_PM_NSTATS];
54 	u64 rx_cyc[T6_PM_NSTATS];
55 };
56 
57 struct cudbg_hw_sched {
58 	u32 kbps[NTX_SCHED];
59 	u32 ipg[NTX_SCHED];
60 	u32 pace_tab[NTX_SCHED];
61 	u32 mode;
62 	u32 map;
63 };
64 
65 #define SGE_QBASE_DATA_REG_NUM 4
66 
67 struct sge_qbase_reg_field {
68 	u32 reg_addr;
69 	u32 reg_data[SGE_QBASE_DATA_REG_NUM];
70 	/* Max supported PFs */
71 	u32 pf_data_value[PCIE_FW_MASTER_M + 1][SGE_QBASE_DATA_REG_NUM];
72 	/* Max supported VFs */
73 	u32 vf_data_value[T6_VF_M + 1][SGE_QBASE_DATA_REG_NUM];
74 	u32 vfcount; /* Actual number of max vfs in current configuration */
75 };
76 
77 struct ireg_field {
78 	u32 ireg_addr;
79 	u32 ireg_data;
80 	u32 ireg_local_offset;
81 	u32 ireg_offset_range;
82 };
83 
84 struct ireg_buf {
85 	struct ireg_field tp_pio;
86 	u32 outbuf[32];
87 };
88 
89 struct cudbg_ulprx_la {
90 	u32 data[ULPRX_LA_SIZE * 8];
91 	u32 size;
92 };
93 
94 struct cudbg_tp_la {
95 	u32 size;
96 	u32 mode;
97 	u8 data[0];
98 };
99 
100 static const char * const cudbg_region[] = {
101 	"DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
102 	"Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
103 	"Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
104 	"TDDP region:", "TPT region:", "STAG region:", "RQ region:",
105 	"RQUDP region:", "PBL region:", "TXPBL region:",
106 	"DBVFIFO region:", "ULPRX state:", "ULPTX state:",
107 	"On-chip queues:"
108 };
109 
110 /* Memory region info relative to current memory (i.e. wrt 0). */
111 struct cudbg_region_info {
112 	bool exist; /* Does region exists in current memory? */
113 	u32 start;  /* Start wrt 0 */
114 	u32 end;    /* End wrt 0 */
115 };
116 
117 struct cudbg_mem_desc {
118 	u32 base;
119 	u32 limit;
120 	u32 idx;
121 };
122 
123 #define CUDBG_MEMINFO_REV 1
124 
125 struct cudbg_meminfo {
126 	struct cudbg_mem_desc avail[4];
127 	struct cudbg_mem_desc mem[ARRAY_SIZE(cudbg_region) + 3];
128 	u32 avail_c;
129 	u32 mem_c;
130 	u32 up_ram_lo;
131 	u32 up_ram_hi;
132 	u32 up_extmem2_lo;
133 	u32 up_extmem2_hi;
134 	u32 rx_pages_data[3];
135 	u32 tx_pages_data[4];
136 	u32 p_structs;
137 	u32 reserved[12];
138 	u32 port_used[4];
139 	u32 port_alloc[4];
140 	u32 loopback_used[NCHAN];
141 	u32 loopback_alloc[NCHAN];
142 	u32 p_structs_free_cnt;
143 	u32 free_rx_cnt;
144 	u32 free_tx_cnt;
145 };
146 
147 struct cudbg_cim_pif_la {
148 	int size;
149 	u8 data[0];
150 };
151 
152 struct cudbg_clk_info {
153 	u64 retransmit_min;
154 	u64 retransmit_max;
155 	u64 persist_timer_min;
156 	u64 persist_timer_max;
157 	u64 keepalive_idle_timer;
158 	u64 keepalive_interval;
159 	u64 initial_srtt;
160 	u64 finwait2_timer;
161 	u32 dack_timer;
162 	u32 res;
163 	u32 cclk_ps;
164 	u32 tre;
165 	u32 dack_re;
166 };
167 
168 struct cudbg_tid_info_region {
169 	u32 ntids;
170 	u32 nstids;
171 	u32 stid_base;
172 	u32 hash_base;
173 
174 	u32 natids;
175 	u32 nftids;
176 	u32 ftid_base;
177 	u32 aftid_base;
178 	u32 aftid_end;
179 
180 	u32 sftid_base;
181 	u32 nsftids;
182 
183 	u32 uotid_base;
184 	u32 nuotids;
185 
186 	u32 sb;
187 	u32 flags;
188 	u32 le_db_conf;
189 	u32 ip_users;
190 	u32 ipv6_users;
191 
192 	u32 hpftid_base;
193 	u32 nhpftids;
194 };
195 
196 #define CUDBG_TID_INFO_REV 1
197 
198 struct cudbg_tid_info_region_rev1 {
199 	struct cudbg_ver_hdr ver_hdr;
200 	struct cudbg_tid_info_region tid;
201 	u32 tid_start;
202 	u32 reserved[16];
203 };
204 
205 #define CUDBG_LOWMEM_MAX_CTXT_QIDS 256
206 #define CUDBG_MAX_FL_QIDS 1024
207 
208 struct cudbg_ch_cntxt {
209 	u32 cntxt_type;
210 	u32 cntxt_id;
211 	u32 data[SGE_CTXT_SIZE / 4];
212 };
213 
214 #define CUDBG_MAX_RPLC_SIZE 128
215 
216 struct cudbg_mps_tcam {
217 	u64 mask;
218 	u32 rplc[8];
219 	u32 idx;
220 	u32 cls_lo;
221 	u32 cls_hi;
222 	u32 rplc_size;
223 	u32 vniy;
224 	u32 vnix;
225 	u32 dip_hit;
226 	u32 vlan_vld;
227 	u32 repli;
228 	u16 ivlan;
229 	u8 addr[ETH_ALEN];
230 	u8 lookup_type;
231 	u8 port_num;
232 	u8 reserved[2];
233 };
234 
235 #define CUDBG_VPD_PF_SIZE 0x800
236 #define CUDBG_SCFG_VER_ADDR 0x06
237 #define CUDBG_SCFG_VER_LEN 4
238 #define CUDBG_VPD_VER_ADDR 0x18c7
239 #define CUDBG_VPD_VER_LEN 2
240 
241 struct cudbg_vpd_data {
242 	u8 sn[SERNUM_LEN + 1];
243 	u8 bn[PN_LEN + 1];
244 	u8 na[MACADDR_LEN + 1];
245 	u8 mn[ID_LEN + 1];
246 	u16 fw_major;
247 	u16 fw_minor;
248 	u16 fw_micro;
249 	u16 fw_build;
250 	u32 scfg_vers;
251 	u32 vpd_vers;
252 };
253 
254 #define CUDBG_MAX_TCAM_TID 0x800
255 #define CUDBG_T6_CLIP 1536
256 #define CUDBG_MAX_TID_COMP_EN 6144
257 #define CUDBG_MAX_TID_COMP_DIS 3072
258 
259 enum cudbg_le_entry_types {
260 	LE_ET_UNKNOWN = 0,
261 	LE_ET_TCAM_CON = 1,
262 	LE_ET_TCAM_SERVER = 2,
263 	LE_ET_TCAM_FILTER = 3,
264 	LE_ET_TCAM_CLIP = 4,
265 	LE_ET_TCAM_ROUTING = 5,
266 	LE_ET_HASH_CON = 6,
267 	LE_ET_INVALID_TID = 8,
268 };
269 
270 struct cudbg_tcam {
271 	u32 filter_start;
272 	u32 server_start;
273 	u32 clip_start;
274 	u32 routing_start;
275 	u32 tid_hash_base;
276 	u32 max_tid;
277 };
278 
279 struct cudbg_tid_data {
280 	u32 tid;
281 	u32 dbig_cmd;
282 	u32 dbig_conf;
283 	u32 dbig_rsp_stat;
284 	u32 data[NUM_LE_DB_DBGI_RSP_DATA_INSTANCES];
285 };
286 
287 #define CUDBG_NUM_ULPTX 11
288 #define CUDBG_NUM_ULPTX_READ 512
289 #define CUDBG_NUM_ULPTX_ASIC 6
290 #define CUDBG_NUM_ULPTX_ASIC_READ 128
291 
292 #define CUDBG_ULPTX_LA_REV 1
293 
294 struct cudbg_ulptx_la {
295 	u32 rdptr[CUDBG_NUM_ULPTX];
296 	u32 wrptr[CUDBG_NUM_ULPTX];
297 	u32 rddata[CUDBG_NUM_ULPTX];
298 	u32 rd_data[CUDBG_NUM_ULPTX][CUDBG_NUM_ULPTX_READ];
299 	u32 rdptr_asic[CUDBG_NUM_ULPTX_ASIC_READ];
300 	u32 rddata_asic[CUDBG_NUM_ULPTX_ASIC_READ][CUDBG_NUM_ULPTX_ASIC];
301 };
302 
303 #define CUDBG_CHAC_PBT_ADDR 0x2800
304 #define CUDBG_CHAC_PBT_LRF  0x3000
305 #define CUDBG_CHAC_PBT_DATA 0x3800
306 #define CUDBG_PBT_DYNAMIC_ENTRIES 8
307 #define CUDBG_PBT_STATIC_ENTRIES 16
308 #define CUDBG_LRF_ENTRIES 8
309 #define CUDBG_PBT_DATA_ENTRIES 512
310 
311 struct cudbg_pbt_tables {
312 	u32 pbt_dynamic[CUDBG_PBT_DYNAMIC_ENTRIES];
313 	u32 pbt_static[CUDBG_PBT_STATIC_ENTRIES];
314 	u32 lrf_table[CUDBG_LRF_ENTRIES];
315 	u32 pbt_data[CUDBG_PBT_DATA_ENTRIES];
316 };
317 
318 #define IREG_NUM_ELEM 4
319 
320 static const u32 t6_tp_pio_array[][IREG_NUM_ELEM] = {
321 	{0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */
322 	{0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */
323 	{0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */
324 	{0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */
325 	{0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */
326 	{0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */
327 	{0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */
328 	{0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */
329 	{0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */
330 	{0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */
331 	{0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */
332 	{0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */
333 };
334 
335 static const u32 t5_tp_pio_array[][IREG_NUM_ELEM] = {
336 	{0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */
337 	{0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */
338 	{0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */
339 	{0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */
340 	{0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */
341 	{0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */
342 	{0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */
343 	{0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */
344 	{0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */
345 	{0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */
346 	{0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */
347 };
348 
349 static const u32 t6_tp_tm_pio_array[][IREG_NUM_ELEM] = {
350 	{0x7e18, 0x7e1c, 0x0, 12}
351 };
352 
353 static const u32 t5_tp_tm_pio_array[][IREG_NUM_ELEM] = {
354 	{0x7e18, 0x7e1c, 0x0, 12}
355 };
356 
357 static const u32 t6_tp_mib_index_array[6][IREG_NUM_ELEM] = {
358 	{0x7e50, 0x7e54, 0x0, 13},
359 	{0x7e50, 0x7e54, 0x10, 6},
360 	{0x7e50, 0x7e54, 0x18, 21},
361 	{0x7e50, 0x7e54, 0x30, 32},
362 	{0x7e50, 0x7e54, 0x50, 22},
363 	{0x7e50, 0x7e54, 0x68, 12}
364 };
365 
366 static const u32 t5_tp_mib_index_array[9][IREG_NUM_ELEM] = {
367 	{0x7e50, 0x7e54, 0x0, 13},
368 	{0x7e50, 0x7e54, 0x10, 6},
369 	{0x7e50, 0x7e54, 0x18, 8},
370 	{0x7e50, 0x7e54, 0x20, 13},
371 	{0x7e50, 0x7e54, 0x30, 16},
372 	{0x7e50, 0x7e54, 0x40, 16},
373 	{0x7e50, 0x7e54, 0x50, 16},
374 	{0x7e50, 0x7e54, 0x60, 6},
375 	{0x7e50, 0x7e54, 0x68, 4}
376 };
377 
378 static const u32 t5_sge_dbg_index_array[2][IREG_NUM_ELEM] = {
379 	{0x10cc, 0x10d0, 0x0, 16},
380 	{0x10cc, 0x10d4, 0x0, 16},
381 };
382 
383 static const u32 t6_sge_qbase_index_array[] = {
384 	/* 1 addr reg SGE_QBASE_INDEX and 4 data reg SGE_QBASE_MAP[0-3] */
385 	0x1250, 0x1240, 0x1244, 0x1248, 0x124c,
386 };
387 
388 static const u32 t5_pcie_pdbg_array[][IREG_NUM_ELEM] = {
389 	{0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */
390 	{0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */
391 	{0x5a04, 0x5a0c, 0x41, 0x10}, /* t5_pcie_pdbg_regs_41_to_50 */
392 };
393 
394 static const u32 t5_pcie_cdbg_array[][IREG_NUM_ELEM] = {
395 	{0x5a10, 0x5a18, 0x00, 0x20}, /* t5_pcie_cdbg_regs_00_to_20 */
396 	{0x5a10, 0x5a18, 0x21, 0x18}, /* t5_pcie_cdbg_regs_21_to_37 */
397 };
398 
399 static const u32 t5_pm_rx_array[][IREG_NUM_ELEM] = {
400 	{0x8FD0, 0x8FD4, 0x10000, 0x20}, /* t5_pm_rx_regs_10000_to_10020 */
401 	{0x8FD0, 0x8FD4, 0x10021, 0x0D}, /* t5_pm_rx_regs_10021_to_1002c */
402 };
403 
404 static const u32 t5_pm_tx_array[][IREG_NUM_ELEM] = {
405 	{0x8FF0, 0x8FF4, 0x10000, 0x20}, /* t5_pm_tx_regs_10000_to_10020 */
406 	{0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */
407 };
408 
409 #define CUDBG_NUM_PCIE_CONFIG_REGS 0x61
410 
411 static const u32 t5_pcie_config_array[][2] = {
412 	{0x0, 0x34},
413 	{0x3c, 0x40},
414 	{0x50, 0x64},
415 	{0x70, 0x80},
416 	{0x94, 0xa0},
417 	{0xb0, 0xb8},
418 	{0xd0, 0xd4},
419 	{0x100, 0x128},
420 	{0x140, 0x148},
421 	{0x150, 0x164},
422 	{0x170, 0x178},
423 	{0x180, 0x194},
424 	{0x1a0, 0x1b8},
425 	{0x1c0, 0x208},
426 };
427 
428 static const u32 t6_ma_ireg_array[][IREG_NUM_ELEM] = {
429 	{0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */
430 	{0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */
431 	{0x78f8, 0x78fc, 0xa800, 20} /* t6_ma_regs_a800_to_a813 */
432 };
433 
434 static const u32 t6_ma_ireg_array2[][IREG_NUM_ELEM] = {
435 	{0x78f8, 0x78fc, 0xe400, 17}, /* t6_ma_regs_e400_to_e600 */
436 	{0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */
437 };
438 
439 static const u32 t6_up_cim_reg_array[][IREG_NUM_ELEM + 1] = {
440 	{0x7b50, 0x7b54, 0x2000, 0x20, 0}, /* up_cim_2000_to_207c */
441 	{0x7b50, 0x7b54, 0x2080, 0x1d, 0}, /* up_cim_2080_to_20fc */
442 	{0x7b50, 0x7b54, 0x00, 0x20, 0}, /* up_cim_00_to_7c */
443 	{0x7b50, 0x7b54, 0x80, 0x20, 0}, /* up_cim_80_to_fc */
444 	{0x7b50, 0x7b54, 0x100, 0x11, 0}, /* up_cim_100_to_14c */
445 	{0x7b50, 0x7b54, 0x200, 0x10, 0}, /* up_cim_200_to_23c */
446 	{0x7b50, 0x7b54, 0x240, 0x2, 0}, /* up_cim_240_to_244 */
447 	{0x7b50, 0x7b54, 0x250, 0x2, 0}, /* up_cim_250_to_254 */
448 	{0x7b50, 0x7b54, 0x260, 0x2, 0}, /* up_cim_260_to_264 */
449 	{0x7b50, 0x7b54, 0x270, 0x2, 0}, /* up_cim_270_to_274 */
450 	{0x7b50, 0x7b54, 0x280, 0x20, 0}, /* up_cim_280_to_2fc */
451 	{0x7b50, 0x7b54, 0x300, 0x20, 0}, /* up_cim_300_to_37c */
452 	{0x7b50, 0x7b54, 0x380, 0x14, 0}, /* up_cim_380_to_3cc */
453 	{0x7b50, 0x7b54, 0x4900, 0x4, 0x4}, /* up_cim_4900_to_4c60 */
454 	{0x7b50, 0x7b54, 0x4904, 0x4, 0x4}, /* up_cim_4904_to_4c64 */
455 	{0x7b50, 0x7b54, 0x4908, 0x4, 0x4}, /* up_cim_4908_to_4c68 */
456 	{0x7b50, 0x7b54, 0x4910, 0x4, 0x4}, /* up_cim_4910_to_4c70 */
457 	{0x7b50, 0x7b54, 0x4914, 0x4, 0x4}, /* up_cim_4914_to_4c74 */
458 	{0x7b50, 0x7b54, 0x4920, 0x10, 0x10}, /* up_cim_4920_to_4a10 */
459 	{0x7b50, 0x7b54, 0x4924, 0x10, 0x10}, /* up_cim_4924_to_4a14 */
460 	{0x7b50, 0x7b54, 0x4928, 0x10, 0x10}, /* up_cim_4928_to_4a18 */
461 	{0x7b50, 0x7b54, 0x492c, 0x10, 0x10}, /* up_cim_492c_to_4a1c */
462 };
463 
464 static const u32 t5_up_cim_reg_array[][IREG_NUM_ELEM + 1] = {
465 	{0x7b50, 0x7b54, 0x2000, 0x20, 0}, /* up_cim_2000_to_207c */
466 	{0x7b50, 0x7b54, 0x2080, 0x19, 0}, /* up_cim_2080_to_20ec */
467 	{0x7b50, 0x7b54, 0x00, 0x20, 0}, /* up_cim_00_to_7c */
468 	{0x7b50, 0x7b54, 0x80, 0x20, 0}, /* up_cim_80_to_fc */
469 	{0x7b50, 0x7b54, 0x100, 0x11, 0}, /* up_cim_100_to_14c */
470 	{0x7b50, 0x7b54, 0x200, 0x10, 0}, /* up_cim_200_to_23c */
471 	{0x7b50, 0x7b54, 0x240, 0x2, 0}, /* up_cim_240_to_244 */
472 	{0x7b50, 0x7b54, 0x250, 0x2, 0}, /* up_cim_250_to_254 */
473 	{0x7b50, 0x7b54, 0x260, 0x2, 0}, /* up_cim_260_to_264 */
474 	{0x7b50, 0x7b54, 0x270, 0x2, 0}, /* up_cim_270_to_274 */
475 	{0x7b50, 0x7b54, 0x280, 0x20, 0}, /* up_cim_280_to_2fc */
476 	{0x7b50, 0x7b54, 0x300, 0x20, 0}, /* up_cim_300_to_37c */
477 	{0x7b50, 0x7b54, 0x380, 0x14, 0}, /* up_cim_380_to_3cc */
478 };
479 
480 static const u32 t6_hma_ireg_array[][IREG_NUM_ELEM] = {
481 	{0x51320, 0x51324, 0xa000, 32} /* t6_hma_regs_a000_to_a01f */
482 };
483 #endif /* __CUDBG_ENTITY_H__ */
484