1  /*
2   * Copyright 2012 Advanced Micro Devices, Inc.
3   *
4   * Permission is hereby granted, free of charge, to any person obtaining a
5   * copy of this software and associated documentation files (the "Software"),
6   * to deal in the Software without restriction, including without limitation
7   * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8   * and/or sell copies of the Software, and to permit persons to whom the
9   * Software is furnished to do so, subject to the following conditions:
10   *
11   * The above copyright notice and this permission notice shall be included in
12   * all copies or substantial portions of the Software.
13   *
14   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17   * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18   * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19   * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20   * OTHER DEALINGS IN THE SOFTWARE.
21   *
22   * Authors: Alex Deucher
23   */
24  #ifndef _SUMOD_H_
25  #define _SUMOD_H_
26  
27  /* pm registers */
28  
29  /* rcu */
30  #define RCU_FW_VERSION                                  0x30c
31  
32  #define RCU_PWR_GATING_SEQ0                             0x408
33  #define RCU_PWR_GATING_SEQ1                             0x40c
34  #define RCU_PWR_GATING_CNTL                             0x410
35  #       define PWR_GATING_EN                            (1 << 0)
36  #       define RSVD_MASK                                (0x3 << 1)
37  #       define PCV(x)                                   ((x) << 3)
38  #       define PCV_MASK                                 (0x1f << 3)
39  #       define PCV_SHIFT                                3
40  #       define PCP(x)                                   ((x) << 8)
41  #       define PCP_MASK                                 (0xf << 8)
42  #       define PCP_SHIFT                                8
43  #       define RPW(x)                                   ((x) << 16)
44  #       define RPW_MASK                                 (0xf << 16)
45  #       define RPW_SHIFT                                16
46  #       define ID(x)                                    ((x) << 24)
47  #       define ID_MASK                                  (0xf << 24)
48  #       define ID_SHIFT                                 24
49  #       define PGS(x)                                   ((x) << 28)
50  #       define PGS_MASK                                 (0xf << 28)
51  #       define PGS_SHIFT                                28
52  
53  #define RCU_ALTVDDNB_NOTIFY                             0x430
54  #define RCU_LCLK_SCALING_CNTL                           0x434
55  #       define LCLK_SCALING_EN                          (1 << 0)
56  #       define LCLK_SCALING_TYPE                        (1 << 1)
57  #       define LCLK_SCALING_TIMER_PRESCALER(x)          ((x) << 4)
58  #       define LCLK_SCALING_TIMER_PRESCALER_MASK        (0xf << 4)
59  #       define LCLK_SCALING_TIMER_PRESCALER_SHIFT       4
60  #       define LCLK_SCALING_TIMER_PERIOD(x)             ((x) << 16)
61  #       define LCLK_SCALING_TIMER_PERIOD_MASK           (0xf << 16)
62  #       define LCLK_SCALING_TIMER_PERIOD_SHIFT          16
63  
64  #define RCU_PWR_GATING_CNTL_2                           0x4a0
65  #       define MPPU(x)                                  ((x) << 0)
66  #       define MPPU_MASK                                (0xffff << 0)
67  #       define MPPU_SHIFT                               0
68  #       define MPPD(x)                                  ((x) << 16)
69  #       define MPPD_MASK                                (0xffff << 16)
70  #       define MPPD_SHIFT                               16
71  #define RCU_PWR_GATING_CNTL_3                           0x4a4
72  #       define DPPU(x)                                  ((x) << 0)
73  #       define DPPU_MASK                                (0xffff << 0)
74  #       define DPPU_SHIFT                               0
75  #       define DPPD(x)                                  ((x) << 16)
76  #       define DPPD_MASK                                (0xffff << 16)
77  #       define DPPD_SHIFT                               16
78  #define RCU_PWR_GATING_CNTL_4                           0x4a8
79  #       define RT(x)                                    ((x) << 0)
80  #       define RT_MASK                                  (0xffff << 0)
81  #       define RT_SHIFT                                 0
82  #       define IT(x)                                    ((x) << 16)
83  #       define IT_MASK                                  (0xffff << 16)
84  #       define IT_SHIFT                                 16
85  
86  /* yes these two have the same address */
87  #define RCU_PWR_GATING_CNTL_5                           0x504
88  #define RCU_GPU_BOOST_DISABLE                           0x508
89  
90  #define MCU_M3ARB_INDEX                                 0x504
91  #define MCU_M3ARB_PARAMS                                0x508
92  
93  #define RCU_GNB_PWR_REP_TIMER_CNTL                      0x50C
94  
95  #define RCU_SclkDpmTdpLimit01                           0x514
96  #define RCU_SclkDpmTdpLimit23                           0x518
97  #define RCU_SclkDpmTdpLimit47                           0x51C
98  #define RCU_SclkDpmTdpLimitPG                           0x520
99  
100  #define GNB_TDP_LIMIT                                   0x540
101  #define RCU_BOOST_MARGIN                                0x544
102  #define RCU_THROTTLE_MARGIN                             0x548
103  
104  #define SMU_PCIE_PG_ARGS                                0x58C
105  #define SMU_PCIE_PG_ARGS_2                              0x598
106  #define SMU_PCIE_PG_ARGS_3                              0x59C
107  
108  /* mmio */
109  #define RCU_STATUS                                      0x11c
110  #       define GMC_PWR_GATER_BUSY                       (1 << 8)
111  #       define GFX_PWR_GATER_BUSY                       (1 << 9)
112  #       define UVD_PWR_GATER_BUSY                       (1 << 10)
113  #       define PCIE_PWR_GATER_BUSY                      (1 << 11)
114  #       define GMC_PWR_GATER_STATE                      (1 << 12)
115  #       define GFX_PWR_GATER_STATE                      (1 << 13)
116  #       define UVD_PWR_GATER_STATE                      (1 << 14)
117  #       define PCIE_PWR_GATER_STATE                     (1 << 15)
118  #       define GFX1_PWR_GATER_BUSY                      (1 << 16)
119  #       define GFX2_PWR_GATER_BUSY                      (1 << 17)
120  #       define GFX1_PWR_GATER_STATE                     (1 << 18)
121  #       define GFX2_PWR_GATER_STATE                     (1 << 19)
122  
123  #define GFX_INT_REQ                                     0x120
124  #       define INT_REQ                                  (1 << 0)
125  #       define SERV_INDEX(x)                            ((x) << 1)
126  #       define SERV_INDEX_MASK                          (0xff << 1)
127  #       define SERV_INDEX_SHIFT                         1
128  #define GFX_INT_STATUS                                  0x124
129  #       define INT_ACK                                  (1 << 0)
130  #       define INT_DONE                                 (1 << 1)
131  
132  #define CG_SCLK_CNTL                                    0x600
133  #       define SCLK_DIVIDER(x)                          ((x) << 0)
134  #       define SCLK_DIVIDER_MASK                        (0x7f << 0)
135  #       define SCLK_DIVIDER_SHIFT                       0
136  #define CG_SCLK_STATUS                                  0x604
137  #       define SCLK_OVERCLK_DETECT                      (1 << 2)
138  
139  #define CG_DCLK_CNTL                                    0x610
140  #       define DCLK_DIVIDER_MASK                        0x7f
141  #       define DCLK_DIR_CNTL_EN                         (1 << 8)
142  #define CG_DCLK_STATUS                                  0x614
143  #       define DCLK_STATUS                              (1 << 0)
144  #define CG_VCLK_CNTL                                    0x618
145  #       define VCLK_DIVIDER_MASK                        0x7f
146  #       define VCLK_DIR_CNTL_EN                         (1 << 8)
147  #define CG_VCLK_STATUS                                  0x61c
148  
149  #define GENERAL_PWRMGT                                  0x63c
150  #       define STATIC_PM_EN                             (1 << 1)
151  
152  #define SCLK_PWRMGT_CNTL                                0x644
153  #       define SCLK_PWRMGT_OFF                          (1 << 0)
154  #       define SCLK_LOW_D1                              (1 << 1)
155  #       define FIR_RESET                                (1 << 4)
156  #       define FIR_FORCE_TREND_SEL                      (1 << 5)
157  #       define FIR_TREND_MODE                           (1 << 6)
158  #       define DYN_GFX_CLK_OFF_EN                       (1 << 7)
159  #       define GFX_CLK_FORCE_ON                         (1 << 8)
160  #       define GFX_CLK_REQUEST_OFF                      (1 << 9)
161  #       define GFX_CLK_FORCE_OFF                        (1 << 10)
162  #       define GFX_CLK_OFF_ACPI_D1                      (1 << 11)
163  #       define GFX_CLK_OFF_ACPI_D2                      (1 << 12)
164  #       define GFX_CLK_OFF_ACPI_D3                      (1 << 13)
165  #       define GFX_VOLTAGE_CHANGE_EN                    (1 << 16)
166  #       define GFX_VOLTAGE_CHANGE_MODE                  (1 << 17)
167  
168  #define TARGET_AND_CURRENT_PROFILE_INDEX                0x66c
169  #       define TARG_SCLK_INDEX(x)                       ((x) << 6)
170  #       define TARG_SCLK_INDEX_MASK                     (0x7 << 6)
171  #       define TARG_SCLK_INDEX_SHIFT                    6
172  #       define CURR_SCLK_INDEX(x)                       ((x) << 9)
173  #       define CURR_SCLK_INDEX_MASK                     (0x7 << 9)
174  #       define CURR_SCLK_INDEX_SHIFT                    9
175  #       define TARG_INDEX(x)                            ((x) << 12)
176  #       define TARG_INDEX_MASK                          (0x7 << 12)
177  #       define TARG_INDEX_SHIFT                         12
178  #       define CURR_INDEX(x)                            ((x) << 15)
179  #       define CURR_INDEX_MASK                          (0x7 << 15)
180  #       define CURR_INDEX_SHIFT                         15
181  
182  #define CG_SCLK_DPM_CTRL                                0x684
183  #       define SCLK_FSTATE_0_DIV(x)                     ((x) << 0)
184  #       define SCLK_FSTATE_0_DIV_MASK                   (0x7f << 0)
185  #       define SCLK_FSTATE_0_DIV_SHIFT                  0
186  #       define SCLK_FSTATE_0_VLD                        (1 << 7)
187  #       define SCLK_FSTATE_1_DIV(x)                     ((x) << 8)
188  #       define SCLK_FSTATE_1_DIV_MASK                   (0x7f << 8)
189  #       define SCLK_FSTATE_1_DIV_SHIFT                  8
190  #       define SCLK_FSTATE_1_VLD                        (1 << 15)
191  #       define SCLK_FSTATE_2_DIV(x)                     ((x) << 16)
192  #       define SCLK_FSTATE_2_DIV_MASK                   (0x7f << 16)
193  #       define SCLK_FSTATE_2_DIV_SHIFT                  16
194  #       define SCLK_FSTATE_2_VLD                        (1 << 23)
195  #       define SCLK_FSTATE_3_DIV(x)                     ((x) << 24)
196  #       define SCLK_FSTATE_3_DIV_MASK                   (0x7f << 24)
197  #       define SCLK_FSTATE_3_DIV_SHIFT                  24
198  #       define SCLK_FSTATE_3_VLD                        (1 << 31)
199  #define CG_SCLK_DPM_CTRL_2                              0x688
200  #define CG_GCOOR                                        0x68c
201  #       define PHC(x)                                   ((x) << 0)
202  #       define PHC_MASK                                 (0x1f << 0)
203  #       define PHC_SHIFT                                0
204  #       define SDC(x)                                   ((x) << 9)
205  #       define SDC_MASK                                 (0x3ff << 9)
206  #       define SDC_SHIFT                                9
207  #       define SU(x)                                    ((x) << 23)
208  #       define SU_MASK                                  (0xf << 23)
209  #       define SU_SHIFT                                 23
210  #       define DIV_ID(x)                                ((x) << 28)
211  #       define DIV_ID_MASK                              (0x7 << 28)
212  #       define DIV_ID_SHIFT                             28
213  
214  #define CG_FTV                                          0x690
215  #define CG_FFCT_0                                       0x694
216  #       define UTC_0(x)                                 ((x) << 0)
217  #       define UTC_0_MASK                               (0x3ff << 0)
218  #       define UTC_0_SHIFT                              0
219  #       define DTC_0(x)                                 ((x) << 10)
220  #       define DTC_0_MASK                               (0x3ff << 10)
221  #       define DTC_0_SHIFT                              10
222  
223  #define CG_GIT                                          0x6d8
224  #       define CG_GICST(x)                              ((x) << 0)
225  #       define CG_GICST_MASK                            (0xffff << 0)
226  #       define CG_GICST_SHIFT                           0
227  #       define CG_GIPOT(x)                              ((x) << 16)
228  #       define CG_GIPOT_MASK                            (0xffff << 16)
229  #       define CG_GIPOT_SHIFT                           16
230  
231  #define CG_SCLK_DPM_CTRL_3                              0x6e0
232  #       define FORCE_SCLK_STATE(x)                      ((x) << 0)
233  #       define FORCE_SCLK_STATE_MASK                    (0x7 << 0)
234  #       define FORCE_SCLK_STATE_SHIFT                   0
235  #       define FORCE_SCLK_STATE_EN                      (1 << 3)
236  #       define GNB_TT(x)                                ((x) << 8)
237  #       define GNB_TT_MASK                              (0xff << 8)
238  #       define GNB_TT_SHIFT                             8
239  #       define GNB_THERMTHRO_MASK                       (1 << 16)
240  #       define CNB_THERMTHRO_MASK_SCLK                  (1 << 17)
241  #       define DPM_SCLK_ENABLE                          (1 << 18)
242  #       define GNB_SLOW_FSTATE_0_MASK                   (1 << 23)
243  #       define GNB_SLOW_FSTATE_0_SHIFT                  23
244  #       define FORCE_NB_PSTATE_1                        (1 << 31)
245  
246  #define CG_SSP                                          0x6e8
247  #       define SST(x)                                   ((x) << 0)
248  #       define SST_MASK                                 (0xffff << 0)
249  #       define SST_SHIFT                                0
250  #       define SSTU(x)                                  ((x) << 16)
251  #       define SSTU_MASK                                (0xffff << 16)
252  #       define SSTU_SHIFT                               16
253  
254  #define CG_ACPI_CNTL                                    0x70c
255  #       define SCLK_ACPI_DIV(x)                         ((x) << 0)
256  #       define SCLK_ACPI_DIV_MASK                       (0x7f << 0)
257  #       define SCLK_ACPI_DIV_SHIFT                      0
258  
259  #define CG_SCLK_DPM_CTRL_4                              0x71c
260  #       define DC_HDC(x)                                ((x) << 14)
261  #       define DC_HDC_MASK                              (0x3fff << 14)
262  #       define DC_HDC_SHIFT                             14
263  #       define DC_HU(x)                                 ((x) << 28)
264  #       define DC_HU_MASK                               (0xf << 28)
265  #       define DC_HU_SHIFT                              28
266  #define CG_SCLK_DPM_CTRL_5                              0x720
267  #       define SCLK_FSTATE_BOOTUP(x)                    ((x) << 0)
268  #       define SCLK_FSTATE_BOOTUP_MASK                  (0x7 << 0)
269  #       define SCLK_FSTATE_BOOTUP_SHIFT                 0
270  #       define TT_TP(x)                                 ((x) << 3)
271  #       define TT_TP_MASK                               (0xffff << 3)
272  #       define TT_TP_SHIFT                              3
273  #       define TT_TU(x)                                 ((x) << 19)
274  #       define TT_TU_MASK                               (0xff << 19)
275  #       define TT_TU_SHIFT                              19
276  #define CG_SCLK_DPM_CTRL_6                              0x724
277  #define CG_AT_0                                         0x728
278  #       define CG_R(x)                                  ((x) << 0)
279  #       define CG_R_MASK                                (0xffff << 0)
280  #       define CG_R_SHIFT                               0
281  #       define CG_L(x)                                  ((x) << 16)
282  #       define CG_L_MASK                                (0xffff << 16)
283  #       define CG_L_SHIFT                               16
284  #define CG_AT_1                                         0x72c
285  #define CG_AT_2                                         0x730
286  #define	CG_THERMAL_INT					0x734
287  #define		DIG_THERM_INTH(x)			((x) << 8)
288  #define		DIG_THERM_INTH_MASK			0x0000FF00
289  #define		DIG_THERM_INTH_SHIFT			8
290  #define		DIG_THERM_INTL(x)			((x) << 16)
291  #define		DIG_THERM_INTL_MASK			0x00FF0000
292  #define		DIG_THERM_INTL_SHIFT			16
293  #define 	THERM_INT_MASK_HIGH			(1 << 24)
294  #define 	THERM_INT_MASK_LOW			(1 << 25)
295  #define CG_AT_3                                         0x738
296  #define CG_AT_4                                         0x73c
297  #define CG_AT_5                                         0x740
298  #define CG_AT_6                                         0x744
299  #define CG_AT_7                                         0x748
300  
301  #define CG_BSP_0                                        0x750
302  #       define BSP(x)                                   ((x) << 0)
303  #       define BSP_MASK                                 (0xffff << 0)
304  #       define BSP_SHIFT                                0
305  #       define BSU(x)                                   ((x) << 16)
306  #       define BSU_MASK                                 (0xf << 16)
307  #       define BSU_SHIFT                                16
308  
309  #define CG_CG_VOLTAGE_CNTL                              0x770
310  #       define REQ                                      (1 << 0)
311  #       define LEVEL(x)                                 ((x) << 1)
312  #       define LEVEL_MASK                               (0x3 << 1)
313  #       define LEVEL_SHIFT                              1
314  #       define CG_VOLTAGE_EN                            (1 << 3)
315  #       define FORCE                                    (1 << 4)
316  #       define PERIOD(x)                                ((x) << 8)
317  #       define PERIOD_MASK                              (0xffff << 8)
318  #       define PERIOD_SHIFT                             8
319  #       define UNIT(x)                                  ((x) << 24)
320  #       define UNIT_MASK                                (0xf << 24)
321  #       define UNIT_SHIFT                               24
322  
323  #define CG_ACPI_VOLTAGE_CNTL                            0x780
324  #       define ACPI_VOLTAGE_EN                          (1 << 8)
325  
326  #define CG_DPM_VOLTAGE_CNTL                             0x788
327  #       define DPM_STATE0_LEVEL_MASK                    (0x3 << 0)
328  #       define DPM_STATE0_LEVEL_SHIFT                   0
329  #       define DPM_VOLTAGE_EN                           (1 << 16)
330  
331  #define CG_PWR_GATING_CNTL                              0x7ac
332  #       define DYN_PWR_DOWN_EN                          (1 << 0)
333  #       define ACPI_PWR_DOWN_EN                         (1 << 1)
334  #       define GFX_CLK_OFF_PWR_DOWN_EN                  (1 << 2)
335  #       define IOC_DISGPU_PWR_DOWN_EN                   (1 << 3)
336  #       define FORCE_POWR_ON                            (1 << 4)
337  #       define PGP(x)                                   ((x) << 8)
338  #       define PGP_MASK                                 (0xffff << 8)
339  #       define PGP_SHIFT                                8
340  #       define PGU(x)                                   ((x) << 24)
341  #       define PGU_MASK                                 (0xf << 24)
342  #       define PGU_SHIFT                                24
343  
344  #define CG_CGTT_LOCAL_0                                 0x7d0
345  #define CG_CGTT_LOCAL_1                                 0x7d4
346  
347  #define DEEP_SLEEP_CNTL                                 0x818
348  #       define R_DIS                                    (1 << 3)
349  #       define HS(x)                                    ((x) << 4)
350  #       define HS_MASK                                  (0xfff << 4)
351  #       define HS_SHIFT                                 4
352  #       define ENABLE_DS                                (1 << 31)
353  #define DEEP_SLEEP_CNTL2                                0x81c
354  #       define LB_UFP_EN                                (1 << 0)
355  #       define INOUT_C(x)                               ((x) << 4)
356  #       define INOUT_C_MASK                             (0xff << 4)
357  #       define INOUT_C_SHIFT                            4
358  
359  #define CG_SCRATCH2                                     0x824
360  
361  #define CG_SCLK_DPM_CTRL_11                             0x830
362  
363  #define HW_REV   					0x5564
364  #       define ATI_REV_ID_MASK                          (0xf << 28)
365  #       define ATI_REV_ID_SHIFT                         28
366  /* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */
367  
368  #define DOUT_SCRATCH3   				0x611c
369  
370  #define GB_ADDR_CONFIG  				0x98f8
371  
372  #endif
373