1 /**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8 /*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32 #include <drm/drmP.h>
33 #include <drm/radeon_drm.h>
34 #include "radeon_drv.h"
35
36 #include <drm/drm_pciids.h>
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/vga_switcheroo.h>
41 #include <linux/compat.h>
42 #include <drm/drm_gem.h>
43 #include <drm/drm_fb_helper.h>
44
45 #include <drm/drm_crtc_helper.h>
46
47 /*
48 * KMS wrapper.
49 * - 2.0.0 - initial interface
50 * - 2.1.0 - add square tiling interface
51 * - 2.2.0 - add r6xx/r7xx const buffer support
52 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
53 * - 2.4.0 - add crtc id query
54 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
55 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
56 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
57 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
58 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
59 * 2.10.0 - fusion 2D tiling
60 * 2.11.0 - backend map, initial compute support for the CS checker
61 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
62 * 2.13.0 - virtual memory support, streamout
63 * 2.14.0 - add evergreen tiling informations
64 * 2.15.0 - add max_pipes query
65 * 2.16.0 - fix evergreen 2D tiled surface calculation
66 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
67 * 2.18.0 - r600-eg: allow "invalid" DB formats
68 * 2.19.0 - r600-eg: MSAA textures
69 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
70 * 2.21.0 - r600-r700: FMASK and CMASK
71 * 2.22.0 - r600 only: RESOLVE_BOX allowed
72 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
73 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
74 * 2.25.0 - eg+: new info request for num SE and num SH
75 * 2.26.0 - r600-eg: fix htile size computation
76 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
77 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
78 * 2.29.0 - R500 FP16 color clear registers
79 * 2.30.0 - fix for FMASK texturing
80 * 2.31.0 - Add fastfb support for rs690
81 * 2.32.0 - new info request for rings working
82 * 2.33.0 - Add SI tiling mode array query
83 * 2.34.0 - Add CIK tiling mode array query
84 * 2.35.0 - Add CIK macrotile mode array query
85 * 2.36.0 - Fix CIK DCE tiling setup
86 * 2.37.0 - allow GS ring setup on r6xx/r7xx
87 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
88 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
89 * 2.39.0 - Add INFO query for number of active CUs
90 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
91 * CS to GPU on >= r600
92 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
93 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
94 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
95 * 2.44.0 - SET_APPEND_CNT packet3 support
96 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
97 * 2.46.0 - Add PFP_SYNC_ME support on evergreen
98 * 2.47.0 - Add UVD_NO_OP register support
99 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
100 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
101 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL)
102 */
103 #define KMS_DRIVER_MAJOR 2
104 #define KMS_DRIVER_MINOR 50
105 #define KMS_DRIVER_PATCHLEVEL 0
106 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
107 void radeon_driver_unload_kms(struct drm_device *dev);
108 void radeon_driver_lastclose_kms(struct drm_device *dev);
109 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
110 void radeon_driver_postclose_kms(struct drm_device *dev,
111 struct drm_file *file_priv);
112 int radeon_suspend_kms(struct drm_device *dev, bool suspend,
113 bool fbcon, bool freeze);
114 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
115 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
116 int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
117 void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
118 void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
119 int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
120 void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
121 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
122 void radeon_gem_object_free(struct drm_gem_object *obj);
123 int radeon_gem_object_open(struct drm_gem_object *obj,
124 struct drm_file *file_priv);
125 void radeon_gem_object_close(struct drm_gem_object *obj,
126 struct drm_file *file_priv);
127 struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
128 struct drm_gem_object *gobj,
129 int flags);
130 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
131 unsigned int flags, int *vpos, int *hpos,
132 ktime_t *stime, ktime_t *etime,
133 const struct drm_display_mode *mode);
134 extern bool radeon_is_px(struct drm_device *dev);
135 extern const struct drm_ioctl_desc radeon_ioctls_kms[];
136 extern int radeon_max_kms_ioctl;
137 int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
138 int radeon_mode_dumb_mmap(struct drm_file *filp,
139 struct drm_device *dev,
140 uint32_t handle, uint64_t *offset_p);
141 int radeon_mode_dumb_create(struct drm_file *file_priv,
142 struct drm_device *dev,
143 struct drm_mode_create_dumb *args);
144 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
145 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
146 struct dma_buf_attachment *,
147 struct sg_table *sg);
148 int radeon_gem_prime_pin(struct drm_gem_object *obj);
149 void radeon_gem_prime_unpin(struct drm_gem_object *obj);
150 struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
151 void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
152 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
153
154 /* atpx handler */
155 #if defined(CONFIG_VGA_SWITCHEROO)
156 void radeon_register_atpx_handler(void);
157 void radeon_unregister_atpx_handler(void);
158 bool radeon_has_atpx_dgpu_power_cntl(void);
159 bool radeon_is_atpx_hybrid(void);
160 #else
radeon_register_atpx_handler(void)161 static inline void radeon_register_atpx_handler(void) {}
radeon_unregister_atpx_handler(void)162 static inline void radeon_unregister_atpx_handler(void) {}
radeon_has_atpx_dgpu_power_cntl(void)163 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
radeon_is_atpx_hybrid(void)164 static inline bool radeon_is_atpx_hybrid(void) { return false; }
165 #endif
166
167 int radeon_no_wb;
168 int radeon_modeset = -1;
169 int radeon_dynclks = -1;
170 int radeon_r4xx_atom = 0;
171 #ifdef __powerpc__
172 /* Default to PCI on PowerPC (fdo #95017) */
173 int radeon_agpmode = -1;
174 #else
175 int radeon_agpmode = 0;
176 #endif
177 int radeon_vram_limit = 0;
178 int radeon_gart_size = -1; /* auto */
179 int radeon_benchmarking = 0;
180 int radeon_testing = 0;
181 int radeon_connector_table = 0;
182 int radeon_tv = 1;
183 int radeon_audio = -1;
184 int radeon_disp_priority = 0;
185 int radeon_hw_i2c = 0;
186 int radeon_pcie_gen2 = -1;
187 int radeon_msi = -1;
188 int radeon_lockup_timeout = 10000;
189 int radeon_fastfb = 0;
190 int radeon_dpm = -1;
191 int radeon_aspm = -1;
192 int radeon_runtime_pm = -1;
193 int radeon_hard_reset = 0;
194 int radeon_vm_size = 8;
195 int radeon_vm_block_size = -1;
196 int radeon_deep_color = 0;
197 int radeon_use_pflipirq = 2;
198 int radeon_bapm = -1;
199 int radeon_backlight = -1;
200 int radeon_auxch = -1;
201 int radeon_mst = 0;
202 int radeon_uvd = 1;
203 int radeon_vce = 1;
204
205 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
206 module_param_named(no_wb, radeon_no_wb, int, 0444);
207
208 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
209 module_param_named(modeset, radeon_modeset, int, 0400);
210
211 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
212 module_param_named(dynclks, radeon_dynclks, int, 0444);
213
214 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
215 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
216
217 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
218 module_param_named(vramlimit, radeon_vram_limit, int, 0600);
219
220 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
221 module_param_named(agpmode, radeon_agpmode, int, 0444);
222
223 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
224 module_param_named(gartsize, radeon_gart_size, int, 0600);
225
226 MODULE_PARM_DESC(benchmark, "Run benchmark");
227 module_param_named(benchmark, radeon_benchmarking, int, 0444);
228
229 MODULE_PARM_DESC(test, "Run tests");
230 module_param_named(test, radeon_testing, int, 0444);
231
232 MODULE_PARM_DESC(connector_table, "Force connector table");
233 module_param_named(connector_table, radeon_connector_table, int, 0444);
234
235 MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
236 module_param_named(tv, radeon_tv, int, 0444);
237
238 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
239 module_param_named(audio, radeon_audio, int, 0444);
240
241 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
242 module_param_named(disp_priority, radeon_disp_priority, int, 0444);
243
244 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
245 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
246
247 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
248 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
249
250 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
251 module_param_named(msi, radeon_msi, int, 0444);
252
253 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
254 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
255
256 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
257 module_param_named(fastfb, radeon_fastfb, int, 0444);
258
259 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
260 module_param_named(dpm, radeon_dpm, int, 0444);
261
262 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
263 module_param_named(aspm, radeon_aspm, int, 0444);
264
265 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
266 module_param_named(runpm, radeon_runtime_pm, int, 0444);
267
268 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
269 module_param_named(hard_reset, radeon_hard_reset, int, 0444);
270
271 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
272 module_param_named(vm_size, radeon_vm_size, int, 0444);
273
274 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
275 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
276
277 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
278 module_param_named(deep_color, radeon_deep_color, int, 0444);
279
280 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
281 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
282
283 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
284 module_param_named(bapm, radeon_bapm, int, 0444);
285
286 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
287 module_param_named(backlight, radeon_backlight, int, 0444);
288
289 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
290 module_param_named(auxch, radeon_auxch, int, 0444);
291
292 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
293 module_param_named(mst, radeon_mst, int, 0444);
294
295 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
296 module_param_named(uvd, radeon_uvd, int, 0444);
297
298 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
299 module_param_named(vce, radeon_vce, int, 0444);
300
301 int radeon_si_support = 1;
302 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
303 module_param_named(si_support, radeon_si_support, int, 0444);
304
305 int radeon_cik_support = 1;
306 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
307 module_param_named(cik_support, radeon_cik_support, int, 0444);
308
309 static struct pci_device_id pciidlist[] = {
310 radeon_PCI_IDS
311 };
312
313 MODULE_DEVICE_TABLE(pci, pciidlist);
314
315 static struct drm_driver kms_driver;
316
317 bool radeon_device_is_virtual(void);
318
radeon_kick_out_firmware_fb(struct pci_dev * pdev)319 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
320 {
321 struct apertures_struct *ap;
322 bool primary = false;
323
324 ap = alloc_apertures(1);
325 if (!ap)
326 return -ENOMEM;
327
328 ap->ranges[0].base = pci_resource_start(pdev, 0);
329 ap->ranges[0].size = pci_resource_len(pdev, 0);
330
331 #ifdef CONFIG_X86
332 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
333 #endif
334 drm_fb_helper_remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
335 kfree(ap);
336
337 return 0;
338 }
339
radeon_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)340 static int radeon_pci_probe(struct pci_dev *pdev,
341 const struct pci_device_id *ent)
342 {
343 int ret;
344
345 if (vga_switcheroo_client_probe_defer(pdev))
346 return -EPROBE_DEFER;
347
348 /* Get rid of things like offb */
349 ret = radeon_kick_out_firmware_fb(pdev);
350 if (ret)
351 return ret;
352
353 return drm_get_pci_dev(pdev, ent, &kms_driver);
354 }
355
356 static void
radeon_pci_remove(struct pci_dev * pdev)357 radeon_pci_remove(struct pci_dev *pdev)
358 {
359 struct drm_device *dev = pci_get_drvdata(pdev);
360
361 drm_put_dev(dev);
362 }
363
364 static void
radeon_pci_shutdown(struct pci_dev * pdev)365 radeon_pci_shutdown(struct pci_dev *pdev)
366 {
367 /* if we are running in a VM, make sure the device
368 * torn down properly on reboot/shutdown
369 */
370 if (radeon_device_is_virtual())
371 radeon_pci_remove(pdev);
372 }
373
radeon_pmops_suspend(struct device * dev)374 static int radeon_pmops_suspend(struct device *dev)
375 {
376 struct pci_dev *pdev = to_pci_dev(dev);
377 struct drm_device *drm_dev = pci_get_drvdata(pdev);
378 return radeon_suspend_kms(drm_dev, true, true, false);
379 }
380
radeon_pmops_resume(struct device * dev)381 static int radeon_pmops_resume(struct device *dev)
382 {
383 struct pci_dev *pdev = to_pci_dev(dev);
384 struct drm_device *drm_dev = pci_get_drvdata(pdev);
385
386 /* GPU comes up enabled by the bios on resume */
387 if (radeon_is_px(drm_dev)) {
388 pm_runtime_disable(dev);
389 pm_runtime_set_active(dev);
390 pm_runtime_enable(dev);
391 }
392
393 return radeon_resume_kms(drm_dev, true, true);
394 }
395
radeon_pmops_freeze(struct device * dev)396 static int radeon_pmops_freeze(struct device *dev)
397 {
398 struct pci_dev *pdev = to_pci_dev(dev);
399 struct drm_device *drm_dev = pci_get_drvdata(pdev);
400 return radeon_suspend_kms(drm_dev, false, true, true);
401 }
402
radeon_pmops_thaw(struct device * dev)403 static int radeon_pmops_thaw(struct device *dev)
404 {
405 struct pci_dev *pdev = to_pci_dev(dev);
406 struct drm_device *drm_dev = pci_get_drvdata(pdev);
407 return radeon_resume_kms(drm_dev, false, true);
408 }
409
radeon_pmops_runtime_suspend(struct device * dev)410 static int radeon_pmops_runtime_suspend(struct device *dev)
411 {
412 struct pci_dev *pdev = to_pci_dev(dev);
413 struct drm_device *drm_dev = pci_get_drvdata(pdev);
414 int ret;
415
416 if (!radeon_is_px(drm_dev)) {
417 pm_runtime_forbid(dev);
418 return -EBUSY;
419 }
420
421 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
422 drm_kms_helper_poll_disable(drm_dev);
423
424 ret = radeon_suspend_kms(drm_dev, false, false, false);
425 pci_save_state(pdev);
426 pci_disable_device(pdev);
427 pci_ignore_hotplug(pdev);
428 if (radeon_is_atpx_hybrid())
429 pci_set_power_state(pdev, PCI_D3cold);
430 else if (!radeon_has_atpx_dgpu_power_cntl())
431 pci_set_power_state(pdev, PCI_D3hot);
432 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
433
434 return 0;
435 }
436
radeon_pmops_runtime_resume(struct device * dev)437 static int radeon_pmops_runtime_resume(struct device *dev)
438 {
439 struct pci_dev *pdev = to_pci_dev(dev);
440 struct drm_device *drm_dev = pci_get_drvdata(pdev);
441 int ret;
442
443 if (!radeon_is_px(drm_dev))
444 return -EINVAL;
445
446 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
447
448 if (radeon_is_atpx_hybrid() ||
449 !radeon_has_atpx_dgpu_power_cntl())
450 pci_set_power_state(pdev, PCI_D0);
451 pci_restore_state(pdev);
452 ret = pci_enable_device(pdev);
453 if (ret)
454 return ret;
455 pci_set_master(pdev);
456
457 ret = radeon_resume_kms(drm_dev, false, false);
458 drm_kms_helper_poll_enable(drm_dev);
459 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
460 return 0;
461 }
462
radeon_pmops_runtime_idle(struct device * dev)463 static int radeon_pmops_runtime_idle(struct device *dev)
464 {
465 struct pci_dev *pdev = to_pci_dev(dev);
466 struct drm_device *drm_dev = pci_get_drvdata(pdev);
467 struct drm_crtc *crtc;
468
469 if (!radeon_is_px(drm_dev)) {
470 pm_runtime_forbid(dev);
471 return -EBUSY;
472 }
473
474 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
475 if (crtc->enabled) {
476 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
477 return -EBUSY;
478 }
479 }
480
481 pm_runtime_mark_last_busy(dev);
482 pm_runtime_autosuspend(dev);
483 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
484 return 1;
485 }
486
radeon_drm_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)487 long radeon_drm_ioctl(struct file *filp,
488 unsigned int cmd, unsigned long arg)
489 {
490 struct drm_file *file_priv = filp->private_data;
491 struct drm_device *dev;
492 long ret;
493 dev = file_priv->minor->dev;
494 ret = pm_runtime_get_sync(dev->dev);
495 if (ret < 0)
496 return ret;
497
498 ret = drm_ioctl(filp, cmd, arg);
499
500 pm_runtime_mark_last_busy(dev->dev);
501 pm_runtime_put_autosuspend(dev->dev);
502 return ret;
503 }
504
505 #ifdef CONFIG_COMPAT
radeon_kms_compat_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)506 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
507 {
508 unsigned int nr = DRM_IOCTL_NR(cmd);
509 int ret;
510
511 if (nr < DRM_COMMAND_BASE)
512 return drm_compat_ioctl(filp, cmd, arg);
513
514 ret = radeon_drm_ioctl(filp, cmd, arg);
515
516 return ret;
517 }
518 #endif
519
520 static const struct dev_pm_ops radeon_pm_ops = {
521 .suspend = radeon_pmops_suspend,
522 .resume = radeon_pmops_resume,
523 .freeze = radeon_pmops_freeze,
524 .thaw = radeon_pmops_thaw,
525 .poweroff = radeon_pmops_freeze,
526 .restore = radeon_pmops_resume,
527 .runtime_suspend = radeon_pmops_runtime_suspend,
528 .runtime_resume = radeon_pmops_runtime_resume,
529 .runtime_idle = radeon_pmops_runtime_idle,
530 };
531
532 static const struct file_operations radeon_driver_kms_fops = {
533 .owner = THIS_MODULE,
534 .open = drm_open,
535 .release = drm_release,
536 .unlocked_ioctl = radeon_drm_ioctl,
537 .mmap = radeon_mmap,
538 .poll = drm_poll,
539 .read = drm_read,
540 #ifdef CONFIG_COMPAT
541 .compat_ioctl = radeon_kms_compat_ioctl,
542 #endif
543 };
544
545 static bool
radeon_get_crtc_scanout_position(struct drm_device * dev,unsigned int pipe,bool in_vblank_irq,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)546 radeon_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
547 bool in_vblank_irq, int *vpos, int *hpos,
548 ktime_t *stime, ktime_t *etime,
549 const struct drm_display_mode *mode)
550 {
551 return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
552 stime, etime, mode);
553 }
554
555 static struct drm_driver kms_driver = {
556 .driver_features =
557 DRIVER_USE_AGP |
558 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
559 DRIVER_PRIME | DRIVER_RENDER,
560 .load = radeon_driver_load_kms,
561 .open = radeon_driver_open_kms,
562 .postclose = radeon_driver_postclose_kms,
563 .lastclose = radeon_driver_lastclose_kms,
564 .unload = radeon_driver_unload_kms,
565 .get_vblank_counter = radeon_get_vblank_counter_kms,
566 .enable_vblank = radeon_enable_vblank_kms,
567 .disable_vblank = radeon_disable_vblank_kms,
568 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
569 .get_scanout_position = radeon_get_crtc_scanout_position,
570 .irq_preinstall = radeon_driver_irq_preinstall_kms,
571 .irq_postinstall = radeon_driver_irq_postinstall_kms,
572 .irq_uninstall = radeon_driver_irq_uninstall_kms,
573 .irq_handler = radeon_driver_irq_handler_kms,
574 .ioctls = radeon_ioctls_kms,
575 .gem_free_object_unlocked = radeon_gem_object_free,
576 .gem_open_object = radeon_gem_object_open,
577 .gem_close_object = radeon_gem_object_close,
578 .dumb_create = radeon_mode_dumb_create,
579 .dumb_map_offset = radeon_mode_dumb_mmap,
580 .fops = &radeon_driver_kms_fops,
581
582 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
583 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
584 .gem_prime_export = radeon_gem_prime_export,
585 .gem_prime_import = drm_gem_prime_import,
586 .gem_prime_pin = radeon_gem_prime_pin,
587 .gem_prime_unpin = radeon_gem_prime_unpin,
588 .gem_prime_res_obj = radeon_gem_prime_res_obj,
589 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
590 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
591 .gem_prime_vmap = radeon_gem_prime_vmap,
592 .gem_prime_vunmap = radeon_gem_prime_vunmap,
593
594 .name = DRIVER_NAME,
595 .desc = DRIVER_DESC,
596 .date = DRIVER_DATE,
597 .major = KMS_DRIVER_MAJOR,
598 .minor = KMS_DRIVER_MINOR,
599 .patchlevel = KMS_DRIVER_PATCHLEVEL,
600 };
601
602 static struct drm_driver *driver;
603 static struct pci_driver *pdriver;
604
605 static struct pci_driver radeon_kms_pci_driver = {
606 .name = DRIVER_NAME,
607 .id_table = pciidlist,
608 .probe = radeon_pci_probe,
609 .remove = radeon_pci_remove,
610 .shutdown = radeon_pci_shutdown,
611 .driver.pm = &radeon_pm_ops,
612 };
613
radeon_init(void)614 static int __init radeon_init(void)
615 {
616 if (vgacon_text_force() && radeon_modeset == -1) {
617 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
618 radeon_modeset = 0;
619 }
620 /* set to modesetting by default if not nomodeset */
621 if (radeon_modeset == -1)
622 radeon_modeset = 1;
623
624 if (radeon_modeset == 1) {
625 DRM_INFO("radeon kernel modesetting enabled.\n");
626 driver = &kms_driver;
627 pdriver = &radeon_kms_pci_driver;
628 driver->driver_features |= DRIVER_MODESET;
629 driver->num_ioctls = radeon_max_kms_ioctl;
630 radeon_register_atpx_handler();
631
632 } else {
633 DRM_ERROR("No UMS support in radeon module!\n");
634 return -EINVAL;
635 }
636
637 return pci_register_driver(pdriver);
638 }
639
radeon_exit(void)640 static void __exit radeon_exit(void)
641 {
642 pci_unregister_driver(pdriver);
643 radeon_unregister_atpx_handler();
644 }
645
646 module_init(radeon_init);
647 module_exit(radeon_exit);
648
649 MODULE_AUTHOR(DRIVER_AUTHOR);
650 MODULE_DESCRIPTION(DRIVER_DESC);
651 MODULE_LICENSE("GPL and additional rights");
652
