1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __X86_MCE_INTERNAL_H__
3 #define __X86_MCE_INTERNAL_H__
4
5 #include <linux/device.h>
6 #include <asm/mce.h>
7
8 enum severity_level {
9 MCE_NO_SEVERITY,
10 MCE_DEFERRED_SEVERITY,
11 MCE_UCNA_SEVERITY = MCE_DEFERRED_SEVERITY,
12 MCE_KEEP_SEVERITY,
13 MCE_SOME_SEVERITY,
14 MCE_AO_SEVERITY,
15 MCE_UC_SEVERITY,
16 MCE_AR_SEVERITY,
17 MCE_PANIC_SEVERITY,
18 };
19
20 extern struct blocking_notifier_head x86_mce_decoder_chain;
21
22 #define ATTR_LEN 16
23 #define INITIAL_CHECK_INTERVAL 5 * 60 /* 5 minutes */
24
25 /* One object for each MCE bank, shared by all CPUs */
26 struct mce_bank {
27 u64 ctl; /* subevents to enable */
28 unsigned char init; /* initialise bank? */
29 struct device_attribute attr; /* device attribute */
30 char attrname[ATTR_LEN]; /* attribute name */
31 };
32
33 struct mce_evt_llist {
34 struct llist_node llnode;
35 struct mce mce;
36 };
37
38 void mce_gen_pool_process(struct work_struct *__unused);
39 bool mce_gen_pool_empty(void);
40 int mce_gen_pool_add(struct mce *mce);
41 int mce_gen_pool_init(void);
42 struct llist_node *mce_gen_pool_prepare_records(void);
43
44 extern int (*mce_severity)(struct mce *a, int tolerant, char **msg, bool is_excp);
45 struct dentry *mce_get_debugfs_dir(void);
46
47 extern struct mce_bank *mce_banks;
48 extern mce_banks_t mce_banks_ce_disabled;
49
50 #ifdef CONFIG_X86_MCE_INTEL
51 unsigned long cmci_intel_adjust_timer(unsigned long interval);
52 bool mce_intel_cmci_poll(void);
53 void mce_intel_hcpu_update(unsigned long cpu);
54 void cmci_disable_bank(int bank);
55 #else
56 # define cmci_intel_adjust_timer mce_adjust_timer_default
mce_intel_cmci_poll(void)57 static inline bool mce_intel_cmci_poll(void) { return false; }
mce_intel_hcpu_update(unsigned long cpu)58 static inline void mce_intel_hcpu_update(unsigned long cpu) { }
cmci_disable_bank(int bank)59 static inline void cmci_disable_bank(int bank) { }
60 #endif
61
62 void mce_timer_kick(unsigned long interval);
63
64 #ifdef CONFIG_ACPI_APEI
65 int apei_write_mce(struct mce *m);
66 ssize_t apei_read_mce(struct mce *m, u64 *record_id);
67 int apei_check_mce(void);
68 int apei_clear_mce(u64 record_id);
69 #else
apei_write_mce(struct mce * m)70 static inline int apei_write_mce(struct mce *m)
71 {
72 return -EINVAL;
73 }
apei_read_mce(struct mce * m,u64 * record_id)74 static inline ssize_t apei_read_mce(struct mce *m, u64 *record_id)
75 {
76 return 0;
77 }
apei_check_mce(void)78 static inline int apei_check_mce(void)
79 {
80 return 0;
81 }
apei_clear_mce(u64 record_id)82 static inline int apei_clear_mce(u64 record_id)
83 {
84 return -EINVAL;
85 }
86 #endif
87
88 void mce_inject_log(struct mce *m);
89
90 /*
91 * We consider records to be equivalent if bank+status+addr+misc all match.
92 * This is only used when the system is going down because of a fatal error
93 * to avoid cluttering the console log with essentially repeated information.
94 * In normal processing all errors seen are logged.
95 */
mce_cmp(struct mce * m1,struct mce * m2)96 static inline bool mce_cmp(struct mce *m1, struct mce *m2)
97 {
98 return m1->bank != m2->bank ||
99 m1->status != m2->status ||
100 m1->addr != m2->addr ||
101 m1->misc != m2->misc;
102 }
103
104 extern struct device_attribute dev_attr_trigger;
105
106 #ifdef CONFIG_X86_MCELOG_LEGACY
107 void mce_work_trigger(void);
108 void mce_register_injector_chain(struct notifier_block *nb);
109 void mce_unregister_injector_chain(struct notifier_block *nb);
110 #else
mce_work_trigger(void)111 static inline void mce_work_trigger(void) { }
mce_register_injector_chain(struct notifier_block * nb)112 static inline void mce_register_injector_chain(struct notifier_block *nb) { }
mce_unregister_injector_chain(struct notifier_block * nb)113 static inline void mce_unregister_injector_chain(struct notifier_block *nb) { }
114 #endif
115
116 struct mca_config {
117 bool dont_log_ce;
118 bool cmci_disabled;
119 bool ignore_ce;
120
121 __u64 lmce_disabled : 1,
122 disabled : 1,
123 ser : 1,
124 recovery : 1,
125 bios_cmci_threshold : 1,
126 __reserved : 59;
127
128 u8 banks;
129 s8 bootlog;
130 int tolerant;
131 int monarch_timeout;
132 int panic_timeout;
133 u32 rip_msr;
134 };
135
136 extern struct mca_config mca_cfg;
137
138 struct mce_vendor_flags {
139 /*
140 * Indicates that overflow conditions are not fatal, when set.
141 */
142 __u64 overflow_recov : 1,
143
144 /*
145 * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and
146 * Recovery. It indicates support for data poisoning in HW and deferred
147 * error interrupts.
148 */
149 succor : 1,
150
151 /*
152 * (AMD) SMCA: This bit indicates support for Scalable MCA which expands
153 * the register space for each MCA bank and also increases number of
154 * banks. Also, to accommodate the new banks and registers, the MCA
155 * register space is moved to a new MSR range.
156 */
157 smca : 1,
158
159 __reserved_0 : 61;
160 };
161
162 extern struct mce_vendor_flags mce_flags;
163
164 struct mca_msr_regs {
165 u32 (*ctl) (int bank);
166 u32 (*status) (int bank);
167 u32 (*addr) (int bank);
168 u32 (*misc) (int bank);
169 };
170
171 extern struct mca_msr_regs msr_ops;
172
173 #endif /* __X86_MCE_INTERNAL_H__ */
174
