1 /***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (C) 2003-2018 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28 #ifndef __CVMX_ASXX_DEFS_H__ 29 #define __CVMX_ASXX_DEFS_H__ 30 31 #define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull)) 32 #define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull)) 33 #define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull) 34 #define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull) 35 #define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull)) 36 #define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull) 37 #define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull) 38 #define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull) 39 #define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull) 40 #define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull) 41 #define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull) 42 #define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull) 43 #define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull) 44 #define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull) 45 #define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull) 46 #define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull) 47 #define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) 48 #define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull) 49 #define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull) 50 #define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull) 51 #define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull) 52 #define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull) 53 #define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) 54 #define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull) 55 #define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) 56 #define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull) 57 58 void __cvmx_interrupt_asxx_enable(int block); 59 60 union cvmx_asxx_gmii_rx_clk_set { 61 uint64_t u64; 62 struct cvmx_asxx_gmii_rx_clk_set_s { 63 #ifdef __BIG_ENDIAN_BITFIELD 64 uint64_t reserved_5_63:59; 65 uint64_t setting:5; 66 #else 67 uint64_t setting:5; 68 uint64_t reserved_5_63:59; 69 #endif 70 } s; 71 struct cvmx_asxx_gmii_rx_clk_set_s cn30xx; 72 struct cvmx_asxx_gmii_rx_clk_set_s cn31xx; 73 struct cvmx_asxx_gmii_rx_clk_set_s cn50xx; 74 }; 75 76 union cvmx_asxx_gmii_rx_dat_set { 77 uint64_t u64; 78 struct cvmx_asxx_gmii_rx_dat_set_s { 79 #ifdef __BIG_ENDIAN_BITFIELD 80 uint64_t reserved_5_63:59; 81 uint64_t setting:5; 82 #else 83 uint64_t setting:5; 84 uint64_t reserved_5_63:59; 85 #endif 86 } s; 87 struct cvmx_asxx_gmii_rx_dat_set_s cn30xx; 88 struct cvmx_asxx_gmii_rx_dat_set_s cn31xx; 89 struct cvmx_asxx_gmii_rx_dat_set_s cn50xx; 90 }; 91 92 union cvmx_asxx_int_en { 93 uint64_t u64; 94 struct cvmx_asxx_int_en_s { 95 #ifdef __BIG_ENDIAN_BITFIELD 96 uint64_t reserved_12_63:52; 97 uint64_t txpsh:4; 98 uint64_t txpop:4; 99 uint64_t ovrflw:4; 100 #else 101 uint64_t ovrflw:4; 102 uint64_t txpop:4; 103 uint64_t txpsh:4; 104 uint64_t reserved_12_63:52; 105 #endif 106 } s; 107 struct cvmx_asxx_int_en_cn30xx { 108 #ifdef __BIG_ENDIAN_BITFIELD 109 uint64_t reserved_11_63:53; 110 uint64_t txpsh:3; 111 uint64_t reserved_7_7:1; 112 uint64_t txpop:3; 113 uint64_t reserved_3_3:1; 114 uint64_t ovrflw:3; 115 #else 116 uint64_t ovrflw:3; 117 uint64_t reserved_3_3:1; 118 uint64_t txpop:3; 119 uint64_t reserved_7_7:1; 120 uint64_t txpsh:3; 121 uint64_t reserved_11_63:53; 122 #endif 123 } cn30xx; 124 struct cvmx_asxx_int_en_cn30xx cn31xx; 125 struct cvmx_asxx_int_en_s cn38xx; 126 struct cvmx_asxx_int_en_s cn38xxp2; 127 struct cvmx_asxx_int_en_cn30xx cn50xx; 128 struct cvmx_asxx_int_en_s cn58xx; 129 struct cvmx_asxx_int_en_s cn58xxp1; 130 }; 131 132 union cvmx_asxx_int_reg { 133 uint64_t u64; 134 struct cvmx_asxx_int_reg_s { 135 #ifdef __BIG_ENDIAN_BITFIELD 136 uint64_t reserved_12_63:52; 137 uint64_t txpsh:4; 138 uint64_t txpop:4; 139 uint64_t ovrflw:4; 140 #else 141 uint64_t ovrflw:4; 142 uint64_t txpop:4; 143 uint64_t txpsh:4; 144 uint64_t reserved_12_63:52; 145 #endif 146 } s; 147 struct cvmx_asxx_int_reg_cn30xx { 148 #ifdef __BIG_ENDIAN_BITFIELD 149 uint64_t reserved_11_63:53; 150 uint64_t txpsh:3; 151 uint64_t reserved_7_7:1; 152 uint64_t txpop:3; 153 uint64_t reserved_3_3:1; 154 uint64_t ovrflw:3; 155 #else 156 uint64_t ovrflw:3; 157 uint64_t reserved_3_3:1; 158 uint64_t txpop:3; 159 uint64_t reserved_7_7:1; 160 uint64_t txpsh:3; 161 uint64_t reserved_11_63:53; 162 #endif 163 } cn30xx; 164 struct cvmx_asxx_int_reg_cn30xx cn31xx; 165 struct cvmx_asxx_int_reg_s cn38xx; 166 struct cvmx_asxx_int_reg_s cn38xxp2; 167 struct cvmx_asxx_int_reg_cn30xx cn50xx; 168 struct cvmx_asxx_int_reg_s cn58xx; 169 struct cvmx_asxx_int_reg_s cn58xxp1; 170 }; 171 172 union cvmx_asxx_mii_rx_dat_set { 173 uint64_t u64; 174 struct cvmx_asxx_mii_rx_dat_set_s { 175 #ifdef __BIG_ENDIAN_BITFIELD 176 uint64_t reserved_5_63:59; 177 uint64_t setting:5; 178 #else 179 uint64_t setting:5; 180 uint64_t reserved_5_63:59; 181 #endif 182 } s; 183 struct cvmx_asxx_mii_rx_dat_set_s cn30xx; 184 struct cvmx_asxx_mii_rx_dat_set_s cn50xx; 185 }; 186 187 union cvmx_asxx_prt_loop { 188 uint64_t u64; 189 struct cvmx_asxx_prt_loop_s { 190 #ifdef __BIG_ENDIAN_BITFIELD 191 uint64_t reserved_8_63:56; 192 uint64_t ext_loop:4; 193 uint64_t int_loop:4; 194 #else 195 uint64_t int_loop:4; 196 uint64_t ext_loop:4; 197 uint64_t reserved_8_63:56; 198 #endif 199 } s; 200 struct cvmx_asxx_prt_loop_cn30xx { 201 #ifdef __BIG_ENDIAN_BITFIELD 202 uint64_t reserved_7_63:57; 203 uint64_t ext_loop:3; 204 uint64_t reserved_3_3:1; 205 uint64_t int_loop:3; 206 #else 207 uint64_t int_loop:3; 208 uint64_t reserved_3_3:1; 209 uint64_t ext_loop:3; 210 uint64_t reserved_7_63:57; 211 #endif 212 } cn30xx; 213 struct cvmx_asxx_prt_loop_cn30xx cn31xx; 214 struct cvmx_asxx_prt_loop_s cn38xx; 215 struct cvmx_asxx_prt_loop_s cn38xxp2; 216 struct cvmx_asxx_prt_loop_cn30xx cn50xx; 217 struct cvmx_asxx_prt_loop_s cn58xx; 218 struct cvmx_asxx_prt_loop_s cn58xxp1; 219 }; 220 221 union cvmx_asxx_rld_bypass { 222 uint64_t u64; 223 struct cvmx_asxx_rld_bypass_s { 224 #ifdef __BIG_ENDIAN_BITFIELD 225 uint64_t reserved_1_63:63; 226 uint64_t bypass:1; 227 #else 228 uint64_t bypass:1; 229 uint64_t reserved_1_63:63; 230 #endif 231 } s; 232 struct cvmx_asxx_rld_bypass_s cn38xx; 233 struct cvmx_asxx_rld_bypass_s cn38xxp2; 234 struct cvmx_asxx_rld_bypass_s cn58xx; 235 struct cvmx_asxx_rld_bypass_s cn58xxp1; 236 }; 237 238 union cvmx_asxx_rld_bypass_setting { 239 uint64_t u64; 240 struct cvmx_asxx_rld_bypass_setting_s { 241 #ifdef __BIG_ENDIAN_BITFIELD 242 uint64_t reserved_5_63:59; 243 uint64_t setting:5; 244 #else 245 uint64_t setting:5; 246 uint64_t reserved_5_63:59; 247 #endif 248 } s; 249 struct cvmx_asxx_rld_bypass_setting_s cn38xx; 250 struct cvmx_asxx_rld_bypass_setting_s cn38xxp2; 251 struct cvmx_asxx_rld_bypass_setting_s cn58xx; 252 struct cvmx_asxx_rld_bypass_setting_s cn58xxp1; 253 }; 254 255 union cvmx_asxx_rld_comp { 256 uint64_t u64; 257 struct cvmx_asxx_rld_comp_s { 258 #ifdef __BIG_ENDIAN_BITFIELD 259 uint64_t reserved_9_63:55; 260 uint64_t pctl:5; 261 uint64_t nctl:4; 262 #else 263 uint64_t nctl:4; 264 uint64_t pctl:5; 265 uint64_t reserved_9_63:55; 266 #endif 267 } s; 268 struct cvmx_asxx_rld_comp_cn38xx { 269 #ifdef __BIG_ENDIAN_BITFIELD 270 uint64_t reserved_8_63:56; 271 uint64_t pctl:4; 272 uint64_t nctl:4; 273 #else 274 uint64_t nctl:4; 275 uint64_t pctl:4; 276 uint64_t reserved_8_63:56; 277 #endif 278 } cn38xx; 279 struct cvmx_asxx_rld_comp_cn38xx cn38xxp2; 280 struct cvmx_asxx_rld_comp_s cn58xx; 281 struct cvmx_asxx_rld_comp_s cn58xxp1; 282 }; 283 284 union cvmx_asxx_rld_data_drv { 285 uint64_t u64; 286 struct cvmx_asxx_rld_data_drv_s { 287 #ifdef __BIG_ENDIAN_BITFIELD 288 uint64_t reserved_8_63:56; 289 uint64_t pctl:4; 290 uint64_t nctl:4; 291 #else 292 uint64_t nctl:4; 293 uint64_t pctl:4; 294 uint64_t reserved_8_63:56; 295 #endif 296 } s; 297 struct cvmx_asxx_rld_data_drv_s cn38xx; 298 struct cvmx_asxx_rld_data_drv_s cn38xxp2; 299 struct cvmx_asxx_rld_data_drv_s cn58xx; 300 struct cvmx_asxx_rld_data_drv_s cn58xxp1; 301 }; 302 303 union cvmx_asxx_rld_fcram_mode { 304 uint64_t u64; 305 struct cvmx_asxx_rld_fcram_mode_s { 306 #ifdef __BIG_ENDIAN_BITFIELD 307 uint64_t reserved_1_63:63; 308 uint64_t mode:1; 309 #else 310 uint64_t mode:1; 311 uint64_t reserved_1_63:63; 312 #endif 313 } s; 314 struct cvmx_asxx_rld_fcram_mode_s cn38xx; 315 struct cvmx_asxx_rld_fcram_mode_s cn38xxp2; 316 }; 317 318 union cvmx_asxx_rld_nctl_strong { 319 uint64_t u64; 320 struct cvmx_asxx_rld_nctl_strong_s { 321 #ifdef __BIG_ENDIAN_BITFIELD 322 uint64_t reserved_5_63:59; 323 uint64_t nctl:5; 324 #else 325 uint64_t nctl:5; 326 uint64_t reserved_5_63:59; 327 #endif 328 } s; 329 struct cvmx_asxx_rld_nctl_strong_s cn38xx; 330 struct cvmx_asxx_rld_nctl_strong_s cn38xxp2; 331 struct cvmx_asxx_rld_nctl_strong_s cn58xx; 332 struct cvmx_asxx_rld_nctl_strong_s cn58xxp1; 333 }; 334 335 union cvmx_asxx_rld_nctl_weak { 336 uint64_t u64; 337 struct cvmx_asxx_rld_nctl_weak_s { 338 #ifdef __BIG_ENDIAN_BITFIELD 339 uint64_t reserved_5_63:59; 340 uint64_t nctl:5; 341 #else 342 uint64_t nctl:5; 343 uint64_t reserved_5_63:59; 344 #endif 345 } s; 346 struct cvmx_asxx_rld_nctl_weak_s cn38xx; 347 struct cvmx_asxx_rld_nctl_weak_s cn38xxp2; 348 struct cvmx_asxx_rld_nctl_weak_s cn58xx; 349 struct cvmx_asxx_rld_nctl_weak_s cn58xxp1; 350 }; 351 352 union cvmx_asxx_rld_pctl_strong { 353 uint64_t u64; 354 struct cvmx_asxx_rld_pctl_strong_s { 355 #ifdef __BIG_ENDIAN_BITFIELD 356 uint64_t reserved_5_63:59; 357 uint64_t pctl:5; 358 #else 359 uint64_t pctl:5; 360 uint64_t reserved_5_63:59; 361 #endif 362 } s; 363 struct cvmx_asxx_rld_pctl_strong_s cn38xx; 364 struct cvmx_asxx_rld_pctl_strong_s cn38xxp2; 365 struct cvmx_asxx_rld_pctl_strong_s cn58xx; 366 struct cvmx_asxx_rld_pctl_strong_s cn58xxp1; 367 }; 368 369 union cvmx_asxx_rld_pctl_weak { 370 uint64_t u64; 371 struct cvmx_asxx_rld_pctl_weak_s { 372 #ifdef __BIG_ENDIAN_BITFIELD 373 uint64_t reserved_5_63:59; 374 uint64_t pctl:5; 375 #else 376 uint64_t pctl:5; 377 uint64_t reserved_5_63:59; 378 #endif 379 } s; 380 struct cvmx_asxx_rld_pctl_weak_s cn38xx; 381 struct cvmx_asxx_rld_pctl_weak_s cn38xxp2; 382 struct cvmx_asxx_rld_pctl_weak_s cn58xx; 383 struct cvmx_asxx_rld_pctl_weak_s cn58xxp1; 384 }; 385 386 union cvmx_asxx_rld_setting { 387 uint64_t u64; 388 struct cvmx_asxx_rld_setting_s { 389 #ifdef __BIG_ENDIAN_BITFIELD 390 uint64_t reserved_13_63:51; 391 uint64_t dfaset:5; 392 uint64_t dfalag:1; 393 uint64_t dfalead:1; 394 uint64_t dfalock:1; 395 uint64_t setting:5; 396 #else 397 uint64_t setting:5; 398 uint64_t dfalock:1; 399 uint64_t dfalead:1; 400 uint64_t dfalag:1; 401 uint64_t dfaset:5; 402 uint64_t reserved_13_63:51; 403 #endif 404 } s; 405 struct cvmx_asxx_rld_setting_cn38xx { 406 #ifdef __BIG_ENDIAN_BITFIELD 407 uint64_t reserved_5_63:59; 408 uint64_t setting:5; 409 #else 410 uint64_t setting:5; 411 uint64_t reserved_5_63:59; 412 #endif 413 } cn38xx; 414 struct cvmx_asxx_rld_setting_cn38xx cn38xxp2; 415 struct cvmx_asxx_rld_setting_s cn58xx; 416 struct cvmx_asxx_rld_setting_s cn58xxp1; 417 }; 418 419 union cvmx_asxx_rx_clk_setx { 420 uint64_t u64; 421 struct cvmx_asxx_rx_clk_setx_s { 422 #ifdef __BIG_ENDIAN_BITFIELD 423 uint64_t reserved_5_63:59; 424 uint64_t setting:5; 425 #else 426 uint64_t setting:5; 427 uint64_t reserved_5_63:59; 428 #endif 429 } s; 430 struct cvmx_asxx_rx_clk_setx_s cn30xx; 431 struct cvmx_asxx_rx_clk_setx_s cn31xx; 432 struct cvmx_asxx_rx_clk_setx_s cn38xx; 433 struct cvmx_asxx_rx_clk_setx_s cn38xxp2; 434 struct cvmx_asxx_rx_clk_setx_s cn50xx; 435 struct cvmx_asxx_rx_clk_setx_s cn58xx; 436 struct cvmx_asxx_rx_clk_setx_s cn58xxp1; 437 }; 438 439 union cvmx_asxx_rx_prt_en { 440 uint64_t u64; 441 struct cvmx_asxx_rx_prt_en_s { 442 #ifdef __BIG_ENDIAN_BITFIELD 443 uint64_t reserved_4_63:60; 444 uint64_t prt_en:4; 445 #else 446 uint64_t prt_en:4; 447 uint64_t reserved_4_63:60; 448 #endif 449 } s; 450 struct cvmx_asxx_rx_prt_en_cn30xx { 451 #ifdef __BIG_ENDIAN_BITFIELD 452 uint64_t reserved_3_63:61; 453 uint64_t prt_en:3; 454 #else 455 uint64_t prt_en:3; 456 uint64_t reserved_3_63:61; 457 #endif 458 } cn30xx; 459 struct cvmx_asxx_rx_prt_en_cn30xx cn31xx; 460 struct cvmx_asxx_rx_prt_en_s cn38xx; 461 struct cvmx_asxx_rx_prt_en_s cn38xxp2; 462 struct cvmx_asxx_rx_prt_en_cn30xx cn50xx; 463 struct cvmx_asxx_rx_prt_en_s cn58xx; 464 struct cvmx_asxx_rx_prt_en_s cn58xxp1; 465 }; 466 467 union cvmx_asxx_rx_wol { 468 uint64_t u64; 469 struct cvmx_asxx_rx_wol_s { 470 #ifdef __BIG_ENDIAN_BITFIELD 471 uint64_t reserved_2_63:62; 472 uint64_t status:1; 473 uint64_t enable:1; 474 #else 475 uint64_t enable:1; 476 uint64_t status:1; 477 uint64_t reserved_2_63:62; 478 #endif 479 } s; 480 struct cvmx_asxx_rx_wol_s cn38xx; 481 struct cvmx_asxx_rx_wol_s cn38xxp2; 482 }; 483 484 union cvmx_asxx_rx_wol_msk { 485 uint64_t u64; 486 struct cvmx_asxx_rx_wol_msk_s { 487 #ifdef __BIG_ENDIAN_BITFIELD 488 uint64_t msk:64; 489 #else 490 uint64_t msk:64; 491 #endif 492 } s; 493 struct cvmx_asxx_rx_wol_msk_s cn38xx; 494 struct cvmx_asxx_rx_wol_msk_s cn38xxp2; 495 }; 496 497 union cvmx_asxx_rx_wol_powok { 498 uint64_t u64; 499 struct cvmx_asxx_rx_wol_powok_s { 500 #ifdef __BIG_ENDIAN_BITFIELD 501 uint64_t reserved_1_63:63; 502 uint64_t powerok:1; 503 #else 504 uint64_t powerok:1; 505 uint64_t reserved_1_63:63; 506 #endif 507 } s; 508 struct cvmx_asxx_rx_wol_powok_s cn38xx; 509 struct cvmx_asxx_rx_wol_powok_s cn38xxp2; 510 }; 511 512 union cvmx_asxx_rx_wol_sig { 513 uint64_t u64; 514 struct cvmx_asxx_rx_wol_sig_s { 515 #ifdef __BIG_ENDIAN_BITFIELD 516 uint64_t reserved_32_63:32; 517 uint64_t sig:32; 518 #else 519 uint64_t sig:32; 520 uint64_t reserved_32_63:32; 521 #endif 522 } s; 523 struct cvmx_asxx_rx_wol_sig_s cn38xx; 524 struct cvmx_asxx_rx_wol_sig_s cn38xxp2; 525 }; 526 527 union cvmx_asxx_tx_clk_setx { 528 uint64_t u64; 529 struct cvmx_asxx_tx_clk_setx_s { 530 #ifdef __BIG_ENDIAN_BITFIELD 531 uint64_t reserved_5_63:59; 532 uint64_t setting:5; 533 #else 534 uint64_t setting:5; 535 uint64_t reserved_5_63:59; 536 #endif 537 } s; 538 struct cvmx_asxx_tx_clk_setx_s cn30xx; 539 struct cvmx_asxx_tx_clk_setx_s cn31xx; 540 struct cvmx_asxx_tx_clk_setx_s cn38xx; 541 struct cvmx_asxx_tx_clk_setx_s cn38xxp2; 542 struct cvmx_asxx_tx_clk_setx_s cn50xx; 543 struct cvmx_asxx_tx_clk_setx_s cn58xx; 544 struct cvmx_asxx_tx_clk_setx_s cn58xxp1; 545 }; 546 547 union cvmx_asxx_tx_comp_byp { 548 uint64_t u64; 549 struct cvmx_asxx_tx_comp_byp_s { 550 #ifdef __BIG_ENDIAN_BITFIELD 551 uint64_t reserved_0_63:64; 552 #else 553 uint64_t reserved_0_63:64; 554 #endif 555 } s; 556 struct cvmx_asxx_tx_comp_byp_cn30xx { 557 #ifdef __BIG_ENDIAN_BITFIELD 558 uint64_t reserved_9_63:55; 559 uint64_t bypass:1; 560 uint64_t pctl:4; 561 uint64_t nctl:4; 562 #else 563 uint64_t nctl:4; 564 uint64_t pctl:4; 565 uint64_t bypass:1; 566 uint64_t reserved_9_63:55; 567 #endif 568 } cn30xx; 569 struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx; 570 struct cvmx_asxx_tx_comp_byp_cn38xx { 571 #ifdef __BIG_ENDIAN_BITFIELD 572 uint64_t reserved_8_63:56; 573 uint64_t pctl:4; 574 uint64_t nctl:4; 575 #else 576 uint64_t nctl:4; 577 uint64_t pctl:4; 578 uint64_t reserved_8_63:56; 579 #endif 580 } cn38xx; 581 struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2; 582 struct cvmx_asxx_tx_comp_byp_cn50xx { 583 #ifdef __BIG_ENDIAN_BITFIELD 584 uint64_t reserved_17_63:47; 585 uint64_t bypass:1; 586 uint64_t reserved_13_15:3; 587 uint64_t pctl:5; 588 uint64_t reserved_5_7:3; 589 uint64_t nctl:5; 590 #else 591 uint64_t nctl:5; 592 uint64_t reserved_5_7:3; 593 uint64_t pctl:5; 594 uint64_t reserved_13_15:3; 595 uint64_t bypass:1; 596 uint64_t reserved_17_63:47; 597 #endif 598 } cn50xx; 599 struct cvmx_asxx_tx_comp_byp_cn58xx { 600 #ifdef __BIG_ENDIAN_BITFIELD 601 uint64_t reserved_13_63:51; 602 uint64_t pctl:5; 603 uint64_t reserved_5_7:3; 604 uint64_t nctl:5; 605 #else 606 uint64_t nctl:5; 607 uint64_t reserved_5_7:3; 608 uint64_t pctl:5; 609 uint64_t reserved_13_63:51; 610 #endif 611 } cn58xx; 612 struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1; 613 }; 614 615 union cvmx_asxx_tx_hi_waterx { 616 uint64_t u64; 617 struct cvmx_asxx_tx_hi_waterx_s { 618 #ifdef __BIG_ENDIAN_BITFIELD 619 uint64_t reserved_4_63:60; 620 uint64_t mark:4; 621 #else 622 uint64_t mark:4; 623 uint64_t reserved_4_63:60; 624 #endif 625 } s; 626 struct cvmx_asxx_tx_hi_waterx_cn30xx { 627 #ifdef __BIG_ENDIAN_BITFIELD 628 uint64_t reserved_3_63:61; 629 uint64_t mark:3; 630 #else 631 uint64_t mark:3; 632 uint64_t reserved_3_63:61; 633 #endif 634 } cn30xx; 635 struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx; 636 struct cvmx_asxx_tx_hi_waterx_s cn38xx; 637 struct cvmx_asxx_tx_hi_waterx_s cn38xxp2; 638 struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx; 639 struct cvmx_asxx_tx_hi_waterx_s cn58xx; 640 struct cvmx_asxx_tx_hi_waterx_s cn58xxp1; 641 }; 642 643 union cvmx_asxx_tx_prt_en { 644 uint64_t u64; 645 struct cvmx_asxx_tx_prt_en_s { 646 #ifdef __BIG_ENDIAN_BITFIELD 647 uint64_t reserved_4_63:60; 648 uint64_t prt_en:4; 649 #else 650 uint64_t prt_en:4; 651 uint64_t reserved_4_63:60; 652 #endif 653 } s; 654 struct cvmx_asxx_tx_prt_en_cn30xx { 655 #ifdef __BIG_ENDIAN_BITFIELD 656 uint64_t reserved_3_63:61; 657 uint64_t prt_en:3; 658 #else 659 uint64_t prt_en:3; 660 uint64_t reserved_3_63:61; 661 #endif 662 } cn30xx; 663 struct cvmx_asxx_tx_prt_en_cn30xx cn31xx; 664 struct cvmx_asxx_tx_prt_en_s cn38xx; 665 struct cvmx_asxx_tx_prt_en_s cn38xxp2; 666 struct cvmx_asxx_tx_prt_en_cn30xx cn50xx; 667 struct cvmx_asxx_tx_prt_en_s cn58xx; 668 struct cvmx_asxx_tx_prt_en_s cn58xxp1; 669 }; 670 671 #endif 672
