1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000, 06 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
10 * Author: Maciej W. Rozycki <macro@mips.com>
11 */
12 #ifndef _ASM_IO_H
13 #define _ASM_IO_H
14
15 #define ARCH_HAS_IOREMAP_WC
16
17 #include <linux/compiler.h>
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/irqflags.h>
21
22 #include <asm/addrspace.h>
23 #include <asm/bug.h>
24 #include <asm/byteorder.h>
25 #include <asm/cpu.h>
26 #include <asm/cpu-features.h>
27 #include <asm-generic/iomap.h>
28 #include <asm/page.h>
29 #include <asm/pgtable-bits.h>
30 #include <asm/processor.h>
31 #include <asm/string.h>
32
33 #include <ioremap.h>
34 #include <mangle-port.h>
35
36 /*
37 * Slowdown I/O port space accesses for antique hardware.
38 */
39 #undef CONF_SLOWDOWN_IO
40
41 /*
42 * Raw operations are never swapped in software. OTOH values that raw
43 * operations are working on may or may not have been swapped by the bus
44 * hardware. An example use would be for flash memory that's used for
45 * execute in place.
46 */
47 # define __raw_ioswabb(a, x) (x)
48 # define __raw_ioswabw(a, x) (x)
49 # define __raw_ioswabl(a, x) (x)
50 # define __raw_ioswabq(a, x) (x)
51 # define ____raw_ioswabq(a, x) (x)
52
53 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
54
55 #define IO_SPACE_LIMIT 0xffff
56
57 /*
58 * On MIPS I/O ports are memory mapped, so we access them using normal
59 * load/store instructions. mips_io_port_base is the virtual address to
60 * which all ports are being mapped. For sake of efficiency some code
61 * assumes that this is an address that can be loaded with a single lui
62 * instruction, so the lower 16 bits must be zero. Should be true on
63 * on any sane architecture; generic code does not use this assumption.
64 */
65 extern const unsigned long mips_io_port_base;
66
67 /*
68 * Gcc will generate code to load the value of mips_io_port_base after each
69 * function call which may be fairly wasteful in some cases. So we don't
70 * play quite by the book. We tell gcc mips_io_port_base is a long variable
71 * which solves the code generation issue. Now we need to violate the
72 * aliasing rules a little to make initialization possible and finally we
73 * will need the barrier() to fight side effects of the aliasing chat.
74 * This trickery will eventually collapse under gcc's optimizer. Oh well.
75 */
set_io_port_base(unsigned long base)76 static inline void set_io_port_base(unsigned long base)
77 {
78 * (unsigned long *) &mips_io_port_base = base;
79 barrier();
80 }
81
82 /*
83 * Thanks to James van Artsdalen for a better timing-fix than
84 * the two short jumps: using outb's to a nonexistent port seems
85 * to guarantee better timings even on fast machines.
86 *
87 * On the other hand, I'd like to be sure of a non-existent port:
88 * I feel a bit unsafe about using 0x80 (should be safe, though)
89 *
90 * Linus
91 *
92 */
93
94 #define __SLOW_DOWN_IO \
95 __asm__ __volatile__( \
96 "sb\t$0,0x80(%0)" \
97 : : "r" (mips_io_port_base));
98
99 #ifdef CONF_SLOWDOWN_IO
100 #ifdef REALLY_SLOW_IO
101 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
102 #else
103 #define SLOW_DOWN_IO __SLOW_DOWN_IO
104 #endif
105 #else
106 #define SLOW_DOWN_IO
107 #endif
108
109 /*
110 * virt_to_phys - map virtual addresses to physical
111 * @address: address to remap
112 *
113 * The returned physical address is the physical (CPU) mapping for
114 * the memory address given. It is only valid to use this function on
115 * addresses directly mapped or allocated via kmalloc.
116 *
117 * This function does not give bus mappings for DMA transfers. In
118 * almost all conceivable cases a device driver should not be using
119 * this function
120 */
virt_to_phys(volatile const void * address)121 static inline unsigned long virt_to_phys(volatile const void *address)
122 {
123 return __pa(address);
124 }
125
126 /*
127 * phys_to_virt - map physical address to virtual
128 * @address: address to remap
129 *
130 * The returned virtual address is a current CPU mapping for
131 * the memory address given. It is only valid to use this function on
132 * addresses that have a kernel mapping
133 *
134 * This function does not handle bus mappings for DMA transfers. In
135 * almost all conceivable cases a device driver should not be using
136 * this function
137 */
phys_to_virt(unsigned long address)138 static inline void * phys_to_virt(unsigned long address)
139 {
140 return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
141 }
142
143 /*
144 * ISA I/O bus memory addresses are 1:1 with the physical address.
145 */
isa_virt_to_bus(volatile void * address)146 static inline unsigned long isa_virt_to_bus(volatile void *address)
147 {
148 return virt_to_phys(address);
149 }
150
isa_bus_to_virt(unsigned long address)151 static inline void *isa_bus_to_virt(unsigned long address)
152 {
153 return phys_to_virt(address);
154 }
155
156 #define isa_page_to_bus page_to_phys
157
158 /*
159 * However PCI ones are not necessarily 1:1 and therefore these interfaces
160 * are forbidden in portable PCI drivers.
161 *
162 * Allow them for x86 for legacy drivers, though.
163 */
164 #define virt_to_bus virt_to_phys
165 #define bus_to_virt phys_to_virt
166
167 /*
168 * Change "struct page" to physical address.
169 */
170 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
171
172 extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags);
173 extern void __iounmap(const volatile void __iomem *addr);
174
175 #ifndef CONFIG_PCI
176 struct pci_dev;
pci_iounmap(struct pci_dev * dev,void __iomem * addr)177 static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
178 #endif
179
__ioremap_mode(phys_addr_t offset,unsigned long size,unsigned long flags)180 static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size,
181 unsigned long flags)
182 {
183 void __iomem *addr = plat_ioremap(offset, size, flags);
184
185 if (addr)
186 return addr;
187
188 #define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL))
189
190 if (cpu_has_64bit_addresses) {
191 u64 base = UNCAC_BASE;
192
193 /*
194 * R10000 supports a 2 bit uncached attribute therefore
195 * UNCAC_BASE may not equal IO_BASE.
196 */
197 if (flags == _CACHE_UNCACHED)
198 base = (u64) IO_BASE;
199 return (void __iomem *) (unsigned long) (base + offset);
200 } else if (__builtin_constant_p(offset) &&
201 __builtin_constant_p(size) && __builtin_constant_p(flags)) {
202 phys_addr_t phys_addr, last_addr;
203
204 phys_addr = fixup_bigphys_addr(offset, size);
205
206 /* Don't allow wraparound or zero size. */
207 last_addr = phys_addr + size - 1;
208 if (!size || last_addr < phys_addr)
209 return NULL;
210
211 /*
212 * Map uncached objects in the low 512MB of address
213 * space using KSEG1.
214 */
215 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
216 flags == _CACHE_UNCACHED)
217 return (void __iomem *)
218 (unsigned long)CKSEG1ADDR(phys_addr);
219 }
220
221 return __ioremap(offset, size, flags);
222
223 #undef __IS_LOW512
224 }
225
226 /*
227 * ioremap - map bus memory into CPU space
228 * @offset: bus address of the memory
229 * @size: size of the resource to map
230 *
231 * ioremap performs a platform specific sequence of operations to
232 * make bus memory CPU accessible via the readb/readw/readl/writeb/
233 * writew/writel functions and the other mmio helpers. The returned
234 * address is not guaranteed to be usable directly as a virtual
235 * address.
236 */
237 #define ioremap(offset, size) \
238 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
239
240 /*
241 * ioremap_nocache - map bus memory into CPU space
242 * @offset: bus address of the memory
243 * @size: size of the resource to map
244 *
245 * ioremap_nocache performs a platform specific sequence of operations to
246 * make bus memory CPU accessible via the readb/readw/readl/writeb/
247 * writew/writel functions and the other mmio helpers. The returned
248 * address is not guaranteed to be usable directly as a virtual
249 * address.
250 *
251 * This version of ioremap ensures that the memory is marked uncachable
252 * on the CPU as well as honouring existing caching rules from things like
253 * the PCI bus. Note that there are other caches and buffers on many
254 * busses. In particular driver authors should read up on PCI writes
255 *
256 * It's useful if some control registers are in such an area and
257 * write combining or read caching is not desirable:
258 */
259 #define ioremap_nocache(offset, size) \
260 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
261 #define ioremap_uc ioremap_nocache
262
263 /*
264 * ioremap_cachable - map bus memory into CPU space
265 * @offset: bus address of the memory
266 * @size: size of the resource to map
267 *
268 * ioremap_nocache performs a platform specific sequence of operations to
269 * make bus memory CPU accessible via the readb/readw/readl/writeb/
270 * writew/writel functions and the other mmio helpers. The returned
271 * address is not guaranteed to be usable directly as a virtual
272 * address.
273 *
274 * This version of ioremap ensures that the memory is marked cachable by
275 * the CPU. Also enables full write-combining. Useful for some
276 * memory-like regions on I/O busses.
277 */
278 #define ioremap_cachable(offset, size) \
279 __ioremap_mode((offset), (size), _page_cachable_default)
280 #define ioremap_cache ioremap_cachable
281
282 /*
283 * ioremap_wc - map bus memory into CPU space
284 * @offset: bus address of the memory
285 * @size: size of the resource to map
286 *
287 * ioremap_wc performs a platform specific sequence of operations to
288 * make bus memory CPU accessible via the readb/readw/readl/writeb/
289 * writew/writel functions and the other mmio helpers. The returned
290 * address is not guaranteed to be usable directly as a virtual
291 * address.
292 *
293 * This version of ioremap ensures that the memory is marked uncachable
294 * but accelerated by means of write-combining feature. It is specifically
295 * useful for PCIe prefetchable windows, which may vastly improve a
296 * communications performance. If it was determined on boot stage, what
297 * CPU CCA doesn't support UCA, the method shall fall-back to the
298 * _CACHE_UNCACHED option (see cpu_probe() method).
299 */
300 #define ioremap_wc(offset, size) \
301 __ioremap_mode((offset), (size), boot_cpu_data.writecombine)
302
iounmap(const volatile void __iomem * addr)303 static inline void iounmap(const volatile void __iomem *addr)
304 {
305 if (plat_iounmap(addr))
306 return;
307
308 #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
309
310 if (cpu_has_64bit_addresses ||
311 (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
312 return;
313
314 __iounmap(addr);
315
316 #undef __IS_KSEG1
317 }
318
319 #if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT)
320 #define war_io_reorder_wmb() wmb()
321 #else
322 #define war_io_reorder_wmb() barrier()
323 #endif
324
325 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
326 \
327 static inline void pfx##write##bwlq(type val, \
328 volatile void __iomem *mem) \
329 { \
330 volatile type *__mem; \
331 type __val; \
332 \
333 war_io_reorder_wmb(); \
334 \
335 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
336 \
337 __val = pfx##ioswab##bwlq(__mem, val); \
338 \
339 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
340 *__mem = __val; \
341 else if (cpu_has_64bits) { \
342 unsigned long __flags; \
343 type __tmp; \
344 \
345 if (irq) \
346 local_irq_save(__flags); \
347 __asm__ __volatile__( \
348 ".set arch=r4000" "\t\t# __writeq""\n\t" \
349 "dsll32 %L0, %L0, 0" "\n\t" \
350 "dsrl32 %L0, %L0, 0" "\n\t" \
351 "dsll32 %M0, %M0, 0" "\n\t" \
352 "or %L0, %L0, %M0" "\n\t" \
353 "sd %L0, %2" "\n\t" \
354 ".set mips0" "\n" \
355 : "=r" (__tmp) \
356 : "0" (__val), "m" (*__mem)); \
357 if (irq) \
358 local_irq_restore(__flags); \
359 } else \
360 BUG(); \
361 } \
362 \
363 static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
364 { \
365 volatile type *__mem; \
366 type __val; \
367 \
368 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
369 \
370 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
371 __val = *__mem; \
372 else if (cpu_has_64bits) { \
373 unsigned long __flags; \
374 \
375 if (irq) \
376 local_irq_save(__flags); \
377 __asm__ __volatile__( \
378 ".set arch=r4000" "\t\t# __readq" "\n\t" \
379 "ld %L0, %1" "\n\t" \
380 "dsra32 %M0, %L0, 0" "\n\t" \
381 "sll %L0, %L0, 0" "\n\t" \
382 ".set mips0" "\n" \
383 : "=r" (__val) \
384 : "m" (*__mem)); \
385 if (irq) \
386 local_irq_restore(__flags); \
387 } else { \
388 __val = 0; \
389 BUG(); \
390 } \
391 \
392 /* prevent prefetching of coherent DMA data prematurely */ \
393 rmb(); \
394 return pfx##ioswab##bwlq(__mem, __val); \
395 }
396
397 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
398 \
399 static inline void pfx##out##bwlq##p(type val, unsigned long port) \
400 { \
401 volatile type *__addr; \
402 type __val; \
403 \
404 war_io_reorder_wmb(); \
405 \
406 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
407 \
408 __val = pfx##ioswab##bwlq(__addr, val); \
409 \
410 /* Really, we want this to be atomic */ \
411 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
412 \
413 *__addr = __val; \
414 slow; \
415 } \
416 \
417 static inline type pfx##in##bwlq##p(unsigned long port) \
418 { \
419 volatile type *__addr; \
420 type __val; \
421 \
422 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
423 \
424 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
425 \
426 __val = *__addr; \
427 slow; \
428 \
429 /* prevent prefetching of coherent DMA data prematurely */ \
430 rmb(); \
431 return pfx##ioswab##bwlq(__addr, __val); \
432 }
433
434 #define __BUILD_MEMORY_PFX(bus, bwlq, type) \
435 \
436 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
437
438 #define BUILDIO_MEM(bwlq, type) \
439 \
440 __BUILD_MEMORY_PFX(__raw_, bwlq, type) \
441 __BUILD_MEMORY_PFX(, bwlq, type) \
442 __BUILD_MEMORY_PFX(__mem_, bwlq, type) \
443
BUILDIO_MEM(b,u8)444 BUILDIO_MEM(b, u8)
445 BUILDIO_MEM(w, u16)
446 BUILDIO_MEM(l, u32)
447 BUILDIO_MEM(q, u64)
448
449 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \
450 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
451 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
452
453 #define BUILDIO_IOPORT(bwlq, type) \
454 __BUILD_IOPORT_PFX(, bwlq, type) \
455 __BUILD_IOPORT_PFX(__mem_, bwlq, type)
456
457 BUILDIO_IOPORT(b, u8)
458 BUILDIO_IOPORT(w, u16)
459 BUILDIO_IOPORT(l, u32)
460 #ifdef CONFIG_64BIT
461 BUILDIO_IOPORT(q, u64)
462 #endif
463
464 #define __BUILDIO(bwlq, type) \
465 \
466 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
467
468 __BUILDIO(q, u64)
469
470 #define readb_relaxed readb
471 #define readw_relaxed readw
472 #define readl_relaxed readl
473 #define readq_relaxed readq
474
475 #define writeb_relaxed writeb
476 #define writew_relaxed writew
477 #define writel_relaxed writel
478 #define writeq_relaxed writeq
479
480 #define readb_be(addr) \
481 __raw_readb((__force unsigned *)(addr))
482 #define readw_be(addr) \
483 be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
484 #define readl_be(addr) \
485 be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
486 #define readq_be(addr) \
487 be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
488
489 #define writeb_be(val, addr) \
490 __raw_writeb((val), (__force unsigned *)(addr))
491 #define writew_be(val, addr) \
492 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
493 #define writel_be(val, addr) \
494 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
495 #define writeq_be(val, addr) \
496 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
497
498 /*
499 * Some code tests for these symbols
500 */
501 #define readq readq
502 #define writeq writeq
503
504 #define __BUILD_MEMORY_STRING(bwlq, type) \
505 \
506 static inline void writes##bwlq(volatile void __iomem *mem, \
507 const void *addr, unsigned int count) \
508 { \
509 const volatile type *__addr = addr; \
510 \
511 while (count--) { \
512 __mem_write##bwlq(*__addr, mem); \
513 __addr++; \
514 } \
515 } \
516 \
517 static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
518 unsigned int count) \
519 { \
520 volatile type *__addr = addr; \
521 \
522 while (count--) { \
523 *__addr = __mem_read##bwlq(mem); \
524 __addr++; \
525 } \
526 }
527
528 #define __BUILD_IOPORT_STRING(bwlq, type) \
529 \
530 static inline void outs##bwlq(unsigned long port, const void *addr, \
531 unsigned int count) \
532 { \
533 const volatile type *__addr = addr; \
534 \
535 while (count--) { \
536 __mem_out##bwlq(*__addr, port); \
537 __addr++; \
538 } \
539 } \
540 \
541 static inline void ins##bwlq(unsigned long port, void *addr, \
542 unsigned int count) \
543 { \
544 volatile type *__addr = addr; \
545 \
546 while (count--) { \
547 *__addr = __mem_in##bwlq(port); \
548 __addr++; \
549 } \
550 }
551
552 #define BUILDSTRING(bwlq, type) \
553 \
554 __BUILD_MEMORY_STRING(bwlq, type) \
555 __BUILD_IOPORT_STRING(bwlq, type)
556
557 BUILDSTRING(b, u8)
558 BUILDSTRING(w, u16)
559 BUILDSTRING(l, u32)
560 #ifdef CONFIG_64BIT
561 BUILDSTRING(q, u64)
562 #endif
563
564
565 #ifdef CONFIG_CPU_CAVIUM_OCTEON
566 #define mmiowb() wmb()
567 #else
568 /* Depends on MIPS II instruction set */
569 #define mmiowb() asm volatile ("sync" ::: "memory")
570 #endif
571
572 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
573 {
574 memset((void __force *) addr, val, count);
575 }
memcpy_fromio(void * dst,const volatile void __iomem * src,int count)576 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
577 {
578 memcpy(dst, (void __force *) src, count);
579 }
memcpy_toio(volatile void __iomem * dst,const void * src,int count)580 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
581 {
582 memcpy((void __force *) dst, src, count);
583 }
584
585 /*
586 * The caches on some architectures aren't dma-coherent and have need to
587 * handle this in software. There are three types of operations that
588 * can be applied to dma buffers.
589 *
590 * - dma_cache_wback_inv(start, size) makes caches and coherent by
591 * writing the content of the caches back to memory, if necessary.
592 * The function also invalidates the affected part of the caches as
593 * necessary before DMA transfers from outside to memory.
594 * - dma_cache_wback(start, size) makes caches and coherent by
595 * writing the content of the caches back to memory, if necessary.
596 * The function also invalidates the affected part of the caches as
597 * necessary before DMA transfers from outside to memory.
598 * - dma_cache_inv(start, size) invalidates the affected parts of the
599 * caches. Dirty lines of the caches may be written back or simply
600 * be discarded. This operation is necessary before dma operations
601 * to the memory.
602 *
603 * This API used to be exported; it now is for arch code internal use only.
604 */
605 #ifdef CONFIG_DMA_NONCOHERENT
606
607 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
608 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
609 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
610
611 #define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size)
612 #define dma_cache_wback(start, size) _dma_cache_wback(start, size)
613 #define dma_cache_inv(start, size) _dma_cache_inv(start, size)
614
615 #else /* Sane hardware */
616
617 #define dma_cache_wback_inv(start,size) \
618 do { (void) (start); (void) (size); } while (0)
619 #define dma_cache_wback(start,size) \
620 do { (void) (start); (void) (size); } while (0)
621 #define dma_cache_inv(start,size) \
622 do { (void) (start); (void) (size); } while (0)
623
624 #endif /* CONFIG_DMA_NONCOHERENT */
625
626 /*
627 * Read a 32-bit register that requires a 64-bit read cycle on the bus.
628 * Avoid interrupt mucking, just adjust the address for 4-byte access.
629 * Assume the addresses are 8-byte aligned.
630 */
631 #ifdef __MIPSEB__
632 #define __CSR_32_ADJUST 4
633 #else
634 #define __CSR_32_ADJUST 0
635 #endif
636
637 #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
638 #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
639
640 /*
641 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
642 * access
643 */
644 #define xlate_dev_mem_ptr(p) __va(p)
645
646 /*
647 * Convert a virtual cached pointer to an uncached pointer
648 */
649 #define xlate_dev_kmem_ptr(p) p
650
651 void __ioread64_copy(void *to, const void __iomem *from, size_t count);
652
653 #endif /* _ASM_IO_H */
654
