1 /* 2 * Macros for accessing system registers with older binutils. 3 * 4 * Copyright (C) 2014 ARM Ltd. 5 * Author: Catalin Marinas <catalin.marinas@arm.com> 6 * 7 * This program is free software: you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef __ASM_SYSREG_H 21 #define __ASM_SYSREG_H 22 23 #include <asm/compiler.h> 24 #include <linux/stringify.h> 25 26 /* 27 * ARMv8 ARM reserves the following encoding for system registers: 28 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 29 * C5.2, version:ARM DDI 0487A.f) 30 * [20-19] : Op0 31 * [18-16] : Op1 32 * [15-12] : CRn 33 * [11-8] : CRm 34 * [7-5] : Op2 35 */ 36 #define Op0_shift 19 37 #define Op0_mask 0x3 38 #define Op1_shift 16 39 #define Op1_mask 0x7 40 #define CRn_shift 12 41 #define CRn_mask 0xf 42 #define CRm_shift 8 43 #define CRm_mask 0xf 44 #define Op2_shift 5 45 #define Op2_mask 0x7 46 47 #define sys_reg(op0, op1, crn, crm, op2) \ 48 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 49 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ 50 ((op2) << Op2_shift)) 51 52 #define sys_insn sys_reg 53 54 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) 55 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) 56 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) 57 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) 58 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) 59 60 #ifndef CONFIG_BROKEN_GAS_INST 61 62 #ifdef __ASSEMBLY__ 63 #define __emit_inst(x) .inst (x) 64 #else 65 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 66 #endif 67 68 #else /* CONFIG_BROKEN_GAS_INST */ 69 70 #ifndef CONFIG_CPU_BIG_ENDIAN 71 #define __INSTR_BSWAP(x) (x) 72 #else /* CONFIG_CPU_BIG_ENDIAN */ 73 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ 74 (((x) << 8) & 0x00ff0000) | \ 75 (((x) >> 8) & 0x0000ff00) | \ 76 (((x) >> 24) & 0x000000ff)) 77 #endif /* CONFIG_CPU_BIG_ENDIAN */ 78 79 #ifdef __ASSEMBLY__ 80 #define __emit_inst(x) .long __INSTR_BSWAP(x) 81 #else /* __ASSEMBLY__ */ 82 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" 83 #endif /* __ASSEMBLY__ */ 84 85 #endif /* CONFIG_BROKEN_GAS_INST */ 86 87 #define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4) 88 #define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3) 89 90 #define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \ 91 (!!x)<<8 | 0x1f) 92 #define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \ 93 (!!x)<<8 | 0x1f) 94 95 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) 96 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) 97 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) 98 99 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) 100 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) 101 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) 102 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) 103 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) 104 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 105 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 106 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 107 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) 108 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) 109 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) 110 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) 111 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) 112 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) 113 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) 114 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) 115 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) 116 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) 117 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) 118 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) 119 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) 120 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) 121 122 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 123 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 124 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 125 126 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) 127 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) 128 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) 129 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) 130 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) 131 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) 132 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) 133 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) 134 135 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) 136 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) 137 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) 138 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) 139 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) 140 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) 141 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) 142 143 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) 144 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) 145 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) 146 147 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) 148 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 149 #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) 150 151 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 152 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 153 154 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) 155 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) 156 157 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) 158 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) 159 160 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) 161 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) 162 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) 163 164 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0) 165 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 166 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2) 167 168 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) 169 170 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) 171 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) 172 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 173 174 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 175 176 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 177 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 178 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 179 180 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) 181 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) 182 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) 183 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) 184 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) 185 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) 186 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) 187 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) 188 189 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0) 190 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) 191 192 /*** Statistical Profiling Extension ***/ 193 /* ID registers */ 194 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) 195 #define SYS_PMSIDR_EL1_FE_SHIFT 0 196 #define SYS_PMSIDR_EL1_FT_SHIFT 1 197 #define SYS_PMSIDR_EL1_FL_SHIFT 2 198 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 199 #define SYS_PMSIDR_EL1_LDS_SHIFT 4 200 #define SYS_PMSIDR_EL1_ERND_SHIFT 5 201 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 202 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL 203 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 204 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL 205 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 206 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL 207 208 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) 209 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 210 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU 211 #define SYS_PMBIDR_EL1_P_SHIFT 4 212 #define SYS_PMBIDR_EL1_F_SHIFT 5 213 214 /* Sampling controls */ 215 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) 216 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0 217 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1 218 #define SYS_PMSCR_EL1_CX_SHIFT 3 219 #define SYS_PMSCR_EL1_PA_SHIFT 4 220 #define SYS_PMSCR_EL1_TS_SHIFT 5 221 #define SYS_PMSCR_EL1_PCT_SHIFT 6 222 223 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) 224 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 225 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1 226 #define SYS_PMSCR_EL2_CX_SHIFT 3 227 #define SYS_PMSCR_EL2_PA_SHIFT 4 228 #define SYS_PMSCR_EL2_TS_SHIFT 5 229 #define SYS_PMSCR_EL2_PCT_SHIFT 6 230 231 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) 232 233 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) 234 #define SYS_PMSIRR_EL1_RND_SHIFT 0 235 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 236 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL 237 238 /* Filtering controls */ 239 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) 240 #define SYS_PMSFCR_EL1_FE_SHIFT 0 241 #define SYS_PMSFCR_EL1_FT_SHIFT 1 242 #define SYS_PMSFCR_EL1_FL_SHIFT 2 243 #define SYS_PMSFCR_EL1_B_SHIFT 16 244 #define SYS_PMSFCR_EL1_LD_SHIFT 17 245 #define SYS_PMSFCR_EL1_ST_SHIFT 18 246 247 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) 248 #define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL 249 250 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) 251 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 252 253 /* Buffer controls */ 254 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) 255 #define SYS_PMBLIMITR_EL1_E_SHIFT 0 256 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1 257 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL 258 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) 259 260 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) 261 262 /* Buffer error reporting */ 263 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) 264 #define SYS_PMBSR_EL1_COLL_SHIFT 16 265 #define SYS_PMBSR_EL1_S_SHIFT 17 266 #define SYS_PMBSR_EL1_EA_SHIFT 18 267 #define SYS_PMBSR_EL1_DL_SHIFT 19 268 #define SYS_PMBSR_EL1_EC_SHIFT 26 269 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL 270 271 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) 272 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) 273 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) 274 275 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 276 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL 277 278 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 279 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL 280 281 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) 282 283 /*** End of Statistical Profiling Extension ***/ 284 285 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) 286 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) 287 288 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) 289 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) 290 291 #define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0) 292 #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) 293 #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) 294 #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) 295 #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) 296 297 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) 298 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) 299 300 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) 301 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) 302 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) 303 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) 304 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) 305 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) 306 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) 307 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) 308 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) 309 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) 310 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) 311 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) 312 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) 313 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) 314 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 315 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) 316 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 317 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6) 318 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7) 319 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 320 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 321 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) 322 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) 323 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 324 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 325 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) 326 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 327 328 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1) 329 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) 330 331 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) 332 333 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1) 334 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) 335 336 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0) 337 338 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) 339 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) 340 341 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) 342 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 343 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 344 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) 345 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) 346 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) 347 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) 348 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 349 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) 350 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) 351 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) 352 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) 353 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) 354 355 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) 356 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 357 358 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 359 360 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 361 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 362 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 363 364 #define __PMEV_op2(n) ((n) & 0x7) 365 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 366 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 367 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 368 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 369 370 #define SYS_PMCCFILTR_EL0 sys_reg (3, 3, 14, 15, 7) 371 372 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) 373 374 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) 375 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) 376 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) 377 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) 378 379 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) 380 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 381 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 382 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 383 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 384 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 385 386 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 387 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) 388 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) 389 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) 390 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) 391 392 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 393 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 394 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) 395 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) 396 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) 397 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 398 #define SYS_ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5) 399 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) 400 401 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 402 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) 403 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) 404 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) 405 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) 406 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) 407 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) 408 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) 409 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) 410 411 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 412 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) 413 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) 414 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 415 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 416 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 417 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 418 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 419 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 420 421 /* Common SCTLR_ELx flags. */ 422 #define SCTLR_ELx_EE (1 << 25) 423 #define SCTLR_ELx_IESB (1 << 21) 424 #define SCTLR_ELx_WXN (1 << 19) 425 #define SCTLR_ELx_I (1 << 12) 426 #define SCTLR_ELx_SA (1 << 3) 427 #define SCTLR_ELx_C (1 << 2) 428 #define SCTLR_ELx_A (1 << 1) 429 #define SCTLR_ELx_M 1 430 431 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ 432 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB) 433 434 /* SCTLR_EL2 specific flags. */ 435 #define SCTLR_EL2_RES1 ((1 << 4) | (1 << 5) | (1 << 11) | (1 << 16) | \ 436 (1 << 18) | (1 << 22) | (1 << 23) | (1 << 28) | \ 437 (1 << 29)) 438 #define SCTLR_EL2_RES0 ((1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | \ 439 (1 << 10) | (1 << 13) | (1 << 14) | (1 << 15) | \ 440 (1 << 17) | (1 << 20) | (1 << 24) | (1 << 26) | \ 441 (1 << 27) | (1 << 30) | (1 << 31) | \ 442 (0xffffffffUL << 32)) 443 444 #ifdef CONFIG_CPU_BIG_ENDIAN 445 #define ENDIAN_SET_EL2 SCTLR_ELx_EE 446 #define ENDIAN_CLEAR_EL2 0 447 #else 448 #define ENDIAN_SET_EL2 0 449 #define ENDIAN_CLEAR_EL2 SCTLR_ELx_EE 450 #endif 451 452 /* SCTLR_EL2 value used for the hyp-stub */ 453 #define SCTLR_EL2_SET (SCTLR_ELx_IESB | ENDIAN_SET_EL2 | SCTLR_EL2_RES1) 454 #define SCTLR_EL2_CLEAR (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ 455 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_WXN | \ 456 ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0) 457 458 #if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffff 459 #error "Inconsistent SCTLR_EL2 set/clear bits" 460 #endif 461 462 /* SCTLR_EL1 specific flags. */ 463 #define SCTLR_EL1_UCI (1 << 26) 464 #define SCTLR_EL1_E0E (1 << 24) 465 #define SCTLR_EL1_SPAN (1 << 23) 466 #define SCTLR_EL1_NTWE (1 << 18) 467 #define SCTLR_EL1_NTWI (1 << 16) 468 #define SCTLR_EL1_UCT (1 << 15) 469 #define SCTLR_EL1_DZE (1 << 14) 470 #define SCTLR_EL1_UMA (1 << 9) 471 #define SCTLR_EL1_SED (1 << 8) 472 #define SCTLR_EL1_ITD (1 << 7) 473 #define SCTLR_EL1_CP15BEN (1 << 5) 474 #define SCTLR_EL1_SA0 (1 << 4) 475 476 #define SCTLR_EL1_RES1 ((1 << 11) | (1 << 20) | (1 << 22) | (1 << 28) | \ 477 (1 << 29)) 478 #define SCTLR_EL1_RES0 ((1 << 6) | (1 << 10) | (1 << 13) | (1 << 17) | \ 479 (1 << 27) | (1 << 30) | (1 << 31) | \ 480 (0xffffffffUL << 32)) 481 482 #ifdef CONFIG_CPU_BIG_ENDIAN 483 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 484 #define ENDIAN_CLEAR_EL1 0 485 #else 486 #define ENDIAN_SET_EL1 0 487 #define ENDIAN_CLEAR_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 488 #endif 489 490 #define SCTLR_EL1_SET (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA |\ 491 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I |\ 492 SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_NTWI |\ 493 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\ 494 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_RES1) 495 #define SCTLR_EL1_CLEAR (SCTLR_ELx_A | SCTLR_EL1_CP15BEN | SCTLR_EL1_ITD |\ 496 SCTLR_EL1_UMA | SCTLR_ELx_WXN | ENDIAN_CLEAR_EL1 |\ 497 SCTLR_EL1_RES0) 498 499 #if (SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != 0xffffffffffffffff 500 #error "Inconsistent SCTLR_EL1 set/clear bits" 501 #endif 502 503 /* id_aa64isar0 */ 504 #define ID_AA64ISAR0_TS_SHIFT 52 505 #define ID_AA64ISAR0_FHM_SHIFT 48 506 #define ID_AA64ISAR0_DP_SHIFT 44 507 #define ID_AA64ISAR0_SM4_SHIFT 40 508 #define ID_AA64ISAR0_SM3_SHIFT 36 509 #define ID_AA64ISAR0_SHA3_SHIFT 32 510 #define ID_AA64ISAR0_RDM_SHIFT 28 511 #define ID_AA64ISAR0_ATOMICS_SHIFT 20 512 #define ID_AA64ISAR0_CRC32_SHIFT 16 513 #define ID_AA64ISAR0_SHA2_SHIFT 12 514 #define ID_AA64ISAR0_SHA1_SHIFT 8 515 #define ID_AA64ISAR0_AES_SHIFT 4 516 517 /* id_aa64isar1 */ 518 #define ID_AA64ISAR1_LRCPC_SHIFT 20 519 #define ID_AA64ISAR1_FCMA_SHIFT 16 520 #define ID_AA64ISAR1_JSCVT_SHIFT 12 521 #define ID_AA64ISAR1_DPB_SHIFT 0 522 523 /* id_aa64pfr0 */ 524 #define ID_AA64PFR0_CSV3_SHIFT 60 525 #define ID_AA64PFR0_CSV2_SHIFT 56 526 #define ID_AA64PFR0_DIT_SHIFT 48 527 #define ID_AA64PFR0_SVE_SHIFT 32 528 #define ID_AA64PFR0_RAS_SHIFT 28 529 #define ID_AA64PFR0_GIC_SHIFT 24 530 #define ID_AA64PFR0_ASIMD_SHIFT 20 531 #define ID_AA64PFR0_FP_SHIFT 16 532 #define ID_AA64PFR0_EL3_SHIFT 12 533 #define ID_AA64PFR0_EL2_SHIFT 8 534 #define ID_AA64PFR0_EL1_SHIFT 4 535 #define ID_AA64PFR0_EL0_SHIFT 0 536 537 #define ID_AA64PFR0_SVE 0x1 538 #define ID_AA64PFR0_RAS_V1 0x1 539 #define ID_AA64PFR0_FP_NI 0xf 540 #define ID_AA64PFR0_FP_SUPPORTED 0x0 541 #define ID_AA64PFR0_ASIMD_NI 0xf 542 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 543 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1 544 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 545 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 546 547 /* id_aa64mmfr0 */ 548 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 549 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 550 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 551 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 552 #define ID_AA64MMFR0_SNSMEM_SHIFT 12 553 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8 554 #define ID_AA64MMFR0_ASID_SHIFT 4 555 #define ID_AA64MMFR0_PARANGE_SHIFT 0 556 557 #define ID_AA64MMFR0_TGRAN4_NI 0xf 558 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 559 #define ID_AA64MMFR0_TGRAN64_NI 0xf 560 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 561 #define ID_AA64MMFR0_TGRAN16_NI 0x0 562 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 563 #define ID_AA64MMFR0_PARANGE_48 0x5 564 #define ID_AA64MMFR0_PARANGE_52 0x6 565 566 #ifdef CONFIG_ARM64_PA_BITS_52 567 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52 568 #else 569 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48 570 #endif 571 572 /* id_aa64mmfr1 */ 573 #define ID_AA64MMFR1_PAN_SHIFT 20 574 #define ID_AA64MMFR1_LOR_SHIFT 16 575 #define ID_AA64MMFR1_HPD_SHIFT 12 576 #define ID_AA64MMFR1_VHE_SHIFT 8 577 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 578 #define ID_AA64MMFR1_HADBS_SHIFT 0 579 580 #define ID_AA64MMFR1_VMIDBITS_8 0 581 #define ID_AA64MMFR1_VMIDBITS_16 2 582 583 /* id_aa64mmfr2 */ 584 #define ID_AA64MMFR2_FWB_SHIFT 40 585 #define ID_AA64MMFR2_AT_SHIFT 32 586 #define ID_AA64MMFR2_LVA_SHIFT 16 587 #define ID_AA64MMFR2_IESB_SHIFT 12 588 #define ID_AA64MMFR2_LSM_SHIFT 8 589 #define ID_AA64MMFR2_UAO_SHIFT 4 590 #define ID_AA64MMFR2_CNP_SHIFT 0 591 592 /* id_aa64dfr0 */ 593 #define ID_AA64DFR0_PMSVER_SHIFT 32 594 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 595 #define ID_AA64DFR0_WRPS_SHIFT 20 596 #define ID_AA64DFR0_BRPS_SHIFT 12 597 #define ID_AA64DFR0_PMUVER_SHIFT 8 598 #define ID_AA64DFR0_TRACEVER_SHIFT 4 599 #define ID_AA64DFR0_DEBUGVER_SHIFT 0 600 601 #define ID_ISAR5_RDM_SHIFT 24 602 #define ID_ISAR5_CRC32_SHIFT 16 603 #define ID_ISAR5_SHA2_SHIFT 12 604 #define ID_ISAR5_SHA1_SHIFT 8 605 #define ID_ISAR5_AES_SHIFT 4 606 #define ID_ISAR5_SEVL_SHIFT 0 607 608 #define MVFR0_FPROUND_SHIFT 28 609 #define MVFR0_FPSHVEC_SHIFT 24 610 #define MVFR0_FPSQRT_SHIFT 20 611 #define MVFR0_FPDIVIDE_SHIFT 16 612 #define MVFR0_FPTRAP_SHIFT 12 613 #define MVFR0_FPDP_SHIFT 8 614 #define MVFR0_FPSP_SHIFT 4 615 #define MVFR0_SIMD_SHIFT 0 616 617 #define MVFR1_SIMDFMAC_SHIFT 28 618 #define MVFR1_FPHP_SHIFT 24 619 #define MVFR1_SIMDHP_SHIFT 20 620 #define MVFR1_SIMDSP_SHIFT 16 621 #define MVFR1_SIMDINT_SHIFT 12 622 #define MVFR1_SIMDLS_SHIFT 8 623 #define MVFR1_FPDNAN_SHIFT 4 624 #define MVFR1_FPFTZ_SHIFT 0 625 626 627 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 628 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 629 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 630 631 #define ID_AA64MMFR0_TGRAN4_NI 0xf 632 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 633 #define ID_AA64MMFR0_TGRAN64_NI 0xf 634 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 635 #define ID_AA64MMFR0_TGRAN16_NI 0x0 636 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 637 638 #if defined(CONFIG_ARM64_4K_PAGES) 639 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT 640 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED 641 #elif defined(CONFIG_ARM64_16K_PAGES) 642 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT 643 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED 644 #elif defined(CONFIG_ARM64_64K_PAGES) 645 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT 646 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED 647 #endif 648 649 650 /* 651 * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which 652 * are reserved by the SVE architecture for future expansion of the LEN 653 * field, with compatible semantics. 654 */ 655 #define ZCR_ELx_LEN_SHIFT 0 656 #define ZCR_ELx_LEN_SIZE 9 657 #define ZCR_ELx_LEN_MASK 0x1ff 658 659 #define CPACR_EL1_ZEN_EL1EN (1 << 16) /* enable EL1 access */ 660 #define CPACR_EL1_ZEN_EL0EN (1 << 17) /* enable EL0 access, if EL1EN set */ 661 #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) 662 663 664 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ 665 #define SYS_MPIDR_SAFE_VAL (1UL << 31) 666 667 #ifdef __ASSEMBLY__ 668 669 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 670 .equ .L__reg_num_x\num, \num 671 .endr 672 .equ .L__reg_num_xzr, 31 673 674 .macro mrs_s, rt, sreg 675 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt)) 676 .endm 677 678 .macro msr_s, sreg, rt 679 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt)) 680 .endm 681 682 #else 683 684 #include <linux/build_bug.h> 685 #include <linux/types.h> 686 687 asm( 688 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" 689 " .equ .L__reg_num_x\\num, \\num\n" 690 " .endr\n" 691 " .equ .L__reg_num_xzr, 31\n" 692 "\n" 693 " .macro mrs_s, rt, sreg\n" 694 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) 695 " .endm\n" 696 "\n" 697 " .macro msr_s, sreg, rt\n" 698 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) 699 " .endm\n" 700 ); 701 702 /* 703 * Unlike read_cpuid, calls to read_sysreg are never expected to be 704 * optimized away or replaced with synthetic values. 705 */ 706 #define read_sysreg(r) ({ \ 707 u64 __val; \ 708 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 709 __val; \ 710 }) 711 712 /* 713 * The "Z" constraint normally means a zero immediate, but when combined with 714 * the "%x0" template means XZR. 715 */ 716 #define write_sysreg(v, r) do { \ 717 u64 __val = (u64)(v); \ 718 asm volatile("msr " __stringify(r) ", %x0" \ 719 : : "rZ" (__val)); \ 720 } while (0) 721 722 /* 723 * For registers without architectural names, or simply unsupported by 724 * GAS. 725 */ 726 #define read_sysreg_s(r) ({ \ 727 u64 __val; \ 728 asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val)); \ 729 __val; \ 730 }) 731 732 #define write_sysreg_s(v, r) do { \ 733 u64 __val = (u64)(v); \ 734 asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \ 735 } while (0) 736 737 /* 738 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the 739 * set mask are set. Other bits are left as-is. 740 */ 741 #define sysreg_clear_set(sysreg, clear, set) do { \ 742 u64 __scs_val = read_sysreg(sysreg); \ 743 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 744 if (__scs_new != __scs_val) \ 745 write_sysreg(__scs_new, sysreg); \ 746 } while (0) 747 748 #endif 749 750 #endif /* __ASM_SYSREG_H */ 751
