1 /*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 /*
18 * This machine is known as:
19 * - i.MX27 3-Stack Development System
20 * - i.MX27 Platform Development Kit (i.MX27 PDK)
21 */
22
23 #include <linux/platform_device.h>
24 #include <linux/gpio.h>
25 #include <linux/irq.h>
26 #include <linux/usb/otg.h>
27 #include <linux/usb/ulpi.h>
28 #include <linux/delay.h>
29 #include <linux/mfd/mc13783.h>
30 #include <linux/spi/spi.h>
31 #include <linux/regulator/machine.h>
32 #include <linux/spi/l4f00242t03.h>
33
34
35 #include <asm/mach-types.h>
36 #include <asm/mach/arch.h>
37 #include <asm/mach/time.h>
38
39 #include "3ds_debugboard.h"
40 #include "common.h"
41 #include "devices-imx27.h"
42 #include "ehci.h"
43 #include "hardware.h"
44 #include "iomux-mx27.h"
45 #include "ulpi.h"
46
47 #define SD1_EN_GPIO IMX_GPIO_NR(2, 25)
48 #define OTG_PHY_RESET_GPIO IMX_GPIO_NR(2, 23)
49 #define SPI2_SS0 IMX_GPIO_NR(4, 21)
50 #define PMIC_INT IMX_GPIO_NR(3, 14)
51 #define SPI1_SS0 IMX_GPIO_NR(4, 28)
52 #define SD1_CD IMX_GPIO_NR(2, 26)
53 #define LCD_RESET IMX_GPIO_NR(1, 3)
54 #define LCD_ENABLE IMX_GPIO_NR(1, 31)
55
56 static const int mx27pdk_pins[] __initconst = {
57 /* UART1 */
58 PE12_PF_UART1_TXD,
59 PE13_PF_UART1_RXD,
60 PE14_PF_UART1_CTS,
61 PE15_PF_UART1_RTS,
62 /* FEC */
63 PD0_AIN_FEC_TXD0,
64 PD1_AIN_FEC_TXD1,
65 PD2_AIN_FEC_TXD2,
66 PD3_AIN_FEC_TXD3,
67 PD4_AOUT_FEC_RX_ER,
68 PD5_AOUT_FEC_RXD1,
69 PD6_AOUT_FEC_RXD2,
70 PD7_AOUT_FEC_RXD3,
71 PD8_AF_FEC_MDIO,
72 PD9_AIN_FEC_MDC,
73 PD10_AOUT_FEC_CRS,
74 PD11_AOUT_FEC_TX_CLK,
75 PD12_AOUT_FEC_RXD0,
76 PD13_AOUT_FEC_RX_DV,
77 PD14_AOUT_FEC_RX_CLK,
78 PD15_AOUT_FEC_COL,
79 PD16_AIN_FEC_TX_ER,
80 PF23_AIN_FEC_TX_EN,
81 /* SDHC1 */
82 PE18_PF_SD1_D0,
83 PE19_PF_SD1_D1,
84 PE20_PF_SD1_D2,
85 PE21_PF_SD1_D3,
86 PE22_PF_SD1_CMD,
87 PE23_PF_SD1_CLK,
88 SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT,
89 /* OTG */
90 OTG_PHY_RESET_GPIO | GPIO_GPIO | GPIO_OUT,
91 PC7_PF_USBOTG_DATA5,
92 PC8_PF_USBOTG_DATA6,
93 PC9_PF_USBOTG_DATA0,
94 PC10_PF_USBOTG_DATA2,
95 PC11_PF_USBOTG_DATA1,
96 PC12_PF_USBOTG_DATA4,
97 PC13_PF_USBOTG_DATA3,
98 PE0_PF_USBOTG_NXT,
99 PE1_PF_USBOTG_STP,
100 PE2_PF_USBOTG_DIR,
101 PE24_PF_USBOTG_CLK,
102 PE25_PF_USBOTG_DATA7,
103 /* CSPI1 */
104 PD31_PF_CSPI1_MOSI,
105 PD30_PF_CSPI1_MISO,
106 PD29_PF_CSPI1_SCLK,
107 PD25_PF_CSPI1_RDY,
108 SPI1_SS0 | GPIO_GPIO | GPIO_OUT,
109 /* CSPI2 */
110 PD22_PF_CSPI2_SCLK,
111 PD23_PF_CSPI2_MISO,
112 PD24_PF_CSPI2_MOSI,
113 SPI2_SS0 | GPIO_GPIO | GPIO_OUT,
114 /* I2C1 */
115 PD17_PF_I2C_DATA,
116 PD18_PF_I2C_CLK,
117 /* PMIC INT */
118 PMIC_INT | GPIO_GPIO | GPIO_IN,
119 /* LCD */
120 PA5_PF_LSCLK,
121 PA6_PF_LD0,
122 PA7_PF_LD1,
123 PA8_PF_LD2,
124 PA9_PF_LD3,
125 PA10_PF_LD4,
126 PA11_PF_LD5,
127 PA12_PF_LD6,
128 PA13_PF_LD7,
129 PA14_PF_LD8,
130 PA15_PF_LD9,
131 PA16_PF_LD10,
132 PA17_PF_LD11,
133 PA18_PF_LD12,
134 PA19_PF_LD13,
135 PA20_PF_LD14,
136 PA21_PF_LD15,
137 PA22_PF_LD16,
138 PA23_PF_LD17,
139 PA28_PF_HSYNC,
140 PA29_PF_VSYNC,
141 PA30_PF_CONTRAST,
142 LCD_ENABLE | GPIO_GPIO | GPIO_OUT,
143 LCD_RESET | GPIO_GPIO | GPIO_OUT,
144 /* SSI4 */
145 PC16_PF_SSI4_FS,
146 PC17_PF_SSI4_RXD,
147 PC18_PF_SSI4_TXD,
148 PC19_PF_SSI4_CLK,
149 };
150
151 static const struct imxuart_platform_data uart_pdata __initconst = {
152 .flags = IMXUART_HAVE_RTSCTS,
153 };
154
155 /*
156 * Matrix keyboard
157 */
158
159 static const uint32_t mx27_3ds_keymap[] = {
160 KEY(0, 0, KEY_UP),
161 KEY(0, 1, KEY_DOWN),
162 KEY(1, 0, KEY_RIGHT),
163 KEY(1, 1, KEY_LEFT),
164 KEY(1, 2, KEY_ENTER),
165 KEY(2, 0, KEY_F6),
166 KEY(2, 1, KEY_F8),
167 KEY(2, 2, KEY_F9),
168 KEY(2, 3, KEY_F10),
169 };
170
171 static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = {
172 .keymap = mx27_3ds_keymap,
173 .keymap_size = ARRAY_SIZE(mx27_3ds_keymap),
174 };
175
mx27_3ds_sdhc1_init(struct device * dev,irq_handler_t detect_irq,void * data)176 static int mx27_3ds_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
177 void *data)
178 {
179 return request_irq(gpio_to_irq(SD1_CD), detect_irq,
180 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
181 }
182
mx27_3ds_sdhc1_exit(struct device * dev,void * data)183 static void mx27_3ds_sdhc1_exit(struct device *dev, void *data)
184 {
185 free_irq(gpio_to_irq(SD1_CD), data);
186 }
187
188 static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
189 .init = mx27_3ds_sdhc1_init,
190 .exit = mx27_3ds_sdhc1_exit,
191 };
192
mx27_3ds_sdhc1_enable_level_translator(void)193 static void mx27_3ds_sdhc1_enable_level_translator(void)
194 {
195 /* Turn on TXB0108 OE pin */
196 gpio_request(SD1_EN_GPIO, "sd1_enable");
197 gpio_direction_output(SD1_EN_GPIO, 1);
198 }
199
200
otg_phy_init(void)201 static int otg_phy_init(void)
202 {
203 gpio_request(OTG_PHY_RESET_GPIO, "usb-otg-reset");
204 gpio_direction_output(OTG_PHY_RESET_GPIO, 0);
205 mdelay(1);
206 gpio_set_value(OTG_PHY_RESET_GPIO, 1);
207 return 0;
208 }
209
mx27_3ds_otg_init(struct platform_device * pdev)210 static int mx27_3ds_otg_init(struct platform_device *pdev)
211 {
212 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
213 }
214
215 static struct mxc_usbh_platform_data otg_pdata __initdata = {
216 .init = mx27_3ds_otg_init,
217 .portsc = MXC_EHCI_MODE_ULPI,
218 };
219
220 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
221 .operating_mode = FSL_USB2_DR_DEVICE,
222 .phy_mode = FSL_USB2_PHY_ULPI,
223 };
224
225 static bool otg_mode_host __initdata;
226
mx27_3ds_otg_mode(char * options)227 static int __init mx27_3ds_otg_mode(char *options)
228 {
229 if (!strcmp(options, "host"))
230 otg_mode_host = true;
231 else if (!strcmp(options, "device"))
232 otg_mode_host = false;
233 else
234 pr_info("otg_mode neither \"host\" nor \"device\". "
235 "Defaulting to device\n");
236 return 1;
237 }
238 __setup("otg_mode=", mx27_3ds_otg_mode);
239
240 /* Regulators */
241 static struct regulator_init_data gpo_init = {
242 .constraints = {
243 .boot_on = 1,
244 .always_on = 1,
245 }
246 };
247
248 static struct regulator_consumer_supply vmmc1_consumers[] = {
249 REGULATOR_SUPPLY("vcore", "spi0.0"),
250 };
251
252 static struct regulator_init_data vmmc1_init = {
253 .constraints = {
254 .min_uV = 2800000,
255 .max_uV = 2800000,
256 .apply_uV = 1,
257 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
258 REGULATOR_CHANGE_STATUS,
259 },
260 .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
261 .consumer_supplies = vmmc1_consumers,
262 };
263
264 static struct regulator_consumer_supply vgen_consumers[] = {
265 REGULATOR_SUPPLY("vdd", "spi0.0"),
266 };
267
268 static struct regulator_init_data vgen_init = {
269 .constraints = {
270 .min_uV = 1800000,
271 .max_uV = 1800000,
272 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
273 },
274 .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
275 .consumer_supplies = vgen_consumers,
276 };
277
278 static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
279 {
280 .id = MC13783_REG_VMMC1,
281 .init_data = &vmmc1_init,
282 }, {
283 .id = MC13783_REG_VGEN,
284 .init_data = &vgen_init,
285 }, {
286 .id = MC13783_REG_GPO1, /* Turn on 1.8V */
287 .init_data = &gpo_init,
288 }, {
289 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
290 .init_data = &gpo_init,
291 },
292 };
293
294 /* MC13783 */
295 static struct mc13xxx_codec_platform_data mx27_3ds_codec = {
296 .dac_ssi_port = MC13783_SSI1_PORT,
297 .adc_ssi_port = MC13783_SSI1_PORT,
298 };
299
300 static struct mc13xxx_platform_data mc13783_pdata = {
301 .regulators = {
302 .regulators = mx27_3ds_regulators,
303 .num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
304
305 },
306 .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC |
307 MC13XXX_USE_CODEC,
308 .codec = &mx27_3ds_codec,
309 };
310
311 static struct imx_ssi_platform_data mx27_3ds_ssi_pdata = {
312 .flags = IMX_SSI_DMA | IMX_SSI_NET,
313 };
314
315 /* SPI */
316 static int spi1_chipselect[] = {SPI1_SS0};
317
318 static const struct spi_imx_master spi1_pdata __initconst = {
319 .chipselect = spi1_chipselect,
320 .num_chipselect = ARRAY_SIZE(spi1_chipselect),
321 };
322
323 static int spi2_chipselect[] = {SPI2_SS0};
324
325 static const struct spi_imx_master spi2_pdata __initconst = {
326 .chipselect = spi2_chipselect,
327 .num_chipselect = ARRAY_SIZE(spi2_chipselect),
328 };
329
330 static struct imx_fb_videomode mx27_3ds_modes[] = {
331 { /* 480x640 @ 60 Hz */
332 .mode = {
333 .name = "Epson-VGA",
334 .refresh = 60,
335 .xres = 480,
336 .yres = 640,
337 .pixclock = 41701,
338 .left_margin = 20,
339 .right_margin = 41,
340 .upper_margin = 10,
341 .lower_margin = 5,
342 .hsync_len = 20,
343 .vsync_len = 10,
344 .sync = FB_SYNC_OE_ACT_HIGH |
345 FB_SYNC_CLK_INVERT,
346 .vmode = FB_VMODE_NONINTERLACED,
347 .flag = 0,
348 },
349 .bpp = 16,
350 .pcr = 0xFAC08B82,
351 },
352 };
353
354 static const struct imx_fb_platform_data mx27_3ds_fb_data __initconst = {
355 .mode = mx27_3ds_modes,
356 .num_modes = ARRAY_SIZE(mx27_3ds_modes),
357 .pwmr = 0x00A903FF,
358 .lscr1 = 0x00120300,
359 .dmacr = 0x00020010,
360 };
361
362 /* LCD */
363 static struct l4f00242t03_pdata mx27_3ds_lcd_pdata = {
364 .reset_gpio = LCD_RESET,
365 .data_enable_gpio = LCD_ENABLE,
366 };
367
368 static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
369 {
370 .modalias = "mc13783",
371 .max_speed_hz = 1000000,
372 .bus_num = 1,
373 .chip_select = 0, /* SS0 */
374 .platform_data = &mc13783_pdata,
375 /* irq number is run-time assigned */
376 .mode = SPI_CS_HIGH,
377 }, {
378 .modalias = "l4f00242t03",
379 .max_speed_hz = 5000000,
380 .bus_num = 0,
381 .chip_select = 0, /* SS0 */
382 .platform_data = &mx27_3ds_lcd_pdata,
383 },
384 };
385
386 static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = {
387 .bitrate = 100000,
388 };
389
mx27pdk_init(void)390 static void __init mx27pdk_init(void)
391 {
392 imx27_soc_init();
393
394 mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
395 "mx27pdk");
396 imx27_add_imx_uart0(&uart_pdata);
397 imx27_add_fec(NULL);
398 imx27_add_imx_keypad(&mx27_3ds_keymap_data);
399 imx27_add_imx2_wdt();
400
401 imx27_add_spi_imx1(&spi2_pdata);
402 imx27_add_spi_imx0(&spi1_pdata);
403
404 imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
405 imx27_add_imx_fb(&mx27_3ds_fb_data);
406
407 imx27_add_imx_ssi(0, &mx27_3ds_ssi_pdata);
408 }
409
mx27pdk_late_init(void)410 static void __init mx27pdk_late_init(void)
411 {
412 mx27_3ds_sdhc1_enable_level_translator();
413 imx27_add_mxc_mmc(0, &sdhc1_pdata);
414
415 otg_phy_init();
416
417 if (otg_mode_host) {
418 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
419 ULPI_OTG_DRVVBUS_EXT);
420
421 if (otg_pdata.otg)
422 imx27_add_mxc_ehci_otg(&otg_pdata);
423 }
424
425 if (!otg_mode_host)
426 imx27_add_fsl_usb2_udc(&otg_device_pdata);
427
428 mx27_3ds_spi_devs[0].irq = gpio_to_irq(PMIC_INT);
429 spi_register_board_info(mx27_3ds_spi_devs,
430 ARRAY_SIZE(mx27_3ds_spi_devs));
431
432 if (mxc_expio_init(MX27_CS5_BASE_ADDR, IMX_GPIO_NR(3, 28)))
433 pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
434
435
436 imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
437 }
438
mx27pdk_timer_init(void)439 static void __init mx27pdk_timer_init(void)
440 {
441 mx27_clocks_init(26000000);
442 }
443
444 MACHINE_START(MX27_3DS, "Freescale MX27PDK")
445 /* maintainer: Freescale Semiconductor, Inc. */
446 .atag_offset = 0x100,
447 .map_io = mx27_map_io,
448 .init_early = imx27_init_early,
449 .init_irq = mx27_init_irq,
450 .init_time = mx27pdk_timer_init,
451 .init_machine = mx27pdk_init,
452 .init_late = mx27pdk_late_init,
453 .restart = mxc_restart,
454 MACHINE_END
455
