1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Common defines for v7m cpus 4 */ 5 #define V7M_SCS_ICTR IOMEM(0xe000e004) 6 #define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f 7 8 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00) 9 10 #define V7M_SCB_CPUID 0x00 11 12 #define V7M_SCB_ICSR 0x04 13 #define V7M_SCB_ICSR_PENDSVSET (1 << 28) 14 #define V7M_SCB_ICSR_PENDSVCLR (1 << 27) 15 #define V7M_SCB_ICSR_RETTOBASE (1 << 11) 16 17 #define V7M_SCB_VTOR 0x08 18 19 #define V7M_SCB_AIRCR 0x0c 20 #define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16) 21 #define V7M_SCB_AIRCR_SYSRESETREQ (1 << 2) 22 23 #define V7M_SCB_SCR 0x10 24 #define V7M_SCB_SCR_SLEEPDEEP (1 << 2) 25 26 #define V7M_SCB_CCR 0x14 27 #define V7M_SCB_CCR_STKALIGN (1 << 9) 28 #define V7M_SCB_CCR_DC (1 << 16) 29 #define V7M_SCB_CCR_IC (1 << 17) 30 #define V7M_SCB_CCR_BP (1 << 18) 31 32 #define V7M_SCB_SHPR2 0x1c 33 #define V7M_SCB_SHPR3 0x20 34 35 #define V7M_SCB_SHCSR 0x24 36 #define V7M_SCB_SHCSR_USGFAULTENA (1 << 18) 37 #define V7M_SCB_SHCSR_BUSFAULTENA (1 << 17) 38 #define V7M_SCB_SHCSR_MEMFAULTENA (1 << 16) 39 40 #define V7M_xPSR_FRAMEPTRALIGN 0x00000200 41 #define V7M_xPSR_EXCEPTIONNO 0x000001ff 42 43 /* 44 * When branching to an address that has bits [31:28] == 0xf an exception return 45 * occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP 46 * extension Bit [4] defines if the exception frame has space allocated for FP 47 * state information, SBOP otherwise. Bit [3] defines the mode that is returned 48 * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used 49 * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01. 50 */ 51 #define EXC_RET_STACK_MASK 0x00000004 52 #define EXC_RET_THREADMODE_PROCESSSTACK 0xfffffffd 53 54 /* Cache related definitions */ 55 56 #define V7M_SCB_CLIDR 0x78 /* Cache Level ID register */ 57 #define V7M_SCB_CTR 0x7c /* Cache Type register */ 58 #define V7M_SCB_CCSIDR 0x80 /* Cache size ID register */ 59 #define V7M_SCB_CSSELR 0x84 /* Cache size selection register */ 60 61 /* Memory-mapped MPU registers for M-class */ 62 #define MPU_TYPE 0x90 63 #define MPU_CTRL 0x94 64 #define MPU_CTRL_ENABLE 1 65 #define MPU_CTRL_PRIVDEFENA (1 << 2) 66 67 #define PMSAv7_RNR 0x98 68 #define PMSAv7_RBAR 0x9c 69 #define PMSAv7_RASR 0xa0 70 71 #define PMSAv8_RNR 0x98 72 #define PMSAv8_RBAR 0x9c 73 #define PMSAv8_RLAR 0xa0 74 #define PMSAv8_RBAR_A(n) (PMSAv8_RBAR + 8*(n)) 75 #define PMSAv8_RLAR_A(n) (PMSAv8_RLAR + 8*(n)) 76 #define PMSAv8_MAIR0 0xc0 77 #define PMSAv8_MAIR1 0xc4 78 79 /* Cache opeartions */ 80 #define V7M_SCB_ICIALLU 0x250 /* I-cache invalidate all to PoU */ 81 #define V7M_SCB_ICIMVAU 0x258 /* I-cache invalidate by MVA to PoU */ 82 #define V7M_SCB_DCIMVAC 0x25c /* D-cache invalidate by MVA to PoC */ 83 #define V7M_SCB_DCISW 0x260 /* D-cache invalidate by set-way */ 84 #define V7M_SCB_DCCMVAU 0x264 /* D-cache clean by MVA to PoU */ 85 #define V7M_SCB_DCCMVAC 0x268 /* D-cache clean by MVA to PoC */ 86 #define V7M_SCB_DCCSW 0x26c /* D-cache clean by set-way */ 87 #define V7M_SCB_DCCIMVAC 0x270 /* D-cache clean and invalidate by MVA to PoC */ 88 #define V7M_SCB_DCCISW 0x274 /* D-cache clean and invalidate by set-way */ 89 #define V7M_SCB_BPIALL 0x278 /* D-cache clean and invalidate by set-way */ 90 91 #ifndef __ASSEMBLY__ 92 93 enum reboot_mode; 94 95 void armv7m_restart(enum reboot_mode mode, const char *cmd); 96 97 #endif /* __ASSEMBLY__ */ 98
