1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <dt-bindings/clock/rk3288-cru.h> 8#include <dt-bindings/power/rk3288-power.h> 9#include <dt-bindings/thermal/thermal.h> 10#include <dt-bindings/power/rk3288-power.h> 11#include <dt-bindings/soc/rockchip,boot-mode.h> 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 compatible = "rockchip,rk3288"; 18 19 interrupt-parent = <&gic>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 mshc0 = &emmc; 30 mshc1 = &sdmmc; 31 mshc2 = &sdio0; 32 mshc3 = &sdio1; 33 serial0 = &uart0; 34 serial1 = &uart1; 35 serial2 = &uart2; 36 serial3 = &uart3; 37 serial4 = &uart4; 38 spi0 = &spi0; 39 spi1 = &spi1; 40 spi2 = &spi2; 41 }; 42 43 arm-pmu { 44 compatible = "arm,cortex-a12-pmu"; 45 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 49 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 50 }; 51 52 cpus { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 enable-method = "rockchip,rk3066-smp"; 56 rockchip,pmu = <&pmu>; 57 58 cpu0: cpu@500 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a12"; 61 reg = <0x500>; 62 resets = <&cru SRST_CORE0>; 63 operating-points-v2 = <&cpu_opp_table>; 64 #cooling-cells = <2>; /* min followed by max */ 65 clock-latency = <40000>; 66 clocks = <&cru ARMCLK>; 67 }; 68 cpu1: cpu@501 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a12"; 71 reg = <0x501>; 72 resets = <&cru SRST_CORE1>; 73 operating-points = <&cpu_opp_table>; 74 #cooling-cells = <2>; /* min followed by max */ 75 clock-latency = <40000>; 76 clocks = <&cru ARMCLK>; 77 }; 78 cpu2: cpu@502 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a12"; 81 reg = <0x502>; 82 resets = <&cru SRST_CORE2>; 83 operating-points = <&cpu_opp_table>; 84 #cooling-cells = <2>; /* min followed by max */ 85 clock-latency = <40000>; 86 clocks = <&cru ARMCLK>; 87 }; 88 cpu3: cpu@503 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a12"; 91 reg = <0x503>; 92 resets = <&cru SRST_CORE3>; 93 operating-points = <&cpu_opp_table>; 94 #cooling-cells = <2>; /* min followed by max */ 95 clock-latency = <40000>; 96 clocks = <&cru ARMCLK>; 97 }; 98 }; 99 100 cpu_opp_table: cpu-opp-table { 101 compatible = "operating-points-v2"; 102 opp-shared; 103 104 opp-126000000 { 105 opp-hz = /bits/ 64 <126000000>; 106 opp-microvolt = <900000>; 107 }; 108 opp-216000000 { 109 opp-hz = /bits/ 64 <216000000>; 110 opp-microvolt = <900000>; 111 }; 112 opp-312000000 { 113 opp-hz = /bits/ 64 <312000000>; 114 opp-microvolt = <900000>; 115 }; 116 opp-408000000 { 117 opp-hz = /bits/ 64 <408000000>; 118 opp-microvolt = <900000>; 119 }; 120 opp-600000000 { 121 opp-hz = /bits/ 64 <600000000>; 122 opp-microvolt = <900000>; 123 }; 124 opp-696000000 { 125 opp-hz = /bits/ 64 <696000000>; 126 opp-microvolt = <950000>; 127 }; 128 opp-816000000 { 129 opp-hz = /bits/ 64 <816000000>; 130 opp-microvolt = <1000000>; 131 }; 132 opp-1008000000 { 133 opp-hz = /bits/ 64 <1008000000>; 134 opp-microvolt = <1050000>; 135 }; 136 opp-1200000000 { 137 opp-hz = /bits/ 64 <1200000000>; 138 opp-microvolt = <1100000>; 139 }; 140 opp-1416000000 { 141 opp-hz = /bits/ 64 <1416000000>; 142 opp-microvolt = <1200000>; 143 }; 144 opp-1512000000 { 145 opp-hz = /bits/ 64 <1512000000>; 146 opp-microvolt = <1300000>; 147 }; 148 opp-1608000000 { 149 opp-hz = /bits/ 64 <1608000000>; 150 opp-microvolt = <1350000>; 151 }; 152 }; 153 154 amba { 155 compatible = "simple-bus"; 156 #address-cells = <2>; 157 #size-cells = <2>; 158 ranges; 159 160 dmac_peri: dma-controller@ff250000 { 161 compatible = "arm,pl330", "arm,primecell"; 162 reg = <0x0 0xff250000 0x0 0x4000>; 163 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 165 #dma-cells = <1>; 166 arm,pl330-broken-no-flushp; 167 clocks = <&cru ACLK_DMAC2>; 168 clock-names = "apb_pclk"; 169 }; 170 171 dmac_bus_ns: dma-controller@ff600000 { 172 compatible = "arm,pl330", "arm,primecell"; 173 reg = <0x0 0xff600000 0x0 0x4000>; 174 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 176 #dma-cells = <1>; 177 arm,pl330-broken-no-flushp; 178 clocks = <&cru ACLK_DMAC1>; 179 clock-names = "apb_pclk"; 180 status = "disabled"; 181 }; 182 183 dmac_bus_s: dma-controller@ffb20000 { 184 compatible = "arm,pl330", "arm,primecell"; 185 reg = <0x0 0xffb20000 0x0 0x4000>; 186 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 188 #dma-cells = <1>; 189 arm,pl330-broken-no-flushp; 190 clocks = <&cru ACLK_DMAC1>; 191 clock-names = "apb_pclk"; 192 }; 193 }; 194 195 reserved-memory { 196 #address-cells = <2>; 197 #size-cells = <2>; 198 ranges; 199 200 /* 201 * The rk3288 cannot use the memory area above 0xfe000000 202 * for dma operations for some reason. While there is 203 * probably a better solution available somewhere, we 204 * haven't found it yet and while devices with 2GB of ram 205 * are not affected, this issue prevents 4GB from booting. 206 * So to make these devices at least bootable, block 207 * this area for the time being until the real solution 208 * is found. 209 */ 210 dma-unusable@fe000000 { 211 reg = <0x0 0xfe000000 0x0 0x1000000>; 212 }; 213 }; 214 215 xin24m: oscillator { 216 compatible = "fixed-clock"; 217 clock-frequency = <24000000>; 218 clock-output-names = "xin24m"; 219 #clock-cells = <0>; 220 }; 221 222 timer { 223 compatible = "arm,armv7-timer"; 224 arm,cpu-registers-not-fw-configured; 225 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 226 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 227 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 228 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 229 clock-frequency = <24000000>; 230 }; 231 232 timer: timer@ff810000 { 233 compatible = "rockchip,rk3288-timer"; 234 reg = <0x0 0xff810000 0x0 0x20>; 235 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&xin24m>, <&cru PCLK_TIMER>; 237 clock-names = "timer", "pclk"; 238 }; 239 240 display-subsystem { 241 compatible = "rockchip,display-subsystem"; 242 ports = <&vopl_out>, <&vopb_out>; 243 }; 244 245 sdmmc: dwmmc@ff0c0000 { 246 compatible = "rockchip,rk3288-dw-mshc"; 247 max-frequency = <150000000>; 248 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 249 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 250 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 251 fifo-depth = <0x100>; 252 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 253 reg = <0x0 0xff0c0000 0x0 0x4000>; 254 resets = <&cru SRST_MMC0>; 255 reset-names = "reset"; 256 status = "disabled"; 257 }; 258 259 sdio0: dwmmc@ff0d0000 { 260 compatible = "rockchip,rk3288-dw-mshc"; 261 max-frequency = <150000000>; 262 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 263 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 264 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 265 fifo-depth = <0x100>; 266 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 267 reg = <0x0 0xff0d0000 0x0 0x4000>; 268 resets = <&cru SRST_SDIO0>; 269 reset-names = "reset"; 270 status = "disabled"; 271 }; 272 273 sdio1: dwmmc@ff0e0000 { 274 compatible = "rockchip,rk3288-dw-mshc"; 275 max-frequency = <150000000>; 276 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, 277 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; 278 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 279 fifo-depth = <0x100>; 280 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 281 reg = <0x0 0xff0e0000 0x0 0x4000>; 282 resets = <&cru SRST_SDIO1>; 283 reset-names = "reset"; 284 status = "disabled"; 285 }; 286 287 emmc: dwmmc@ff0f0000 { 288 compatible = "rockchip,rk3288-dw-mshc"; 289 max-frequency = <150000000>; 290 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 291 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 292 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 293 fifo-depth = <0x100>; 294 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 295 reg = <0x0 0xff0f0000 0x0 0x4000>; 296 resets = <&cru SRST_EMMC>; 297 reset-names = "reset"; 298 status = "disabled"; 299 }; 300 301 saradc: saradc@ff100000 { 302 compatible = "rockchip,saradc"; 303 reg = <0x0 0xff100000 0x0 0x100>; 304 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 305 #io-channel-cells = <1>; 306 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 307 clock-names = "saradc", "apb_pclk"; 308 resets = <&cru SRST_SARADC>; 309 reset-names = "saradc-apb"; 310 status = "disabled"; 311 }; 312 313 spi0: spi@ff110000 { 314 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 315 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 316 clock-names = "spiclk", "apb_pclk"; 317 dmas = <&dmac_peri 11>, <&dmac_peri 12>; 318 dma-names = "tx", "rx"; 319 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 322 reg = <0x0 0xff110000 0x0 0x1000>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 status = "disabled"; 326 }; 327 328 spi1: spi@ff120000 { 329 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 330 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 331 clock-names = "spiclk", "apb_pclk"; 332 dmas = <&dmac_peri 13>, <&dmac_peri 14>; 333 dma-names = "tx", "rx"; 334 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 335 pinctrl-names = "default"; 336 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 337 reg = <0x0 0xff120000 0x0 0x1000>; 338 #address-cells = <1>; 339 #size-cells = <0>; 340 status = "disabled"; 341 }; 342 343 spi2: spi@ff130000 { 344 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 345 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 346 clock-names = "spiclk", "apb_pclk"; 347 dmas = <&dmac_peri 15>, <&dmac_peri 16>; 348 dma-names = "tx", "rx"; 349 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 352 reg = <0x0 0xff130000 0x0 0x1000>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 status = "disabled"; 356 }; 357 358 i2c1: i2c@ff140000 { 359 compatible = "rockchip,rk3288-i2c"; 360 reg = <0x0 0xff140000 0x0 0x1000>; 361 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 clock-names = "i2c"; 365 clocks = <&cru PCLK_I2C1>; 366 pinctrl-names = "default"; 367 pinctrl-0 = <&i2c1_xfer>; 368 status = "disabled"; 369 }; 370 371 i2c3: i2c@ff150000 { 372 compatible = "rockchip,rk3288-i2c"; 373 reg = <0x0 0xff150000 0x0 0x1000>; 374 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 clock-names = "i2c"; 378 clocks = <&cru PCLK_I2C3>; 379 pinctrl-names = "default"; 380 pinctrl-0 = <&i2c3_xfer>; 381 status = "disabled"; 382 }; 383 384 i2c4: i2c@ff160000 { 385 compatible = "rockchip,rk3288-i2c"; 386 reg = <0x0 0xff160000 0x0 0x1000>; 387 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 clock-names = "i2c"; 391 clocks = <&cru PCLK_I2C4>; 392 pinctrl-names = "default"; 393 pinctrl-0 = <&i2c4_xfer>; 394 status = "disabled"; 395 }; 396 397 i2c5: i2c@ff170000 { 398 compatible = "rockchip,rk3288-i2c"; 399 reg = <0x0 0xff170000 0x0 0x1000>; 400 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 clock-names = "i2c"; 404 clocks = <&cru PCLK_I2C5>; 405 pinctrl-names = "default"; 406 pinctrl-0 = <&i2c5_xfer>; 407 status = "disabled"; 408 }; 409 410 uart0: serial@ff180000 { 411 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 412 reg = <0x0 0xff180000 0x0 0x100>; 413 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 414 reg-shift = <2>; 415 reg-io-width = <4>; 416 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 417 clock-names = "baudclk", "apb_pclk"; 418 pinctrl-names = "default"; 419 pinctrl-0 = <&uart0_xfer>; 420 status = "disabled"; 421 }; 422 423 uart1: serial@ff190000 { 424 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 425 reg = <0x0 0xff190000 0x0 0x100>; 426 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 427 reg-shift = <2>; 428 reg-io-width = <4>; 429 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 430 clock-names = "baudclk", "apb_pclk"; 431 pinctrl-names = "default"; 432 pinctrl-0 = <&uart1_xfer>; 433 status = "disabled"; 434 }; 435 436 uart2: serial@ff690000 { 437 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 438 reg = <0x0 0xff690000 0x0 0x100>; 439 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 440 reg-shift = <2>; 441 reg-io-width = <4>; 442 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 443 clock-names = "baudclk", "apb_pclk"; 444 pinctrl-names = "default"; 445 pinctrl-0 = <&uart2_xfer>; 446 status = "disabled"; 447 }; 448 449 uart3: serial@ff1b0000 { 450 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 451 reg = <0x0 0xff1b0000 0x0 0x100>; 452 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 453 reg-shift = <2>; 454 reg-io-width = <4>; 455 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 456 clock-names = "baudclk", "apb_pclk"; 457 pinctrl-names = "default"; 458 pinctrl-0 = <&uart3_xfer>; 459 status = "disabled"; 460 }; 461 462 uart4: serial@ff1c0000 { 463 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 464 reg = <0x0 0xff1c0000 0x0 0x100>; 465 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 466 reg-shift = <2>; 467 reg-io-width = <4>; 468 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 469 clock-names = "baudclk", "apb_pclk"; 470 pinctrl-names = "default"; 471 pinctrl-0 = <&uart4_xfer>; 472 status = "disabled"; 473 }; 474 475 thermal-zones { 476 reserve_thermal: reserve_thermal { 477 polling-delay-passive = <1000>; /* milliseconds */ 478 polling-delay = <5000>; /* milliseconds */ 479 480 thermal-sensors = <&tsadc 0>; 481 }; 482 483 cpu_thermal: cpu_thermal { 484 polling-delay-passive = <100>; /* milliseconds */ 485 polling-delay = <5000>; /* milliseconds */ 486 487 thermal-sensors = <&tsadc 1>; 488 489 trips { 490 cpu_alert0: cpu_alert0 { 491 temperature = <70000>; /* millicelsius */ 492 hysteresis = <2000>; /* millicelsius */ 493 type = "passive"; 494 }; 495 cpu_alert1: cpu_alert1 { 496 temperature = <75000>; /* millicelsius */ 497 hysteresis = <2000>; /* millicelsius */ 498 type = "passive"; 499 }; 500 cpu_crit: cpu_crit { 501 temperature = <90000>; /* millicelsius */ 502 hysteresis = <2000>; /* millicelsius */ 503 type = "critical"; 504 }; 505 }; 506 507 cooling-maps { 508 map0 { 509 trip = <&cpu_alert0>; 510 cooling-device = 511 <&cpu0 THERMAL_NO_LIMIT 6>; 512 }; 513 map1 { 514 trip = <&cpu_alert1>; 515 cooling-device = 516 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 517 }; 518 }; 519 }; 520 521 gpu_thermal: gpu_thermal { 522 polling-delay-passive = <100>; /* milliseconds */ 523 polling-delay = <5000>; /* milliseconds */ 524 525 thermal-sensors = <&tsadc 2>; 526 527 trips { 528 gpu_alert0: gpu_alert0 { 529 temperature = <70000>; /* millicelsius */ 530 hysteresis = <2000>; /* millicelsius */ 531 type = "passive"; 532 }; 533 gpu_crit: gpu_crit { 534 temperature = <90000>; /* millicelsius */ 535 hysteresis = <2000>; /* millicelsius */ 536 type = "critical"; 537 }; 538 }; 539 540 cooling-maps { 541 map0 { 542 trip = <&gpu_alert0>; 543 cooling-device = 544 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 545 }; 546 }; 547 }; 548 }; 549 550 tsadc: tsadc@ff280000 { 551 compatible = "rockchip,rk3288-tsadc"; 552 reg = <0x0 0xff280000 0x0 0x100>; 553 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 555 clock-names = "tsadc", "apb_pclk"; 556 resets = <&cru SRST_TSADC>; 557 reset-names = "tsadc-apb"; 558 pinctrl-names = "init", "default", "sleep"; 559 pinctrl-0 = <&otp_gpio>; 560 pinctrl-1 = <&otp_out>; 561 pinctrl-2 = <&otp_gpio>; 562 #thermal-sensor-cells = <1>; 563 rockchip,hw-tshut-temp = <95000>; 564 status = "disabled"; 565 }; 566 567 gmac: ethernet@ff290000 { 568 compatible = "rockchip,rk3288-gmac"; 569 reg = <0x0 0xff290000 0x0 0x10000>; 570 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 572 interrupt-names = "macirq", "eth_wake_irq"; 573 rockchip,grf = <&grf>; 574 clocks = <&cru SCLK_MAC>, 575 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 576 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 577 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 578 clock-names = "stmmaceth", 579 "mac_clk_rx", "mac_clk_tx", 580 "clk_mac_ref", "clk_mac_refout", 581 "aclk_mac", "pclk_mac"; 582 resets = <&cru SRST_MAC>; 583 reset-names = "stmmaceth"; 584 status = "disabled"; 585 }; 586 587 usb_host0_ehci: usb@ff500000 { 588 compatible = "generic-ehci"; 589 reg = <0x0 0xff500000 0x0 0x100>; 590 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&cru HCLK_USBHOST0>; 592 clock-names = "usbhost"; 593 phys = <&usbphy1>; 594 phy-names = "usb"; 595 status = "disabled"; 596 }; 597 598 /* NOTE: ohci@ff520000 doesn't actually work on hardware */ 599 600 usb_host1: usb@ff540000 { 601 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 602 "snps,dwc2"; 603 reg = <0x0 0xff540000 0x0 0x40000>; 604 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&cru HCLK_USBHOST1>; 606 clock-names = "otg"; 607 dr_mode = "host"; 608 phys = <&usbphy2>; 609 phy-names = "usb2-phy"; 610 status = "disabled"; 611 }; 612 613 usb_otg: usb@ff580000 { 614 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 615 "snps,dwc2"; 616 reg = <0x0 0xff580000 0x0 0x40000>; 617 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&cru HCLK_OTG0>; 619 clock-names = "otg"; 620 dr_mode = "otg"; 621 g-np-tx-fifo-size = <16>; 622 g-rx-fifo-size = <275>; 623 g-tx-fifo-size = <256 128 128 64 64 32>; 624 phys = <&usbphy0>; 625 phy-names = "usb2-phy"; 626 status = "disabled"; 627 }; 628 629 usb_hsic: usb@ff5c0000 { 630 compatible = "generic-ehci"; 631 reg = <0x0 0xff5c0000 0x0 0x100>; 632 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&cru HCLK_HSIC>; 634 clock-names = "usbhost"; 635 status = "disabled"; 636 }; 637 638 i2c0: i2c@ff650000 { 639 compatible = "rockchip,rk3288-i2c"; 640 reg = <0x0 0xff650000 0x0 0x1000>; 641 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 clock-names = "i2c"; 645 clocks = <&cru PCLK_I2C0>; 646 pinctrl-names = "default"; 647 pinctrl-0 = <&i2c0_xfer>; 648 status = "disabled"; 649 }; 650 651 i2c2: i2c@ff660000 { 652 compatible = "rockchip,rk3288-i2c"; 653 reg = <0x0 0xff660000 0x0 0x1000>; 654 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 655 #address-cells = <1>; 656 #size-cells = <0>; 657 clock-names = "i2c"; 658 clocks = <&cru PCLK_I2C2>; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&i2c2_xfer>; 661 status = "disabled"; 662 }; 663 664 pwm0: pwm@ff680000 { 665 compatible = "rockchip,rk3288-pwm"; 666 reg = <0x0 0xff680000 0x0 0x10>; 667 #pwm-cells = <3>; 668 pinctrl-names = "default"; 669 pinctrl-0 = <&pwm0_pin>; 670 clocks = <&cru PCLK_PWM>; 671 clock-names = "pwm"; 672 status = "disabled"; 673 }; 674 675 pwm1: pwm@ff680010 { 676 compatible = "rockchip,rk3288-pwm"; 677 reg = <0x0 0xff680010 0x0 0x10>; 678 #pwm-cells = <3>; 679 pinctrl-names = "default"; 680 pinctrl-0 = <&pwm1_pin>; 681 clocks = <&cru PCLK_PWM>; 682 clock-names = "pwm"; 683 status = "disabled"; 684 }; 685 686 pwm2: pwm@ff680020 { 687 compatible = "rockchip,rk3288-pwm"; 688 reg = <0x0 0xff680020 0x0 0x10>; 689 #pwm-cells = <3>; 690 pinctrl-names = "default"; 691 pinctrl-0 = <&pwm2_pin>; 692 clocks = <&cru PCLK_PWM>; 693 clock-names = "pwm"; 694 status = "disabled"; 695 }; 696 697 pwm3: pwm@ff680030 { 698 compatible = "rockchip,rk3288-pwm"; 699 reg = <0x0 0xff680030 0x0 0x10>; 700 #pwm-cells = <2>; 701 pinctrl-names = "default"; 702 pinctrl-0 = <&pwm3_pin>; 703 clocks = <&cru PCLK_PWM>; 704 clock-names = "pwm"; 705 status = "disabled"; 706 }; 707 708 bus_intmem@ff700000 { 709 compatible = "mmio-sram"; 710 reg = <0x0 0xff700000 0x0 0x18000>; 711 #address-cells = <1>; 712 #size-cells = <1>; 713 ranges = <0 0x0 0xff700000 0x18000>; 714 smp-sram@0 { 715 compatible = "rockchip,rk3066-smp-sram"; 716 reg = <0x00 0x10>; 717 }; 718 }; 719 720 sram@ff720000 { 721 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 722 reg = <0x0 0xff720000 0x0 0x1000>; 723 }; 724 725 pmu: power-management@ff730000 { 726 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; 727 reg = <0x0 0xff730000 0x0 0x100>; 728 729 power: power-controller { 730 compatible = "rockchip,rk3288-power-controller"; 731 #power-domain-cells = <1>; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 735 assigned-clocks = <&cru SCLK_EDP_24M>; 736 assigned-clock-parents = <&xin24m>; 737 738 /* 739 * Note: Although SCLK_* are the working clocks 740 * of device without including on the NOC, needed for 741 * synchronous reset. 742 * 743 * The clocks on the which NOC: 744 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. 745 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. 746 * ACLK_RGA is on ACLK_RGA_NIU. 747 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. 748 * 749 * Which clock are device clocks: 750 * clocks devices 751 * *_IEP IEP:Image Enhancement Processor 752 * *_ISP ISP:Image Signal Processing 753 * *_VIP VIP:Video Input Processor 754 * *_VOP* VOP:Visual Output Processor 755 * *_RGA RGA 756 * *_EDP* EDP 757 * *_LVDS_* LVDS 758 * *_HDMI HDMI 759 * *_MIPI_* MIPI 760 */ 761 pd_vio@RK3288_PD_VIO { 762 reg = <RK3288_PD_VIO>; 763 clocks = <&cru ACLK_IEP>, 764 <&cru ACLK_ISP>, 765 <&cru ACLK_RGA>, 766 <&cru ACLK_VIP>, 767 <&cru ACLK_VOP0>, 768 <&cru ACLK_VOP1>, 769 <&cru DCLK_VOP0>, 770 <&cru DCLK_VOP1>, 771 <&cru HCLK_IEP>, 772 <&cru HCLK_ISP>, 773 <&cru HCLK_RGA>, 774 <&cru HCLK_VIP>, 775 <&cru HCLK_VOP0>, 776 <&cru HCLK_VOP1>, 777 <&cru PCLK_EDP_CTRL>, 778 <&cru PCLK_HDMI_CTRL>, 779 <&cru PCLK_LVDS_PHY>, 780 <&cru PCLK_MIPI_CSI>, 781 <&cru PCLK_MIPI_DSI0>, 782 <&cru PCLK_MIPI_DSI1>, 783 <&cru SCLK_EDP_24M>, 784 <&cru SCLK_EDP>, 785 <&cru SCLK_ISP_JPE>, 786 <&cru SCLK_ISP>, 787 <&cru SCLK_RGA>; 788 pm_qos = <&qos_vio0_iep>, 789 <&qos_vio1_vop>, 790 <&qos_vio1_isp_w0>, 791 <&qos_vio1_isp_w1>, 792 <&qos_vio0_vop>, 793 <&qos_vio0_vip>, 794 <&qos_vio2_rga_r>, 795 <&qos_vio2_rga_w>, 796 <&qos_vio1_isp_r>; 797 }; 798 799 /* 800 * Note: The following 3 are HEVC(H.265) clocks, 801 * and on the ACLK_HEVC_NIU (NOC). 802 */ 803 pd_hevc@RK3288_PD_HEVC { 804 reg = <RK3288_PD_HEVC>; 805 clocks = <&cru ACLK_HEVC>, 806 <&cru SCLK_HEVC_CABAC>, 807 <&cru SCLK_HEVC_CORE>; 808 pm_qos = <&qos_hevc_r>, 809 <&qos_hevc_w>; 810 }; 811 812 /* 813 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC 814 * (video endecoder & decoder) clocks that on the 815 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). 816 */ 817 pd_video@RK3288_PD_VIDEO { 818 reg = <RK3288_PD_VIDEO>; 819 clocks = <&cru ACLK_VCODEC>, 820 <&cru HCLK_VCODEC>; 821 pm_qos = <&qos_video>; 822 }; 823 824 /* 825 * Note: ACLK_GPU is the GPU clock, 826 * and on the ACLK_GPU_NIU (NOC). 827 */ 828 pd_gpu@RK3288_PD_GPU { 829 reg = <RK3288_PD_GPU>; 830 clocks = <&cru ACLK_GPU>; 831 pm_qos = <&qos_gpu_r>, 832 <&qos_gpu_w>; 833 }; 834 }; 835 836 reboot-mode { 837 compatible = "syscon-reboot-mode"; 838 offset = <0x94>; 839 mode-normal = <BOOT_NORMAL>; 840 mode-recovery = <BOOT_RECOVERY>; 841 mode-bootloader = <BOOT_FASTBOOT>; 842 mode-loader = <BOOT_BL_DOWNLOAD>; 843 }; 844 }; 845 846 sgrf: syscon@ff740000 { 847 compatible = "rockchip,rk3288-sgrf", "syscon"; 848 reg = <0x0 0xff740000 0x0 0x1000>; 849 }; 850 851 cru: clock-controller@ff760000 { 852 compatible = "rockchip,rk3288-cru"; 853 reg = <0x0 0xff760000 0x0 0x1000>; 854 rockchip,grf = <&grf>; 855 #clock-cells = <1>; 856 #reset-cells = <1>; 857 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, 858 <&cru PLL_NPLL>, <&cru ACLK_CPU>, 859 <&cru HCLK_CPU>, <&cru PCLK_CPU>, 860 <&cru ACLK_PERI>, <&cru HCLK_PERI>, 861 <&cru PCLK_PERI>; 862 assigned-clock-rates = <594000000>, <400000000>, 863 <500000000>, <300000000>, 864 <150000000>, <75000000>, 865 <300000000>, <150000000>, 866 <75000000>; 867 }; 868 869 grf: syscon@ff770000 { 870 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; 871 reg = <0x0 0xff770000 0x0 0x1000>; 872 873 edp_phy: edp-phy { 874 compatible = "rockchip,rk3288-dp-phy"; 875 clocks = <&cru SCLK_EDP_24M>; 876 clock-names = "24m"; 877 #phy-cells = <0>; 878 status = "disabled"; 879 }; 880 881 io_domains: io-domains { 882 compatible = "rockchip,rk3288-io-voltage-domain"; 883 status = "disabled"; 884 }; 885 886 usbphy: usbphy { 887 compatible = "rockchip,rk3288-usb-phy"; 888 #address-cells = <1>; 889 #size-cells = <0>; 890 status = "disabled"; 891 892 usbphy0: usb-phy@320 { 893 #phy-cells = <0>; 894 reg = <0x320>; 895 clocks = <&cru SCLK_OTGPHY0>; 896 clock-names = "phyclk"; 897 #clock-cells = <0>; 898 }; 899 900 usbphy1: usb-phy@334 { 901 #phy-cells = <0>; 902 reg = <0x334>; 903 clocks = <&cru SCLK_OTGPHY1>; 904 clock-names = "phyclk"; 905 #clock-cells = <0>; 906 }; 907 908 usbphy2: usb-phy@348 { 909 #phy-cells = <0>; 910 reg = <0x348>; 911 clocks = <&cru SCLK_OTGPHY2>; 912 clock-names = "phyclk"; 913 #clock-cells = <0>; 914 }; 915 }; 916 }; 917 918 wdt: watchdog@ff800000 { 919 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; 920 reg = <0x0 0xff800000 0x0 0x100>; 921 clocks = <&cru PCLK_WDT>; 922 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 923 status = "disabled"; 924 }; 925 926 spdif: sound@ff88b0000 { 927 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; 928 reg = <0x0 0xff8b0000 0x0 0x10000>; 929 #sound-dai-cells = <0>; 930 clock-names = "hclk", "mclk"; 931 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; 932 dmas = <&dmac_bus_s 3>; 933 dma-names = "tx"; 934 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 935 pinctrl-names = "default"; 936 pinctrl-0 = <&spdif_tx>; 937 rockchip,grf = <&grf>; 938 status = "disabled"; 939 }; 940 941 i2s: i2s@ff890000 { 942 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; 943 reg = <0x0 0xff890000 0x0 0x10000>; 944 #sound-dai-cells = <0>; 945 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; 949 dma-names = "tx", "rx"; 950 clock-names = "i2s_hclk", "i2s_clk"; 951 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; 952 pinctrl-names = "default"; 953 pinctrl-0 = <&i2s0_bus>; 954 rockchip,playback-channels = <8>; 955 rockchip,capture-channels = <2>; 956 status = "disabled"; 957 }; 958 959 crypto: cypto-controller@ff8a0000 { 960 compatible = "rockchip,rk3288-crypto"; 961 reg = <0x0 0xff8a0000 0x0 0x4000>; 962 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 963 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, 964 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; 965 clock-names = "aclk", "hclk", "sclk", "apb_pclk"; 966 resets = <&cru SRST_CRYPTO>; 967 reset-names = "crypto-rst"; 968 status = "okay"; 969 }; 970 971 iep_mmu: iommu@ff900800 { 972 compatible = "rockchip,iommu"; 973 reg = <0x0 0xff900800 0x0 0x40>; 974 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 975 interrupt-names = "iep_mmu"; 976 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 977 clock-names = "aclk", "iface"; 978 #iommu-cells = <0>; 979 status = "disabled"; 980 }; 981 982 isp_mmu: iommu@ff914000 { 983 compatible = "rockchip,iommu"; 984 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 985 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 986 interrupt-names = "isp_mmu"; 987 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 988 clock-names = "aclk", "iface"; 989 #iommu-cells = <0>; 990 rockchip,disable-mmu-reset; 991 status = "disabled"; 992 }; 993 994 rga: rga@ff920000 { 995 compatible = "rockchip,rk3288-rga"; 996 reg = <0x0 0xff920000 0x0 0x180>; 997 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; 999 clock-names = "aclk", "hclk", "sclk"; 1000 power-domains = <&power RK3288_PD_VIO>; 1001 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; 1002 reset-names = "core", "axi", "ahb"; 1003 }; 1004 1005 vopb: vop@ff930000 { 1006 compatible = "rockchip,rk3288-vop"; 1007 reg = <0x0 0xff930000 0x0 0x19c>; 1008 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1010 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1011 power-domains = <&power RK3288_PD_VIO>; 1012 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 1013 reset-names = "axi", "ahb", "dclk"; 1014 iommus = <&vopb_mmu>; 1015 status = "disabled"; 1016 1017 vopb_out: port { 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 1021 vopb_out_hdmi: endpoint@0 { 1022 reg = <0>; 1023 remote-endpoint = <&hdmi_in_vopb>; 1024 }; 1025 1026 vopb_out_edp: endpoint@1 { 1027 reg = <1>; 1028 remote-endpoint = <&edp_in_vopb>; 1029 }; 1030 1031 vopb_out_mipi: endpoint@2 { 1032 reg = <2>; 1033 remote-endpoint = <&mipi_in_vopb>; 1034 }; 1035 1036 vopb_out_lvds: endpoint@3 { 1037 reg = <3>; 1038 remote-endpoint = <&lvds_in_vopb>; 1039 }; 1040 }; 1041 }; 1042 1043 vopb_mmu: iommu@ff930300 { 1044 compatible = "rockchip,iommu"; 1045 reg = <0x0 0xff930300 0x0 0x100>; 1046 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1047 interrupt-names = "vopb_mmu"; 1048 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1049 clock-names = "aclk", "iface"; 1050 power-domains = <&power RK3288_PD_VIO>; 1051 #iommu-cells = <0>; 1052 status = "disabled"; 1053 }; 1054 1055 vopl: vop@ff940000 { 1056 compatible = "rockchip,rk3288-vop"; 1057 reg = <0x0 0xff940000 0x0 0x19c>; 1058 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1059 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1060 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1061 power-domains = <&power RK3288_PD_VIO>; 1062 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 1063 reset-names = "axi", "ahb", "dclk"; 1064 iommus = <&vopl_mmu>; 1065 status = "disabled"; 1066 1067 vopl_out: port { 1068 #address-cells = <1>; 1069 #size-cells = <0>; 1070 1071 vopl_out_hdmi: endpoint@0 { 1072 reg = <0>; 1073 remote-endpoint = <&hdmi_in_vopl>; 1074 }; 1075 1076 vopl_out_edp: endpoint@1 { 1077 reg = <1>; 1078 remote-endpoint = <&edp_in_vopl>; 1079 }; 1080 1081 vopl_out_mipi: endpoint@2 { 1082 reg = <2>; 1083 remote-endpoint = <&mipi_in_vopl>; 1084 }; 1085 1086 vopl_out_lvds: endpoint@3 { 1087 reg = <3>; 1088 remote-endpoint = <&lvds_in_vopl>; 1089 }; 1090 }; 1091 }; 1092 1093 vopl_mmu: iommu@ff940300 { 1094 compatible = "rockchip,iommu"; 1095 reg = <0x0 0xff940300 0x0 0x100>; 1096 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1097 interrupt-names = "vopl_mmu"; 1098 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1099 clock-names = "aclk", "iface"; 1100 power-domains = <&power RK3288_PD_VIO>; 1101 #iommu-cells = <0>; 1102 status = "disabled"; 1103 }; 1104 1105 mipi_dsi: mipi@ff960000 { 1106 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; 1107 reg = <0x0 0xff960000 0x0 0x4000>; 1108 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1109 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; 1110 clock-names = "ref", "pclk"; 1111 power-domains = <&power RK3288_PD_VIO>; 1112 rockchip,grf = <&grf>; 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 status = "disabled"; 1116 1117 ports { 1118 mipi_in: port { 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 mipi_in_vopb: endpoint@0 { 1122 reg = <0>; 1123 remote-endpoint = <&vopb_out_mipi>; 1124 }; 1125 mipi_in_vopl: endpoint@1 { 1126 reg = <1>; 1127 remote-endpoint = <&vopl_out_mipi>; 1128 }; 1129 }; 1130 }; 1131 }; 1132 1133 lvds: lvds@ff96c000 { 1134 compatible = "rockchip,rk3288-lvds"; 1135 reg = <0x0 0xff96c000 0x0 0x4000>; 1136 clocks = <&cru PCLK_LVDS_PHY>; 1137 clock-names = "pclk_lvds"; 1138 pinctrl-names = "lcdc"; 1139 pinctrl-0 = <&lcdc_ctl>; 1140 power-domains = <&power RK3288_PD_VIO>; 1141 rockchip,grf = <&grf>; 1142 status = "disabled"; 1143 1144 ports { 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 1148 lvds_in: port@0 { 1149 reg = <0>; 1150 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 1154 lvds_in_vopb: endpoint@0 { 1155 reg = <0>; 1156 remote-endpoint = <&vopb_out_lvds>; 1157 }; 1158 lvds_in_vopl: endpoint@1 { 1159 reg = <1>; 1160 remote-endpoint = <&vopl_out_lvds>; 1161 }; 1162 }; 1163 }; 1164 }; 1165 1166 edp: dp@ff970000 { 1167 compatible = "rockchip,rk3288-dp"; 1168 reg = <0x0 0xff970000 0x0 0x4000>; 1169 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1170 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; 1171 clock-names = "dp", "pclk"; 1172 phys = <&edp_phy>; 1173 phy-names = "dp"; 1174 resets = <&cru SRST_EDP>; 1175 reset-names = "dp"; 1176 rockchip,grf = <&grf>; 1177 status = "disabled"; 1178 1179 ports { 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 edp_in: port@0 { 1183 reg = <0>; 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 edp_in_vopb: endpoint@0 { 1187 reg = <0>; 1188 remote-endpoint = <&vopb_out_edp>; 1189 }; 1190 edp_in_vopl: endpoint@1 { 1191 reg = <1>; 1192 remote-endpoint = <&vopl_out_edp>; 1193 }; 1194 }; 1195 }; 1196 }; 1197 1198 hdmi: hdmi@ff980000 { 1199 compatible = "rockchip,rk3288-dw-hdmi"; 1200 reg = <0x0 0xff980000 0x0 0x20000>; 1201 reg-io-width = <4>; 1202 #sound-dai-cells = <0>; 1203 rockchip,grf = <&grf>; 1204 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1205 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; 1206 clock-names = "iahb", "isfr", "cec"; 1207 power-domains = <&power RK3288_PD_VIO>; 1208 status = "disabled"; 1209 1210 ports { 1211 hdmi_in: port { 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 hdmi_in_vopb: endpoint@0 { 1215 reg = <0>; 1216 remote-endpoint = <&vopb_out_hdmi>; 1217 }; 1218 hdmi_in_vopl: endpoint@1 { 1219 reg = <1>; 1220 remote-endpoint = <&vopl_out_hdmi>; 1221 }; 1222 }; 1223 }; 1224 }; 1225 1226 vpu_mmu: iommu@ff9a0800 { 1227 compatible = "rockchip,iommu"; 1228 reg = <0x0 0xff9a0800 0x0 0x100>; 1229 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1230 interrupt-names = "vpu_mmu"; 1231 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1232 clock-names = "aclk", "iface"; 1233 #iommu-cells = <0>; 1234 status = "disabled"; 1235 }; 1236 1237 hevc_mmu: iommu@ff9c0440 { 1238 compatible = "rockchip,iommu"; 1239 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; 1240 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1241 interrupt-names = "hevc_mmu"; 1242 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; 1243 clock-names = "aclk", "iface"; 1244 #iommu-cells = <0>; 1245 status = "disabled"; 1246 }; 1247 1248 gpu: gpu@ffa30000 { 1249 compatible = "rockchip,rk3288-mali", "arm,mali-t760"; 1250 reg = <0x0 0xffa30000 0x0 0x10000>; 1251 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1254 interrupt-names = "job", "mmu", "gpu"; 1255 clocks = <&cru ACLK_GPU>; 1256 operating-points-v2 = <&gpu_opp_table>; 1257 power-domains = <&power RK3288_PD_GPU>; 1258 status = "disabled"; 1259 }; 1260 1261 gpu_opp_table: gpu-opp-table { 1262 compatible = "operating-points-v2"; 1263 1264 opp@100000000 { 1265 opp-hz = /bits/ 64 <100000000>; 1266 opp-microvolt = <950000>; 1267 }; 1268 opp@200000000 { 1269 opp-hz = /bits/ 64 <200000000>; 1270 opp-microvolt = <950000>; 1271 }; 1272 opp@300000000 { 1273 opp-hz = /bits/ 64 <300000000>; 1274 opp-microvolt = <1000000>; 1275 }; 1276 opp@400000000 { 1277 opp-hz = /bits/ 64 <400000000>; 1278 opp-microvolt = <1100000>; 1279 }; 1280 opp@500000000 { 1281 opp-hz = /bits/ 64 <500000000>; 1282 opp-microvolt = <1200000>; 1283 }; 1284 opp@600000000 { 1285 opp-hz = /bits/ 64 <600000000>; 1286 opp-microvolt = <1250000>; 1287 }; 1288 }; 1289 1290 qos_gpu_r: qos@ffaa0000 { 1291 compatible = "syscon"; 1292 reg = <0x0 0xffaa0000 0x0 0x20>; 1293 }; 1294 1295 qos_gpu_w: qos@ffaa0080 { 1296 compatible = "syscon"; 1297 reg = <0x0 0xffaa0080 0x0 0x20>; 1298 }; 1299 1300 qos_vio1_vop: qos@ffad0000 { 1301 compatible = "syscon"; 1302 reg = <0x0 0xffad0000 0x0 0x20>; 1303 }; 1304 1305 qos_vio1_isp_w0: qos@ffad0100 { 1306 compatible = "syscon"; 1307 reg = <0x0 0xffad0100 0x0 0x20>; 1308 }; 1309 1310 qos_vio1_isp_w1: qos@ffad0180 { 1311 compatible = "syscon"; 1312 reg = <0x0 0xffad0180 0x0 0x20>; 1313 }; 1314 1315 qos_vio0_vop: qos@ffad0400 { 1316 compatible = "syscon"; 1317 reg = <0x0 0xffad0400 0x0 0x20>; 1318 }; 1319 1320 qos_vio0_vip: qos@ffad0480 { 1321 compatible = "syscon"; 1322 reg = <0x0 0xffad0480 0x0 0x20>; 1323 }; 1324 1325 qos_vio0_iep: qos@ffad0500 { 1326 compatible = "syscon"; 1327 reg = <0x0 0xffad0500 0x0 0x20>; 1328 }; 1329 1330 qos_vio2_rga_r: qos@ffad0800 { 1331 compatible = "syscon"; 1332 reg = <0x0 0xffad0800 0x0 0x20>; 1333 }; 1334 1335 qos_vio2_rga_w: qos@ffad0880 { 1336 compatible = "syscon"; 1337 reg = <0x0 0xffad0880 0x0 0x20>; 1338 }; 1339 1340 qos_vio1_isp_r: qos@ffad0900 { 1341 compatible = "syscon"; 1342 reg = <0x0 0xffad0900 0x0 0x20>; 1343 }; 1344 1345 qos_video: qos@ffae0000 { 1346 compatible = "syscon"; 1347 reg = <0x0 0xffae0000 0x0 0x20>; 1348 }; 1349 1350 qos_hevc_r: qos@ffaf0000 { 1351 compatible = "syscon"; 1352 reg = <0x0 0xffaf0000 0x0 0x20>; 1353 }; 1354 1355 qos_hevc_w: qos@ffaf0080 { 1356 compatible = "syscon"; 1357 reg = <0x0 0xffaf0080 0x0 0x20>; 1358 }; 1359 1360 gic: interrupt-controller@ffc01000 { 1361 compatible = "arm,gic-400"; 1362 interrupt-controller; 1363 #interrupt-cells = <3>; 1364 #address-cells = <0>; 1365 1366 reg = <0x0 0xffc01000 0x0 0x1000>, 1367 <0x0 0xffc02000 0x0 0x2000>, 1368 <0x0 0xffc04000 0x0 0x2000>, 1369 <0x0 0xffc06000 0x0 0x2000>; 1370 interrupts = <GIC_PPI 9 0xf04>; 1371 }; 1372 1373 efuse: efuse@ffb40000 { 1374 compatible = "rockchip,rk3288-efuse"; 1375 reg = <0x0 0xffb40000 0x0 0x20>; 1376 #address-cells = <1>; 1377 #size-cells = <1>; 1378 clocks = <&cru PCLK_EFUSE256>; 1379 clock-names = "pclk_efuse"; 1380 1381 cpu_leakage: cpu_leakage@17 { 1382 reg = <0x17 0x1>; 1383 }; 1384 }; 1385 1386 pinctrl: pinctrl { 1387 compatible = "rockchip,rk3288-pinctrl"; 1388 rockchip,grf = <&grf>; 1389 rockchip,pmu = <&pmu>; 1390 #address-cells = <2>; 1391 #size-cells = <2>; 1392 ranges; 1393 1394 gpio0: gpio0@ff750000 { 1395 compatible = "rockchip,gpio-bank"; 1396 reg = <0x0 0xff750000 0x0 0x100>; 1397 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1398 clocks = <&cru PCLK_GPIO0>; 1399 1400 gpio-controller; 1401 #gpio-cells = <2>; 1402 1403 interrupt-controller; 1404 #interrupt-cells = <2>; 1405 }; 1406 1407 gpio1: gpio1@ff780000 { 1408 compatible = "rockchip,gpio-bank"; 1409 reg = <0x0 0xff780000 0x0 0x100>; 1410 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1411 clocks = <&cru PCLK_GPIO1>; 1412 1413 gpio-controller; 1414 #gpio-cells = <2>; 1415 1416 interrupt-controller; 1417 #interrupt-cells = <2>; 1418 }; 1419 1420 gpio2: gpio2@ff790000 { 1421 compatible = "rockchip,gpio-bank"; 1422 reg = <0x0 0xff790000 0x0 0x100>; 1423 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1424 clocks = <&cru PCLK_GPIO2>; 1425 1426 gpio-controller; 1427 #gpio-cells = <2>; 1428 1429 interrupt-controller; 1430 #interrupt-cells = <2>; 1431 }; 1432 1433 gpio3: gpio3@ff7a0000 { 1434 compatible = "rockchip,gpio-bank"; 1435 reg = <0x0 0xff7a0000 0x0 0x100>; 1436 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1437 clocks = <&cru PCLK_GPIO3>; 1438 1439 gpio-controller; 1440 #gpio-cells = <2>; 1441 1442 interrupt-controller; 1443 #interrupt-cells = <2>; 1444 }; 1445 1446 gpio4: gpio4@ff7b0000 { 1447 compatible = "rockchip,gpio-bank"; 1448 reg = <0x0 0xff7b0000 0x0 0x100>; 1449 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1450 clocks = <&cru PCLK_GPIO4>; 1451 1452 gpio-controller; 1453 #gpio-cells = <2>; 1454 1455 interrupt-controller; 1456 #interrupt-cells = <2>; 1457 }; 1458 1459 gpio5: gpio5@ff7c0000 { 1460 compatible = "rockchip,gpio-bank"; 1461 reg = <0x0 0xff7c0000 0x0 0x100>; 1462 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1463 clocks = <&cru PCLK_GPIO5>; 1464 1465 gpio-controller; 1466 #gpio-cells = <2>; 1467 1468 interrupt-controller; 1469 #interrupt-cells = <2>; 1470 }; 1471 1472 gpio6: gpio6@ff7d0000 { 1473 compatible = "rockchip,gpio-bank"; 1474 reg = <0x0 0xff7d0000 0x0 0x100>; 1475 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1476 clocks = <&cru PCLK_GPIO6>; 1477 1478 gpio-controller; 1479 #gpio-cells = <2>; 1480 1481 interrupt-controller; 1482 #interrupt-cells = <2>; 1483 }; 1484 1485 gpio7: gpio7@ff7e0000 { 1486 compatible = "rockchip,gpio-bank"; 1487 reg = <0x0 0xff7e0000 0x0 0x100>; 1488 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1489 clocks = <&cru PCLK_GPIO7>; 1490 1491 gpio-controller; 1492 #gpio-cells = <2>; 1493 1494 interrupt-controller; 1495 #interrupt-cells = <2>; 1496 }; 1497 1498 gpio8: gpio8@ff7f0000 { 1499 compatible = "rockchip,gpio-bank"; 1500 reg = <0x0 0xff7f0000 0x0 0x100>; 1501 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1502 clocks = <&cru PCLK_GPIO8>; 1503 1504 gpio-controller; 1505 #gpio-cells = <2>; 1506 1507 interrupt-controller; 1508 #interrupt-cells = <2>; 1509 }; 1510 1511 hdmi { 1512 hdmi_cec_c0: hdmi-cec-c0 { 1513 rockchip,pins = <7 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; 1514 }; 1515 1516 hdmi_cec_c7: hdmi-cec-c7 { 1517 rockchip,pins = <7 RK_PC7 RK_FUNC_4 &pcfg_pull_none>; 1518 }; 1519 1520 hdmi_ddc: hdmi-ddc { 1521 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>, 1522 <7 20 RK_FUNC_2 &pcfg_pull_none>; 1523 }; 1524 }; 1525 1526 pcfg_pull_up: pcfg-pull-up { 1527 bias-pull-up; 1528 }; 1529 1530 pcfg_pull_down: pcfg-pull-down { 1531 bias-pull-down; 1532 }; 1533 1534 pcfg_pull_none: pcfg-pull-none { 1535 bias-disable; 1536 }; 1537 1538 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1539 bias-disable; 1540 drive-strength = <12>; 1541 }; 1542 1543 sleep { 1544 global_pwroff: global-pwroff { 1545 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; 1546 }; 1547 1548 ddrio_pwroff: ddrio-pwroff { 1549 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 1550 }; 1551 1552 ddr0_retention: ddr0-retention { 1553 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; 1554 }; 1555 1556 ddr1_retention: ddr1-retention { 1557 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; 1558 }; 1559 }; 1560 1561 edp { 1562 edp_hpd: edp-hpd { 1563 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>; 1564 }; 1565 }; 1566 1567 i2c0 { 1568 i2c0_xfer: i2c0-xfer { 1569 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, 1570 <0 16 RK_FUNC_1 &pcfg_pull_none>; 1571 }; 1572 }; 1573 1574 i2c1 { 1575 i2c1_xfer: i2c1-xfer { 1576 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, 1577 <8 5 RK_FUNC_1 &pcfg_pull_none>; 1578 }; 1579 }; 1580 1581 i2c2 { 1582 i2c2_xfer: i2c2-xfer { 1583 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, 1584 <6 10 RK_FUNC_1 &pcfg_pull_none>; 1585 }; 1586 }; 1587 1588 i2c3 { 1589 i2c3_xfer: i2c3-xfer { 1590 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, 1591 <2 17 RK_FUNC_1 &pcfg_pull_none>; 1592 }; 1593 }; 1594 1595 i2c4 { 1596 i2c4_xfer: i2c4-xfer { 1597 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, 1598 <7 18 RK_FUNC_1 &pcfg_pull_none>; 1599 }; 1600 }; 1601 1602 i2c5 { 1603 i2c5_xfer: i2c5-xfer { 1604 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, 1605 <7 20 RK_FUNC_1 &pcfg_pull_none>; 1606 }; 1607 }; 1608 1609 i2s0 { 1610 i2s0_bus: i2s0-bus { 1611 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, 1612 <6 1 RK_FUNC_1 &pcfg_pull_none>, 1613 <6 2 RK_FUNC_1 &pcfg_pull_none>, 1614 <6 3 RK_FUNC_1 &pcfg_pull_none>, 1615 <6 4 RK_FUNC_1 &pcfg_pull_none>, 1616 <6 8 RK_FUNC_1 &pcfg_pull_none>; 1617 }; 1618 }; 1619 1620 lcdc { 1621 lcdc_ctl: lcdc-ctl { 1622 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>, 1623 <1 25 RK_FUNC_1 &pcfg_pull_none>, 1624 <1 26 RK_FUNC_1 &pcfg_pull_none>, 1625 <1 27 RK_FUNC_1 &pcfg_pull_none>; 1626 }; 1627 }; 1628 1629 sdmmc { 1630 sdmmc_clk: sdmmc-clk { 1631 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; 1632 }; 1633 1634 sdmmc_cmd: sdmmc-cmd { 1635 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; 1636 }; 1637 1638 sdmmc_cd: sdmmc-cd { 1639 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; 1640 }; 1641 1642 sdmmc_bus1: sdmmc-bus1 { 1643 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; 1644 }; 1645 1646 sdmmc_bus4: sdmmc-bus4 { 1647 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, 1648 <6 17 RK_FUNC_1 &pcfg_pull_up>, 1649 <6 18 RK_FUNC_1 &pcfg_pull_up>, 1650 <6 19 RK_FUNC_1 &pcfg_pull_up>; 1651 }; 1652 }; 1653 1654 sdio0 { 1655 sdio0_bus1: sdio0-bus1 { 1656 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; 1657 }; 1658 1659 sdio0_bus4: sdio0-bus4 { 1660 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, 1661 <4 21 RK_FUNC_1 &pcfg_pull_up>, 1662 <4 22 RK_FUNC_1 &pcfg_pull_up>, 1663 <4 23 RK_FUNC_1 &pcfg_pull_up>; 1664 }; 1665 1666 sdio0_cmd: sdio0-cmd { 1667 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; 1668 }; 1669 1670 sdio0_clk: sdio0-clk { 1671 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; 1672 }; 1673 1674 sdio0_cd: sdio0-cd { 1675 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; 1676 }; 1677 1678 sdio0_wp: sdio0-wp { 1679 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; 1680 }; 1681 1682 sdio0_pwr: sdio0-pwr { 1683 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; 1684 }; 1685 1686 sdio0_bkpwr: sdio0-bkpwr { 1687 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; 1688 }; 1689 1690 sdio0_int: sdio0-int { 1691 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; 1692 }; 1693 }; 1694 1695 sdio1 { 1696 sdio1_bus1: sdio1-bus1 { 1697 rockchip,pins = <3 24 4 &pcfg_pull_up>; 1698 }; 1699 1700 sdio1_bus4: sdio1-bus4 { 1701 rockchip,pins = <3 24 4 &pcfg_pull_up>, 1702 <3 25 4 &pcfg_pull_up>, 1703 <3 26 4 &pcfg_pull_up>, 1704 <3 27 4 &pcfg_pull_up>; 1705 }; 1706 1707 sdio1_cd: sdio1-cd { 1708 rockchip,pins = <3 28 4 &pcfg_pull_up>; 1709 }; 1710 1711 sdio1_wp: sdio1-wp { 1712 rockchip,pins = <3 29 4 &pcfg_pull_up>; 1713 }; 1714 1715 sdio1_bkpwr: sdio1-bkpwr { 1716 rockchip,pins = <3 30 4 &pcfg_pull_up>; 1717 }; 1718 1719 sdio1_int: sdio1-int { 1720 rockchip,pins = <3 31 4 &pcfg_pull_up>; 1721 }; 1722 1723 sdio1_cmd: sdio1-cmd { 1724 rockchip,pins = <4 6 4 &pcfg_pull_up>; 1725 }; 1726 1727 sdio1_clk: sdio1-clk { 1728 rockchip,pins = <4 7 4 &pcfg_pull_none>; 1729 }; 1730 1731 sdio1_pwr: sdio1-pwr { 1732 rockchip,pins = <4 9 4 &pcfg_pull_up>; 1733 }; 1734 }; 1735 1736 emmc { 1737 emmc_clk: emmc-clk { 1738 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; 1739 }; 1740 1741 emmc_cmd: emmc-cmd { 1742 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; 1743 }; 1744 1745 emmc_pwr: emmc-pwr { 1746 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; 1747 }; 1748 1749 emmc_bus1: emmc-bus1 { 1750 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; 1751 }; 1752 1753 emmc_bus4: emmc-bus4 { 1754 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1755 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1756 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1757 <3 3 RK_FUNC_2 &pcfg_pull_up>; 1758 }; 1759 1760 emmc_bus8: emmc-bus8 { 1761 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1762 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1763 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1764 <3 3 RK_FUNC_2 &pcfg_pull_up>, 1765 <3 4 RK_FUNC_2 &pcfg_pull_up>, 1766 <3 5 RK_FUNC_2 &pcfg_pull_up>, 1767 <3 6 RK_FUNC_2 &pcfg_pull_up>, 1768 <3 7 RK_FUNC_2 &pcfg_pull_up>; 1769 }; 1770 }; 1771 1772 spi0 { 1773 spi0_clk: spi0-clk { 1774 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; 1775 }; 1776 spi0_cs0: spi0-cs0 { 1777 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; 1778 }; 1779 spi0_tx: spi0-tx { 1780 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; 1781 }; 1782 spi0_rx: spi0-rx { 1783 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; 1784 }; 1785 spi0_cs1: spi0-cs1 { 1786 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; 1787 }; 1788 }; 1789 spi1 { 1790 spi1_clk: spi1-clk { 1791 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; 1792 }; 1793 spi1_cs0: spi1-cs0 { 1794 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; 1795 }; 1796 spi1_rx: spi1-rx { 1797 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; 1798 }; 1799 spi1_tx: spi1-tx { 1800 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; 1801 }; 1802 }; 1803 1804 spi2 { 1805 spi2_cs1: spi2-cs1 { 1806 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; 1807 }; 1808 spi2_clk: spi2-clk { 1809 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; 1810 }; 1811 spi2_cs0: spi2-cs0 { 1812 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; 1813 }; 1814 spi2_rx: spi2-rx { 1815 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; 1816 }; 1817 spi2_tx: spi2-tx { 1818 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; 1819 }; 1820 }; 1821 1822 uart0 { 1823 uart0_xfer: uart0-xfer { 1824 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, 1825 <4 17 RK_FUNC_1 &pcfg_pull_none>; 1826 }; 1827 1828 uart0_cts: uart0-cts { 1829 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>; 1830 }; 1831 1832 uart0_rts: uart0-rts { 1833 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; 1834 }; 1835 }; 1836 1837 uart1 { 1838 uart1_xfer: uart1-xfer { 1839 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, 1840 <5 9 RK_FUNC_1 &pcfg_pull_none>; 1841 }; 1842 1843 uart1_cts: uart1-cts { 1844 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>; 1845 }; 1846 1847 uart1_rts: uart1-rts { 1848 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; 1849 }; 1850 }; 1851 1852 uart2 { 1853 uart2_xfer: uart2-xfer { 1854 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, 1855 <7 23 RK_FUNC_1 &pcfg_pull_none>; 1856 }; 1857 /* no rts / cts for uart2 */ 1858 }; 1859 1860 uart3 { 1861 uart3_xfer: uart3-xfer { 1862 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, 1863 <7 8 RK_FUNC_1 &pcfg_pull_none>; 1864 }; 1865 1866 uart3_cts: uart3-cts { 1867 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>; 1868 }; 1869 1870 uart3_rts: uart3-rts { 1871 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; 1872 }; 1873 }; 1874 1875 uart4 { 1876 uart4_xfer: uart4-xfer { 1877 rockchip,pins = <5 15 3 &pcfg_pull_up>, 1878 <5 14 3 &pcfg_pull_none>; 1879 }; 1880 1881 uart4_cts: uart4-cts { 1882 rockchip,pins = <5 12 3 &pcfg_pull_up>; 1883 }; 1884 1885 uart4_rts: uart4-rts { 1886 rockchip,pins = <5 13 3 &pcfg_pull_none>; 1887 }; 1888 }; 1889 1890 tsadc { 1891 otp_gpio: otp-gpio { 1892 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>; 1893 }; 1894 1895 otp_out: otp-out { 1896 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; 1897 }; 1898 }; 1899 1900 pwm0 { 1901 pwm0_pin: pwm0-pin { 1902 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; 1903 }; 1904 }; 1905 1906 pwm1 { 1907 pwm1_pin: pwm1-pin { 1908 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; 1909 }; 1910 }; 1911 1912 pwm2 { 1913 pwm2_pin: pwm2-pin { 1914 rockchip,pins = <7 22 3 &pcfg_pull_none>; 1915 }; 1916 }; 1917 1918 pwm3 { 1919 pwm3_pin: pwm3-pin { 1920 rockchip,pins = <7 23 3 &pcfg_pull_none>; 1921 }; 1922 }; 1923 1924 gmac { 1925 rgmii_pins: rgmii-pins { 1926 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1927 <3 31 3 &pcfg_pull_none>, 1928 <3 26 3 &pcfg_pull_none>, 1929 <3 27 3 &pcfg_pull_none>, 1930 <3 28 3 &pcfg_pull_none_12ma>, 1931 <3 29 3 &pcfg_pull_none_12ma>, 1932 <3 24 3 &pcfg_pull_none_12ma>, 1933 <3 25 3 &pcfg_pull_none_12ma>, 1934 <4 0 3 &pcfg_pull_none>, 1935 <4 5 3 &pcfg_pull_none>, 1936 <4 6 3 &pcfg_pull_none>, 1937 <4 9 3 &pcfg_pull_none_12ma>, 1938 <4 4 3 &pcfg_pull_none_12ma>, 1939 <4 1 3 &pcfg_pull_none>, 1940 <4 3 3 &pcfg_pull_none>; 1941 }; 1942 1943 rmii_pins: rmii-pins { 1944 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1945 <3 31 3 &pcfg_pull_none>, 1946 <3 28 3 &pcfg_pull_none>, 1947 <3 29 3 &pcfg_pull_none>, 1948 <4 0 3 &pcfg_pull_none>, 1949 <4 5 3 &pcfg_pull_none>, 1950 <4 4 3 &pcfg_pull_none>, 1951 <4 1 3 &pcfg_pull_none>, 1952 <4 2 3 &pcfg_pull_none>, 1953 <4 3 3 &pcfg_pull_none>; 1954 }; 1955 }; 1956 1957 spdif { 1958 spdif_tx: spdif-tx { 1959 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>; 1960 }; 1961 }; 1962 }; 1963}; 1964
