Searched refs:wrm_reg (Results 1 – 3 of 3) sorted by relevance
324 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v11_0_misc_op()325 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v11_0_misc_op()326 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v11_0_misc_op()332 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v11_0_misc_op()333 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v11_0_misc_op()334 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v11_0_misc_op()335 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; in mes_v11_0_misc_op()
814 op_input.wrm_reg.reg0 = reg0; in amdgpu_mes_reg_write_reg_wait()815 op_input.wrm_reg.reg1 = reg1; in amdgpu_mes_reg_write_reg_wait()816 op_input.wrm_reg.ref = ref; in amdgpu_mes_reg_write_reg_wait()817 op_input.wrm_reg.mask = mask; in amdgpu_mes_reg_write_reg_wait()840 op_input.wrm_reg.reg0 = reg; in amdgpu_mes_reg_wait()841 op_input.wrm_reg.ref = val; in amdgpu_mes_reg_wait()842 op_input.wrm_reg.mask = mask; in amdgpu_mes_reg_wait()
288 } wrm_reg; member
