| /Linux-v6.6/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | smu7_hwmgr.c | 746 &data->dpm_table.sclk_table, in smu7_reset_dpm_tables()
804 data->dpm_table.sclk_table.count = 0; in smu7_setup_dpm_tables_v0()
807 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != in smu7_setup_dpm_tables_v0()
809 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v0()
811 …data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0; in smu7_setup_dpm_tables_v0()
812 data->dpm_table.sclk_table.count++; in smu7_setup_dpm_tables_v0()
898 data->dpm_table.sclk_table.count = 0; in smu7_setup_dpm_tables_v1()
900 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value != in smu7_setup_dpm_tables_v1()
903 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v1()
906 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = in smu7_setup_dpm_tables_v1()
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| D | process_pptables_v1_0.c | 407 phm_ppt_v1_clock_voltage_dependency_table *sclk_table; in get_sclk_voltage_dependency_table() local
418 sclk_table = kzalloc(struct_size(sclk_table, entries, tonga_table->ucNumEntries), in get_sclk_voltage_dependency_table()
420 if (!sclk_table) in get_sclk_voltage_dependency_table()
423 sclk_table->count = (uint32_t)tonga_table->ucNumEntries; in get_sclk_voltage_dependency_table()
431 entries, sclk_table, i); in get_sclk_voltage_dependency_table()
447 sclk_table = kzalloc(struct_size(sclk_table, entries, polaris_table->ucNumEntries), in get_sclk_voltage_dependency_table()
449 if (!sclk_table) in get_sclk_voltage_dependency_table()
452 sclk_table->count = (uint32_t)polaris_table->ucNumEntries; in get_sclk_voltage_dependency_table()
460 entries, sclk_table, i); in get_sclk_voltage_dependency_table()
470 *pp_tonga_sclk_dep_table = sclk_table; in get_sclk_voltage_dependency_table()
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| D | smu7_hwmgr.h | 104 struct smu7_single_dpm_table sclk_table; member
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| D | vega10_hwmgr.c | 3417 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_find_dpm_states_clocks_in_dpm_table() local
3425 for (i = 0; i < sclk_table->count; i++) { in vega10_find_dpm_states_clocks_in_dpm_table()
3426 if (sclk == sclk_table->dpm_levels[i].value) in vega10_find_dpm_states_clocks_in_dpm_table()
3430 if (i >= sclk_table->count) { in vega10_find_dpm_states_clocks_in_dpm_table()
3431 if (sclk > sclk_table->dpm_levels[i-1].value) { in vega10_find_dpm_states_clocks_in_dpm_table()
3433 sclk_table->dpm_levels[i-1].value = sclk; in vega10_find_dpm_states_clocks_in_dpm_table()
4649 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_emit_clock_levels() local
4673 count = sclk_table->count; in vega10_emit_clock_levels()
4676 i, sclk_table->dpm_levels[i].value / 100, in vega10_emit_clock_levels()
4795 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_print_clock_levels() local
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| D | smu8_hwmgr.c | 1560 struct phm_clock_voltage_dependency_table *sclk_table = in smu8_print_clock_levels() local
1573 for (i = 0; i < sclk_table->count; i++) in smu8_print_clock_levels()
1575 i, sclk_table->entries[i].clk / 100, in smu8_print_clock_levels()
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| D | vega12_hwmgr.c | 2691 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
2694 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
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| D | vega20_hwmgr.c | 1469 struct vega20_single_dpm_table *sclk_table = in vega20_get_sclk_od() local
1473 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; in vega20_get_sclk_od()
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| /Linux-v6.6/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | vegam_smumgr.c | 888 for (i = 0; i < dpm_table->sclk_table.count; i++) { in vegam_populate_all_graphic_levels()
891 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels()
909 (uint8_t)dpm_table->sclk_table.count; in vegam_populate_all_graphic_levels()
911 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in vegam_populate_all_graphic_levels()
913 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
922 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
947 for (i = 2; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
1287 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { in vegam_program_memory_timing_parameters()
1290 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in vegam_program_memory_timing_parameters()
1374 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in vegam_populate_smc_boot_level()
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| D | polaris10_smumgr.c | 1067 for (i = 0; i < dpm_table->sclk_table.count; i++) { in polaris10_populate_all_graphic_levels()
1070 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
1084 dpm_table->sclk_table.dpm_levels[0].value, in polaris10_populate_all_graphic_levels()
1091 dividers.real_clock < dpm_table->sclk_table.dpm_levels[0].value ? in polaris10_populate_all_graphic_levels()
1098 (uint8_t)dpm_table->sclk_table.count; in polaris10_populate_all_graphic_levels()
1100 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in polaris10_populate_all_graphic_levels()
1111 for (i = 0; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
1136 for (i = 2; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
1498 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { in polaris10_program_memory_timing_parameters()
1501 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in polaris10_program_memory_timing_parameters()
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| D | fiji_smumgr.c | 1022 for (i = 0; i < dpm_table->sclk_table.count; i++) { in fiji_populate_all_graphic_levels()
1024 dpm_table->sclk_table.dpm_levels[i].value, in fiji_populate_all_graphic_levels()
1038 levels[dpm_table->sclk_table.count - 1].DisplayWatermark = in fiji_populate_all_graphic_levels()
1042 (uint8_t)dpm_table->sclk_table.count; in fiji_populate_all_graphic_levels()
1044 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in fiji_populate_all_graphic_levels()
1051 for (i = 0; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels()
1076 for (i = 2; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels()
1316 data->dpm_table.sclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1532 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in fiji_program_memory_timing_parameters()
1535 data->dpm_table.sclk_table.dpm_levels[i].value, in fiji_program_memory_timing_parameters()
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| D | tonga_smumgr.c | 710 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
712 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels()
726 if (dpm_table->sclk_table.count > 1) in tonga_populate_all_graphic_levels()
727 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in tonga_populate_all_graphic_levels()
731 (uint8_t)dpm_table->sclk_table.count; in tonga_populate_all_graphic_levels()
733 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in tonga_populate_all_graphic_levels()
740 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
770 for (i = 2; i < dpm_table->sclk_table.count; i++) in tonga_populate_all_graphic_levels()
1497 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in tonga_program_memory_timing_parameters()
1500 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in tonga_program_memory_timing_parameters()
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| D | iceland_smumgr.c | 980 for (i = 0; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
982 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
996 if (dpm_table->sclk_table.count > 1) in iceland_populate_all_graphic_levels()
997 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in iceland_populate_all_graphic_levels()
1001 (uint8_t)dpm_table->sclk_table.count; in iceland_populate_all_graphic_levels()
1003 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in iceland_populate_all_graphic_levels()
1026 for (i = 2; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
1621 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in iceland_program_memory_timing_parameters()
1624 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in iceland_program_memory_timing_parameters()
1657 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in iceland_populate_smc_boot_level()
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| D | ci_smumgr.c | 486 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
488 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
494 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
501 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
503 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
1660 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in ci_program_memory_timing_parameters()
1663 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in ci_program_memory_timing_parameters()
1696 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in ci_populate_smc_boot_level()
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| /Linux-v6.6/drivers/gpu/drm/radeon/ |
| D | ci_dpm.c | 2516 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2519 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
3250 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
3252 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
3259 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
3265 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3267 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
3425 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3440 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3443 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
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| D | ci_dpm.h | 69 struct ci_single_dpm_table sclk_table; member
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