Searched refs:lane_cnt (Results 1 – 11 of 11) sorted by relevance
259 u8 lane_cnt; member561 u8 lane_cnt; in zynqmp_dp_mode_configure() local580 for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) { in zynqmp_dp_mode_configure()585 rate = zynqmp_dp_max_rate(bw, lane_cnt, bpp); in zynqmp_dp_mode_configure()588 dp->mode.lane_cnt = lane_cnt; in zynqmp_dp_mode_configure()611 for (i = 0; i < dp->mode.lane_cnt; i++) { in zynqmp_dp_adjust_train()628 for (i = 0; i < dp->mode.lane_cnt; i++) in zynqmp_dp_adjust_train()648 dp->mode.lane_cnt); in zynqmp_dp_update_vs_emph()652 for (i = 0; i < dp->mode.lane_cnt; i++) { in zynqmp_dp_update_vs_emph()680 u8 lane_cnt = dp->mode.lane_cnt; in zynqmp_dp_link_train_cr() local[all …]
342 u8 lane_cnt = csid->phy.lane_cnt; in __csid_configure_stream() local348 if (!lane_cnt) in __csid_configure_stream()349 lane_cnt = 4; in __csid_configure_stream()440 val |= (lane_cnt - 1) << TPG_CTRL_NUM_ACTIVE_LANES; in __csid_configure_stream()446 val = (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; in __csid_configure_stream()
87 u8 lane_cnt; member
217 val = phy->lane_cnt - 1; in csid_configure_stream()
246 val = phy->lane_cnt - 1; in csid_configure_stream()
98 csid->phy.lane_cnt); in csid_set_clock_rates()767 csid->phy.lane_cnt = lane_cfg->num_data; in csid_link_setup()
25 for (i = 0; i < (phy)->lane_cnt; i++)155 ss_phy->lane_cnt = phy->attrs.bus_width; in samsung_ufs_phy_init()283 phy->lane_cnt = PHY_DEF_LANE_CNT; in samsung_ufs_phy_probe()
125 u8 lane_cnt; member
140 u16 lane_cnt:2; member
833 intel_dsi->lane_count = mipi_config->lane_cnt + 1; in intel_dsi_vbt_init()
1012 int ret = 0, lane, lane_cnt; in dp_ctrl_update_vx_px() local1043 lane_cnt = ctrl->link->link_params.num_lanes; in dp_ctrl_update_vx_px()1044 for (lane = 0; lane < lane_cnt; lane++) in dp_ctrl_update_vx_px()1051 buf, lane_cnt); in dp_ctrl_update_vx_px()1052 if (ret == lane_cnt) in dp_ctrl_update_vx_px()
