| /Linux-v6.6/drivers/gpu/drm/msm/adreno/ |
| D | a6xx_gmu.c | 19 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) in a6xx_gmu_fault() argument
21 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_fault()
26 gmu->hung = true; in a6xx_gmu_fault()
37 struct a6xx_gmu *gmu = data; in a6xx_gmu_irq() local
40 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); in a6xx_gmu_irq()
41 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); in a6xx_gmu_irq()
44 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); in a6xx_gmu_irq()
46 a6xx_gmu_fault(gmu); in a6xx_gmu_irq()
50 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); in a6xx_gmu_irq()
53 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", in a6xx_gmu_irq()
[all …]
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| D | a6xx_hfi.c | 26 static int a6xx_hfi_queue_read(struct a6xx_gmu *gmu, in a6xx_hfi_queue_read() argument
57 if (!gmu->legacy) in a6xx_hfi_queue_read()
64 static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu, in a6xx_hfi_queue_write() argument
88 if (!gmu->legacy) { in a6xx_hfi_queue_write()
96 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01); in a6xx_hfi_queue_write()
100 static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, u32 id, u32 seqnum, in a6xx_hfi_wait_for_ack() argument
103 struct a6xx_hfi_queue *queue = &gmu->queues[HFI_RESPONSE_QUEUE]; in a6xx_hfi_wait_for_ack()
108 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, in a6xx_hfi_wait_for_ack()
112 DRM_DEV_ERROR(gmu->dev, in a6xx_hfi_wait_for_ack()
119 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, in a6xx_hfi_wait_for_ack()
[all …]
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| D | a6xx_gmu.h | 101 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset) in gmu_read() argument
103 return msm_readl(gmu->mmio + (offset << 2)); in gmu_read()
106 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value) in gmu_write() argument
108 msm_writel(value, gmu->mmio + (offset << 2)); in gmu_write()
112 gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size) in gmu_write_bulk() argument
114 memcpy_toio(gmu->mmio + (offset << 2), data, size); in gmu_write_bulk()
118 static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or) in gmu_rmw() argument
120 u32 val = gmu_read(gmu, reg); in gmu_rmw()
124 gmu_write(gmu, reg, val | or); in gmu_rmw()
127 static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi) in gmu_read64() argument
[all …]
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| D | a6xx_gpu.c | 24 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu)) in _a6xx_check_idle()
702 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_set_hwcg() local
725 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); in a6xx_set_hwcg()
732 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); in a6xx_set_hwcg()
1199 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in hw_init() local
1204 ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); in hw_init()
1225 a6xx_sptprac_enable(gmu); in hw_init()
1359 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); in hw_init()
1362 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5)); in hw_init()
1363 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); in hw_init()
[all …]
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| D | a6xx_gpu.h | 23 struct a6xx_gmu gmu; member
86 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);
88 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);
90 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
91 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
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| D | a6xx_gpu_state.c | 144 if (!a6xx_gmu_sptprac_is_on(&a6xx_gpu->gmu)) in a6xx_crashdumper_run()
784 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in _a6xx_get_gmu_registers() local
804 val = gmu_read_rscc(gmu, offset); in _a6xx_get_gmu_registers()
806 val = gmu_read(gmu, offset); in _a6xx_get_gmu_registers()
833 if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) in a6xx_get_gmu_registers()
871 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_snapshot_gmu_hfi_history() local
874 BUILD_BUG_ON(ARRAY_SIZE(gmu->queues) != ARRAY_SIZE(a6xx_state->hfi_queue_history)); in a6xx_snapshot_gmu_hfi_history()
876 for (i = 0; i < ARRAY_SIZE(gmu->queues); i++) { in a6xx_snapshot_gmu_hfi_history()
877 struct a6xx_hfi_queue *queue = &gmu->queues[i]; in a6xx_snapshot_gmu_hfi_history()
1047 a6xx_state->gmu_log = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.log); in a6xx_gpu_state_get()
[all …]
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| /Linux-v6.6/arch/arm64/boot/dts/qcom/ |
| D | msm8992.dtsi | 31 gmu-sram@0 {
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| D | sm6350.dtsi | 1335 qcom,gmu = <&gmu>;
1418 gmu: gmu@3d6a000 { label
1419 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
1423 reg-names = "gmu",
1430 "gmu";
1438 "gmu",
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| D | sc8180x.dtsi | 2212 qcom,gmu = <&gmu>;
2255 gmu: gmu@2c6a000 { label
2256 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2261 reg-names = "gmu",
2267 interrupt-names = "hfi", "gmu";
2274 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
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| D | sm8350.dtsi | 1850 qcom,gmu = <&gmu>;
1914 gmu: gmu@3d6a000 { label
1915 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
1920 reg-names = "gmu", "rscc", "gmu_pdc";
1924 interrupt-names = "hfi", "gmu";
1933 clock-names = "gmu",
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| D | sc7180.dtsi | 2093 qcom,gmu = <&gmu>;
2187 gmu: gmu@506a000 { label
2188 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2191 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2194 interrupt-names = "hfi", "gmu";
2199 clock-names = "gmu", "cxo", "axi", "memnoc";
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| D | sm8150.dtsi | 2213 qcom,gmu = <&gmu>;
2265 gmu: gmu@2c6a000 { label
2266 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2271 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2275 interrupt-names = "hfi", "gmu";
2282 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
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| D | sm8150-hdk.dts | 358 &gmu {
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| D | sm8150-mtp.dts | 353 &gmu {
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| D | sm8250-hdk.dts | 368 &gmu {
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| D | sm6115.dtsi | 1344 "gmu",
1352 qcom,gmu = <&gmu_wrapper>;
1417 gmu_wrapper: gmu@596a000 {
1418 compatible = "qcom,adreno-gmu-wrapper";
1420 reg-names = "gmu";
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| D | sdm845-xiaomi-beryllium-common.dtsi | 242 &gmu {
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| D | sc8280xp.dtsi | 2359 qcom,gmu = <&gmu>;
2419 gmu: gmu@3d6a000 { label
2420 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
2424 reg-names = "gmu", "rscc", "gmu_pdc";
2427 interrupt-names = "hfi", "gmu";
2435 clock-names = "gmu",
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| D | sdm845.dtsi | 4787 qcom,gmu = <&gmu>;
4863 gmu: gmu@506a000 { label
4864 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4869 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4873 interrupt-names = "hfi", "gmu";
4879 clock-names = "gmu", "cxo", "axi", "memnoc";
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| D | sm8250.dtsi | 2603 qcom,gmu = <&gmu>;
2661 gmu: gmu@3d6a000 { label
2662 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2668 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2672 interrupt-names = "hfi", "gmu";
2679 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
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| D | sc7280.dtsi | 2570 qcom,gmu = <&gmu>;
2647 gmu: gmu@3d6a000 { label
2648 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2652 reg-names = "gmu", "rscc", "gmu_pdc";
2655 interrupt-names = "hfi", "gmu";
2663 clock-names = "gmu",
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| D | sdm850-lenovo-yoga-c630.dts | 358 &gmu {
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| D | sdm845-xiaomi-polaris.dts | 384 &gmu {
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| D | sdm845-mtp.dts | 429 &gmu {
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| D | sdm845-shift-axolotl.dts | 422 &gmu {
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