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Searched refs:emc_dbg (Results 1 – 4 of 4) sorted by relevance

/Linux-v6.6/drivers/memory/tegra/
Dtegra210-emc-cc-r21021.c36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__) macro
108 emc_dbg(emc, EMA_UPDATES, "%s: (s=%lu) EMA: %u\n", \
498 emc_dbg(emc, PER_TRAIN, "Periodic training starting\n"); in tegra210_emc_r21021_periodic_compensation()
559 emc_dbg(emc, EMA_WRITES, "0x%08x <= 0x%08x\n", in tegra210_emc_r21021_periodic_compensation()
616 u32 emc_dbg, emc_cfg_pipe_clk, emc_pin; in tegra210_emc_r21021_set_clock() local
624 emc_dbg(emc, INFO, "Running clock change.\n"); in tegra210_emc_r21021_set_clock()
661 emc_dbg = emc_readl(emc, EMC_DBG); in tegra210_emc_r21021_set_clock()
675 emc_dbg(emc, INFO, "Clock change version: %d\n", in tegra210_emc_r21021_set_clock()
677 emc_dbg(emc, INFO, "DRAM type = %d\n", dram_type); in tegra210_emc_r21021_set_clock()
678 emc_dbg(emc, INFO, "DRAM dev #: %u\n", emc->num_devices); in tegra210_emc_r21021_set_clock()
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Dtegra30-emc.c534 u32 emc_dbg; in emc_prepare_timing_change() local
555 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_prepare_timing_change()
689 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, in emc_prepare_timing_change()
693 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_prepare_timing_change()
715 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG); in emc_prepare_timing_change()
728 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_prepare_timing_change()
1120 u32 fbio_cfg5, emc_cfg, emc_dbg, emc_adr_cfg; in emc_setup_hw() local
1155 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_setup_hw()
1156 emc_dbg |= EMC_DBG_CFG_PRIORITY; in emc_setup_hw()
1157 emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY; in emc_setup_hw()
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Dtegra20-emc.c598 u32 emc_cfg, emc_dbg, emc_fbio, emc_adr_cfg; in emc_setup_hw() local
627 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_setup_hw()
628 emc_dbg |= EMC_DBG_CFG_PRIORITY; in emc_setup_hw()
629 emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY; in emc_setup_hw()
630 emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE; in emc_setup_hw()
631 emc_dbg &= ~EMC_DBG_FORCE_UPDATE; in emc_setup_hw()
632 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_setup_hw()
Dtegra210-emc-core.c886 u32 emc_dbg = emc_readl(emc, EMC_DBG); in tegra210_emc_set_shadow_bypass() local
889 emc_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG); in tegra210_emc_set_shadow_bypass()
891 emc_writel(emc, emc_dbg & ~EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG); in tegra210_emc_set_shadow_bypass()