Searched refs:dram_type (Results 1 – 13 of 13) sorted by relevance
340 ast->dram_type = AST_DRAM_1Gx16; in ast_get_dram_info()356 ast->dram_type = AST_DRAM_1Gx16; in ast_get_dram_info()360 ast->dram_type = AST_DRAM_2Gx16; in ast_get_dram_info()363 ast->dram_type = AST_DRAM_4Gx16; in ast_get_dram_info()366 ast->dram_type = AST_DRAM_8Gx16; in ast_get_dram_info()372 ast->dram_type = AST_DRAM_512Mx16; in ast_get_dram_info()376 ast->dram_type = AST_DRAM_1Gx16; in ast_get_dram_info()379 ast->dram_type = AST_DRAM_2Gx16; in ast_get_dram_info()382 ast->dram_type = AST_DRAM_4Gx16; in ast_get_dram_info()389 ast->dram_type = AST_DRAM_512Mx16; in ast_get_dram_info()[all …]
285 if (ast->dram_type == AST_DRAM_1Gx16) in ast_init_dram_reg()287 else if (ast->dram_type == AST_DRAM_1Gx32) in ast_init_dram_reg()361 u32 dram_type; member1585 param.dram_type = AST_DDR3; in ast_post_chip_2300()1588 param.dram_type = AST_DDR2; in ast_post_chip_2300()1623 if (param.dram_type == AST_DDR3) { in ast_post_chip_2300()
189 uint32_t dram_type; member
46 static int dram_type; variable53 switch (dram_type) { in mt7620_dram_init()79 switch (dram_type) { in mt7628_dram_init()233 dram_type = cfg0 & DRAM_TYPE_MT7628_MASK; in prom_soc_init()235 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & in prom_soc_init()237 if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN) in prom_soc_init()238 dram_type = SYSCFG0_DRAM_TYPE_SDRAM; in prom_soc_init()
619 u32 value, dram_type; in tegra210_emc_r21021_set_clock() local631 dram_type = value >> EMC_FBIO_CFG5_DRAM_TYPE_SHIFT; in tegra210_emc_r21021_set_clock()638 dram_type == DRAM_TYPE_LPDDR4) in tegra210_emc_r21021_set_clock()641 if (dram_type == DRAM_TYPE_DDR3) in tegra210_emc_r21021_set_clock()645 (dram_type == DRAM_TYPE_LPDDR2)) in tegra210_emc_r21021_set_clock()677 emc_dbg(emc, INFO, "DRAM type = %d\n", dram_type); in tegra210_emc_r21021_set_clock()863 if (src_clk_period > 50000 && dram_type == DRAM_TYPE_LPDDR4) in tegra210_emc_r21021_set_clock()874 if (dram_type == DRAM_TYPE_LPDDR4) in tegra210_emc_r21021_set_clock()876 else if (dram_type == DRAM_TYPE_LPDDR2 || is_lpddr3) in tegra210_emc_r21021_set_clock()879 else if (dram_type == DRAM_TYPE_DDR3) in tegra210_emc_r21021_set_clock()[all …]
490 enum emc_dram_type dram_type; member629 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()724 if (emc->dram_type == DRAM_TYPE_DDR3 && in tegra_emc_prepare_timing_change()751 if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF) in tegra_emc_prepare_timing_change()757 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()766 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()774 if (emc->dram_type == DRAM_TYPE_DDR3) { in tegra_emc_prepare_timing_change()849 if (emc->dram_type == DRAM_TYPE_LPDDR3 && in tegra_emc_complete_timing_change()857 if (emc->dram_type == DRAM_TYPE_DDR3 && in tegra_emc_complete_timing_change()901 emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5); in emc_init()[all …]
527 enum emc_dram_type dram_type; in emc_prepare_timing_change() local572 dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK; in emc_prepare_timing_change()648 if (dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_ON) { in emc_prepare_timing_change()701 if (dram_type == DRAM_TYPE_DDR3) { in emc_prepare_timing_change()731 if (dram_type == DRAM_TYPE_DDR3) in emc_prepare_timing_change()736 if (dram_type == DRAM_TYPE_DDR3) { in emc_prepare_timing_change()1123 enum emc_dram_type dram_type; in emc_setup_hw() local1128 dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK; in emc_setup_hw()1136 switch (dram_type) { in emc_setup_hw()1162 switch (dram_type) { in emc_setup_hw()[all …]
601 enum emc_dram_type dram_type; in emc_setup_hw() local641 dram_type = FIELD_GET(EMC_FBIO_CFG5_DRAM_TYPE, emc_fbio); in emc_setup_hw()643 switch (dram_type) { in emc_setup_hw()665 if (dram_type == DRAM_TYPE_LPDDR2) { in emc_setup_hw()
772 if ((emc->dram_type != DRAM_TYPE_LPDDR2 && in tegra210_emc_set_refresh()773 emc->dram_type != DRAM_TYPE_LPDDR4) || in tegra210_emc_set_refresh()1774 emc->dram_type = value & 0x3; in tegra210_emc_detect()
908 unsigned int dram_type; member
1428 if (pvt->dram_type == MEM_LRDDR3) { in debug_dump_dramcfg_low()1636 if (umc->dram_type == MEM_LRDDR4 || umc->dram_type == MEM_LRDDR5) { in umc_dump_misc_regs()1818 umc->dram_type = MEM_EMPTY; in umc_determine_memory_type()1828 umc->dram_type = MEM_LRDDR5; in umc_determine_memory_type()1830 umc->dram_type = MEM_RDDR5; in umc_determine_memory_type()1832 umc->dram_type = MEM_DDR5; in umc_determine_memory_type()1835 umc->dram_type = MEM_LRDDR4; in umc_determine_memory_type()1837 umc->dram_type = MEM_RDDR4; in umc_determine_memory_type()1839 umc->dram_type = MEM_DDR4; in umc_determine_memory_type()1842 edac_dbg(1, " UMC%d DIMM type: %s\n", i, edac_mem_types[umc->dram_type]); in umc_determine_memory_type()[all …]
234 u32 nr_pages, dram_type; in init_csrows() local265 dram_type = (reg04 & ASPEED_MCR_CONF_DRAM_TYPE) ? MEM_DDR4 : MEM_DDR3; in init_csrows()268 dimm->mtype = dram_type; in init_csrows()
315 enum mem_type dram_type; member384 enum mem_type dram_type; member
