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Searched refs:SH_RD (Results 1 – 2 of 2) sorted by relevance

/Linux-v6.6/arch/riscv/kernel/
Dtraps_misaligned.c98 #define SH_RD 7 macro
119 #define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
143 #define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
273 insn = RVC_RS2S(insn) << SH_RD; in handle_misaligned_load()
275 ((insn >> SH_RD) & 0x1f)) { in handle_misaligned_load()
282 insn = RVC_RS2S(insn) << SH_RD; in handle_misaligned_load()
284 ((insn >> SH_RD) & 0x1f)) { in handle_misaligned_load()
290 insn = RVC_RS2S(insn) << SH_RD; in handle_misaligned_load()
298 insn = RVC_RS2S(insn) << SH_RD; in handle_misaligned_load()
346 ((insn >> SH_RD) & 0x1f)) { in handle_misaligned_store()
[all …]
/Linux-v6.6/arch/riscv/kvm/
Dvcpu_insn.c83 #define SH_RD 7 macro
105 #define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
129 #define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
240 if ((insn >> SH_RD) & MASK_RX) in kvm_riscv_vcpu_csr_return()
513 insn = RVC_RS2S(insn) << SH_RD; in kvm_riscv_vcpu_mmio_load()
515 ((insn >> SH_RD) & 0x1f)) { in kvm_riscv_vcpu_mmio_load()
522 insn = RVC_RS2S(insn) << SH_RD; in kvm_riscv_vcpu_mmio_load()
524 ((insn >> SH_RD) & 0x1f)) { in kvm_riscv_vcpu_mmio_load()
631 ((insn >> SH_RD) & 0x1f)) { in kvm_riscv_vcpu_mmio_store()
639 ((insn >> SH_RD) & 0x1f)) { in kvm_riscv_vcpu_mmio_store()