Searched refs:SDP (Results 1 – 16 of 16) sorted by relevance
4 SDP Main Board with an AXC001 CPU Card hoisting ARC700 core in silicon
4 SDP Main Board with an AXC003 FPGA Card which can contain various flavours of
7 /* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
10 model = "TI OMAP2430 SDP";
10 model = "TI OMAP3430 SDP";
12 model = "TI OMAP4 SDP board";
7 * Device Tree for AXS103 SDP with AXS10X Main Board and
16 Data Port (SDP) and DCN. This component has multiple features, such as memory53 pipeline is connected to the Scalable Data Port (SDP) via DCHUB; you can see54 the SDP as the element from our Data Fabric that feeds the display pipe.
215 SDP
35 - OMAP3 SDP board233 Default setup on OMAP3 SDP236 Here's the default setup on OMAP3 SDP board. All planes go to LCD. DVI
147 #define SDP 0x01 /* sta: scsi parity signal */ macro
668 #define SDP 0x01 /* sta: scsi parity signal */ macro
527 connection made (e.g. A configured SDP should output a maximum598 "Unknown", "SDP", "DCP", "CDP", "ACA", "C", "PD",
338 panel (found on the Zoom2/3/3630 SDP boards). To compile this driver
20773 SYNOPSYS ARC HSDK SDP pll clock driver20779 SYNOPSYS ARC SDP clock driver20785 SYNOPSYS ARC SDP platform support
