Searched refs:RGMII (Results 1 – 25 of 48) sorted by relevance
12
| /Linux-v6.6/include/dt-bindings/phy/ |
| D | phy-lan966x-serdes.h | 10 #define RGMII(x) (SERDES6G_MAX + 1 + (x)) macro
11 #define RGMII_MAX RGMII(2)
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| /Linux-v6.6/Documentation/devicetree/bindings/net/ |
| D | ibm,emac.txt | 5 special McMAL DMA controller, and sometimes an RGMII or ZMII
55 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
56 of the RGMII device node.
58 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
59 RGMII channel is used by this EMAC.
195 iv) RGMII node
203 - revision : as provided by the RGMII new version register if
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| D | apm-xgene-enet.txt | 8 - "apm,xgene-enet": RGMII based 1G interface
42 - tx-delay: Delay value for RGMII bridge TX clock.
46 - rx-delay: Delay value for RGMII bridge RX clock.
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| D | cavium-pip.txt | 40 - rx-delay: Delay value for RGMII receive clock. Optional. Disabled if 0.
43 - tx-delay: Delay value for RGMII transmit clock. Optional. Disabled if 0.
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| D | snps,dwc-qos-ethernet.txt | 29 In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX
34 In some configurations (e.g. GMII/RGMII), this clock is derived from the
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| /Linux-v6.6/arch/arm64/boot/dts/freescale/ |
| D | fsl-lx2160a-bluebox3-rev-a.dts | 15 /* The RGMII PHYs have a different MDIO address */
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| D | fsl-ls1028a-kontron-sl28-var4.dts | 6 * extends the base and provides one more port connected via RGMII.
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| D | fsl-ls1028a-kontron-sl28-var1.dts | 7 * port is connected via RGMII. This port is not TSN aware.
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| /Linux-v6.6/arch/arm64/boot/dts/amlogic/ |
| D | meson-gxm-vega-s96.dts | 28 /* External PHY is in RGMII */
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| D | meson-gxm-q200.dts | 53 /* External PHY is in RGMII */
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| D | meson-gxl-s905d-p230.dts | 71 /* External PHY is in RGMII */
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| D | meson-gxbb-odroidc2.dts | 290 "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
292 "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
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| D | meson-gxbb-nanopi-k2.dts | 247 "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
249 "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
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| D | meson-gxm-nexbox-a1.dts | 164 /* External PHY is in RGMII */
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| /Linux-v6.6/drivers/phy/microchip/ |
| D | lan966x_serdes.c | 99 SERDES_MUX_RGMII(RGMII(0), 2, HSIO_HW_CFG_RGMII_0_CFG |
105 SERDES_MUX_RGMII(RGMII(1), 3, HSIO_HW_CFG_RGMII_1_CFG |
111 SERDES_MUX_RGMII(RGMII(0), 5, HSIO_HW_CFG_RGMII_0_CFG |
117 SERDES_MUX_RGMII(RGMII(1), 6, HSIO_HW_CFG_RGMII_1_CFG |
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| /Linux-v6.6/arch/powerpc/boot/dts/ |
| D | kmeter1.dts | 314 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
330 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
457 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
464 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
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| D | fsp2.dts | 538 rgmii-device = <&RGMII>;
564 rgmii-device = <&RGMII>;
568 RGMII: rgmii@b0000600 { label
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| /Linux-v6.6/drivers/net/pcs/ |
| D | Kconfig | 33 on RZ/N1 SoCs. This PCS converts MII to RMII/RGMII or can be set in
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| /Linux-v6.6/arch/arm/boot/dts/microchip/ |
| D | at91-sama5d3_eds.dts | 211 /* Reserved for reset signal to the RGMII connector. */
217 /* Reserved for an interrupt line from the RMII and RGMII connectors. */
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| /Linux-v6.6/Documentation/networking/ |
| D | phy.rst | 72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
95 Whenever possible, use the PHY side RGMII delay for these reasons:
119 required delays, as defined per the RGMII standard, several options may be
124 option to insert the expected 2ns RGMII delay.
129 Common problems with RGMII delay mismatch
132 When there is a RGMII delay mismatch between the Ethernet MAC and the PHY, this
205 RGMII, and SGMII. See "PHY interface mode" below. For a full
547 RGMII v1.3:
550 RGMII v2.0:
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| /Linux-v6.6/arch/mips/ralink/ |
| D | Kconfig | 65 dual-core CPU, a 5-port 10/100/1000 switch/PHY and one RGMII.
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| /Linux-v6.6/Documentation/networking/dsa/ |
| D | bcm_sf2.rst | 19 - several external MII/RevMII/GMII/RGMII interfaces
105 - turning off RGMII data processing logic when the link goes down
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| D | sja1105.rst | 358 RGMII fixed-link and internal delays
363 correct RGMII timing budget.
370 In RGMII the clock frequency changes with link speed (125 MHz at 1000 Mbps, 25
373 In the situation where the switch port is connected through an RGMII fixed-link
377 The take-away is that in RGMII mode, the switch's internal delays are only
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| /Linux-v6.6/arch/arm/boot/dts/nxp/imx/ |
| D | imx6qdl-wandboard-revd1.dtsi | 147 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */
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| D | imx6qp-prtwd3.dts | 460 /* Configure clock provider for RGMII ref clock */
462 /* Configure clock consumer for RGMII ref clock */
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