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Searched refs:PA_CL_UCP_0_W__DATA_REGISTER__SHIFT (Results 1 – 13 of 13) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h5671 #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x00000000 macro
Dgfx_7_2_sh_mask.h5618 #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 macro
Dgfx_8_0_sh_mask.h6406 #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 macro
Dgfx_8_1_sh_mask.h6940 #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 macro
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h15468 #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT … macro
Dgc_9_2_1_sh_mask.h16649 #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT … macro
Dgc_9_4_3_sh_mask.h18948 #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT … macro
Dgc_9_1_sh_mask.h16777 #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT … macro
Dgc_9_4_2_sh_mask.h8898 #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT … macro
Dgc_11_0_0_sh_mask.h20566 #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT … macro
Dgc_10_1_0_sh_mask.h22970 #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT … macro
Dgc_11_0_3_sh_mask.h22896 #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT … macro
Dgc_10_3_0_sh_mask.h21078 #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT … macro