Searched refs:EMC_XM2DQSPADCTRL2 (Results 1 – 5 of 5) sorted by relevance
401 0x0800211c /* EMC_XM2DQSPADCTRL2 */505 0x0800211c /* EMC_XM2DQSPADCTRL2 */609 0x0800211c /* EMC_XM2DQSPADCTRL2 */713 0x0800211c /* EMC_XM2DQSPADCTRL2 */815 0x0800013d /* EMC_XM2DQSPADCTRL2 */918 0x0600013d /* EMC_XM2DQSPADCTRL2 */1026 0x0800211c /* EMC_XM2DQSPADCTRL2 */1130 0x0800211c /* EMC_XM2DQSPADCTRL2 */1234 0x0800211c /* EMC_XM2DQSPADCTRL2 */1338 0x0800211c /* EMC_XM2DQSPADCTRL2 */[all …]
96 0x0800013d /* EMC_XM2DQSPADCTRL2 */200 0x0800013d /* EMC_XM2DQSPADCTRL2 */303 0x0800013d /* EMC_XM2DQSPADCTRL2 */
2739 0x0800211c /* EMC_XM2DQSPADCTRL2 */2841 0x0800211c /* EMC_XM2DQSPADCTRL2 */2943 0x0800211c /* EMC_XM2DQSPADCTRL2 */3045 0x0800211c /* EMC_XM2DQSPADCTRL2 */3145 0x0800013d /* EMC_XM2DQSPADCTRL2 */3246 0x0600013d /* EMC_XM2DQSPADCTRL2 */3352 0x0800211c /* EMC_XM2DQSPADCTRL2 */3454 0x0800211c /* EMC_XM2DQSPADCTRL2 */3556 0x0800211c /* EMC_XM2DQSPADCTRL2 */3658 0x0800211c /* EMC_XM2DQSPADCTRL2 */[all …]
160 #define EMC_XM2DQSPADCTRL2 0x2fc macro662 val = readl(emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()676 writel(val, emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()700 writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()
108 #define EMC_XM2DQSPADCTRL2 0x2fc macro310 [71] = EMC_XM2DQSPADCTRL2,465 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL2); in emc_dqs_preset()469 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL2); in emc_dqs_preset()
