Searched refs:DPLL_FPA01_P1_POST_DIV_SHIFT (Results 1 – 6 of 6) sorted by relevance
344 DPLL_FPA01_P1_POST_DIV_SHIFT); in psb_intel_crtc_clock_get()360 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in psb_intel_crtc_clock_get()
875 DPLL_FPA01_P1_POST_DIV_SHIFT); in cdv_intel_crtc_clock_get()895 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in cdv_intel_crtc_clock_get()
254 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 macro
838 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()844 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()898 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()903 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()1109 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
3866 DPLL_FPA01_P1_POST_DIV_SHIFT); in i9xx_crtc_clock_get()3897 DPLL_FPA01_P1_POST_DIV_SHIFT); in i9xx_crtc_clock_get()3908 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in i9xx_crtc_clock_get()7881 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | in i830_enable_pipe()
1478 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 macro
