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Searched refs:CGU_CLK_DIV (Results 1 – 10 of 10) sorted by relevance

/Linux-v6.6/drivers/clk/ingenic/
Djz4740-cgu.c95 "pll half", CGU_CLK_DIV,
104 "cclk", CGU_CLK_DIV,
118 "hclk", CGU_CLK_DIV,
127 "pclk", CGU_CLK_DIV,
136 "mclk", CGU_CLK_DIV,
150 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
160 "lcd_pclk", CGU_CLK_DIV,
166 "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
174 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
182 "mmc", CGU_CLK_DIV | CGU_CLK_GATE,
[all …]
Djz4770-cgu.c151 "cclk", CGU_CLK_DIV,
164 "h0clk", CGU_CLK_DIV,
172 "h1clk", CGU_CLK_DIV | CGU_CLK_GATE,
181 "h2clk", CGU_CLK_DIV,
189 "c1clk", CGU_CLK_DIV | CGU_CLK_GATE,
198 "pclk", CGU_CLK_DIV,
209 "mmc0_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
216 "mmc1_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
223 "mmc2_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
230 "cim", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
[all …]
Djz4760-cgu.c143 "cclk", CGU_CLK_DIV,
156 "hclk", CGU_CLK_DIV,
164 "sclk", CGU_CLK_DIV,
172 "h2clk", CGU_CLK_DIV,
180 "mclk", CGU_CLK_DIV,
193 "pclk", CGU_CLK_DIV,
204 "pll0_half", CGU_CLK_DIV,
215 "uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
222 "gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
229 "lpclk_div", CGU_CLK_DIV | CGU_CLK_MUX,
[all …]
Djz4755-cgu.c77 "pll half", CGU_CLK_DIV,
86 "ext half", CGU_CLK_DIV,
95 "cclk", CGU_CLK_DIV,
104 "hclk", CGU_CLK_DIV,
113 "pclk", CGU_CLK_DIV,
122 "mclk", CGU_CLK_DIV,
131 "h1clk", CGU_CLK_DIV,
140 "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
148 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
155 "mmc", CGU_CLK_DIV,
[all …]
Djz4725b-cgu.c80 "pll half", CGU_CLK_DIV,
89 "cclk", CGU_CLK_DIV,
103 "hclk", CGU_CLK_DIV,
112 "pclk", CGU_CLK_DIV,
121 "mclk", CGU_CLK_DIV,
135 "ipu", CGU_CLK_DIV | CGU_CLK_GATE,
145 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
152 "i2s", CGU_CLK_MUX | CGU_CLK_DIV,
159 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
167 "mmc_mux", CGU_CLK_DIV,
[all …]
Djz4780-cgu.c343 "cpu", CGU_CLK_DIV,
354 "l2cache", CGU_CLK_DIV,
365 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
380 "ahb2", CGU_CLK_DIV,
386 "pclk", CGU_CLK_DIV,
392 "ddr", CGU_CLK_MUX | CGU_CLK_DIV,
404 "vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
413 "i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV,
426 "lcd0pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
434 "lcd1pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
[all …]
Dx1830-cgu.c227 "cpu", CGU_CLK_DIV | CGU_CLK_GATE,
235 "l2cache", CGU_CLK_DIV,
246 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
259 "ahb2", CGU_CLK_DIV,
265 "pclk", CGU_CLK_DIV | CGU_CLK_GATE,
272 "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
285 "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
294 "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
310 "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
317 "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
[all …]
Dx1000-cgu.c286 "cpu", CGU_CLK_DIV | CGU_CLK_GATE,
298 "l2cache", CGU_CLK_DIV,
309 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
322 "ahb2", CGU_CLK_DIV,
328 "pclk", CGU_CLK_DIV | CGU_CLK_GATE,
335 "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
348 "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
387 "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
401 "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
408 "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
[all …]
Dcgu.c415 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_recalc_rate()
501 if (clk_info->type & CGU_CLK_DIV) in ingenic_clk_determine_rate()
535 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_set_rate()
693 if (caps & CGU_CLK_DIV) { in ingenic_register_clock()
694 caps &= ~CGU_CLK_DIV; in ingenic_register_clock()
Dcgu.h167 CGU_CLK_DIV = BIT(5), enumerator