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Searched refs:rfHSSIPara2 (Results 1 – 12 of 12) sorted by relevance

/Linux-v6.1/drivers/staging/rtl8723bs/hal/
Drtl8723b_rf6052.c116 …PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 825… in phy_RF6052_Config_ParaFile()
119 …PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255… in phy_RF6052_Config_ParaFile()
Drtl8723b_phycfg.c325 …pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parameter2… in phy_InitBBRFRegisterDefinition()
326 …pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; /* wire control parameter2… in phy_InitBBRFRegisterDefinition()
/Linux-v6.1/drivers/staging/rtl8192e/rtl8192e/
Dr8190P_rtl8256.c92 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, in rtl92e_config_rf()
94 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, in rtl92e_config_rf()
Dr8192E_phy.c122 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, in _rtl92e_phy_rf_read()
124 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); in _rtl92e_phy_rf_read()
125 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); in _rtl92e_phy_rf_read()
404 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; in _rtl92e_init_bb_rf_reg_def()
405 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; in _rtl92e_init_bb_rf_reg_def()
406 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; in _rtl92e_init_bb_rf_reg_def()
407 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; in _rtl92e_init_bb_rf_reg_def()
Dr8190P_def.h113 u32 rfHSSIPara2; member
/Linux-v6.1/drivers/staging/rtl8192u/
Dr8190_rtl8256.c152 …rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 0 to 4 bits for Z-se… in phy_rf8256_config_para_file()
153 …rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for Z-seri… in phy_rf8256_config_para_file()
Dr819xU_phy.c165 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, in rtl8192_phy_RFSerialRead()
168 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); in rtl8192_phy_RFSerialRead()
169 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); in rtl8192_phy_RFSerialRead()
615 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; in rtl8192_InitBBRFRegDef()
616 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; in rtl8192_InitBBRFRegDef()
617 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; in rtl8192_InitBBRFRegDef()
618 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; in rtl8192_InitBBRFRegDef()
Dr8192U.h625 u32 rfHSSIPara2; member
/Linux-v6.1/drivers/staging/r8188eu/include/
DHal8188EPhyCfg.h42 u32 rfHSSIPara2; /* wire parameter control2 : */ member
/Linux-v6.1/drivers/staging/rtl8723bs/include/
Dhal_com_phycfg.h45 u32 rfHSSIPara2; /* wire parameter control2 : */ member
/Linux-v6.1/drivers/staging/r8188eu/hal/
Drtl8188e_rf6052.c392 …rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bit… in phy_RF6052_Config_ParaFile()
395 …rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits… in phy_RF6052_Config_ParaFile()
Drtl8188e_phycfg.c145 rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2); in phy_RFSerialRead()
379 pHalData->PHYRegDef.rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parameter2 */ in phy_InitBBRFRegisterDefinition()