Searched refs:region_base (Results 1 – 9 of 9) sorted by relevance
241 u64 bar_phys_base, region_base, region_end_address; in hl_pci_set_inbound_region() local250 region_base = bar_phys_base + pci_region->offset_in_bar; in hl_pci_set_inbound_region()251 region_end_address = region_base + pci_region->size - 1; in hl_pci_set_inbound_region()254 lower_32_bits(region_base)); in hl_pci_set_inbound_region()256 upper_32_bits(region_base)); in hl_pci_set_inbound_region()354 if ((addr >= region->region_base) && in hl_get_pci_memory_region()355 (addr < region->region_base + region->region_size)) in hl_get_pci_memory_region()
928 unsigned long base_ptr, region_base, region_size; in octeon_prune_device_tree() local955 region_base = mio_boot_reg_cfg.s.base << 16; in octeon_prune_device_tree()957 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base in octeon_prune_device_tree()958 && base_ptr < region_base + region_size) { in octeon_prune_device_tree()1010 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); in octeon_prune_device_tree()1011 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); in octeon_prune_device_tree()1032 unsigned long base_ptr, region_base, region_size; in octeon_prune_device_tree() local1045 region_base = mio_boot_reg_cfg.s.base << 16; in octeon_prune_device_tree()1047 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base in octeon_prune_device_tree()1048 && base_ptr < region_base + region_size) in octeon_prune_device_tree()[all …]
58 region->region_base = bar_base_addr; in hl_set_dram_bar()76 acc_addr = hdev->pcie_bar[region->bar_id] + addr - region->region_base + in hl_access_sram_dram_region()241 *val = RREG32(addr - cfg_region->region_base); in hl_access_cfg_region()244 WREG32(addr - cfg_region->region_base, *val); in hl_access_cfg_region()247 val_l = RREG32(addr - cfg_region->region_base); in hl_access_cfg_region()248 val_h = RREG32(addr + sizeof(u32) - cfg_region->region_base); in hl_access_cfg_region()253 WREG32(addr - cfg_region->region_base, lower_32_bits(*val)); in hl_access_cfg_region()254 WREG32(addr + sizeof(u32) - cfg_region->region_base, upper_32_bits(*val)); in hl_access_cfg_region()
1860 if (end_addr >= region->region_base + region->region_size) { in hl_fw_dynamic_validate_memory_bound()1872 if (end_addr >= region->region_base - region->offset_in_bar + in hl_fw_dynamic_validate_memory_bound()1966 device_addr = region->region_base + response->ram_offset; in hl_fw_dynamic_validate_response()2130 (addr - region->region_base); in hl_fw_dynamic_copy_image()2162 (addr - region->region_base); in hl_fw_dynamic_copy_msg()
785 if (addr >= mem_reg->region_base && in hl_access_dev_mem_by_region()786 addr <= mem_reg->region_base + mem_reg->region_size - acc_size) { in hl_access_dev_mem_by_region()
1264 u64 region_base; member
933 region->region_base = CFG_BASE; in goya_set_pci_memory_regions()942 region->region_base = SRAM_BASE_ADDR; in goya_set_pci_memory_regions()951 region->region_base = DRAM_PHYS_BASE; in goya_set_pci_memory_regions()
1809 region->region_base = CFG_BASE; in gaudi_set_pci_memory_regions()1818 region->region_base = SRAM_BASE_ADDR; in gaudi_set_pci_memory_regions()1827 region->region_base = DRAM_PHYS_BASE; in gaudi_set_pci_memory_regions()1836 region->region_base = PSOC_SCRATCHPAD_ADDR; in gaudi_set_pci_memory_regions()
2893 region->region_base = CFG_BASE; in gaudi2_set_pci_memory_regions()2902 region->region_base = SRAM_BASE_ADDR; in gaudi2_set_pci_memory_regions()2911 region->region_base = DRAM_PHYS_BASE; in gaudi2_set_pci_memory_regions()
