Searched refs:pll_ctl_val (Results 1 – 1 of 1) sorted by relevance
751 unsigned pll_ctl_val = omap_readw(DPLL_CTL); in omap1_clk_init() local754 if (pll_ctl_val & 0x10) { in omap1_clk_init()756 if (pll_ctl_val & 0xf80) in omap1_clk_init()757 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; in omap1_clk_init()758 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; in omap1_clk_init()761 switch (pll_ctl_val & 0xc) { in omap1_clk_init()
