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Searched refs:mmCP_WAIT_SEM_ADDR_HI_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h4736 #define mmCP_WAIT_SEM_ADDR_HI_BASE_IDX … macro
Dgc_9_1_offset.h4966 #define mmCP_WAIT_SEM_ADDR_HI_BASE_IDX … macro
Dgc_9_2_1_offset.h4922 #define mmCP_WAIT_SEM_ADDR_HI_BASE_IDX … macro
Dgc_10_1_0_offset.h7210 #define mmCP_WAIT_SEM_ADDR_HI_BASE_IDX … macro
Dgc_10_3_0_offset.h6841 #define mmCP_WAIT_SEM_ADDR_HI_BASE_IDX … macro