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Searched refs:UVD_SUVD_CGC_CTRL__SRE_MODE_MASK (Results 1 – 17 of 17) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h255 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK … macro
Duvd_5_0_sh_mask.h785 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1 macro
Duvd_6_0_sh_mask.h779 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1 macro
/Linux-v6.1/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c712 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | in uvd_v5_0_set_sw_clock_gating()
Dvcn_v4_0.c724 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v4_0_disable_clock_gating()
840 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v4_0_enable_clock_gating()
Dvcn_v1_0.c554 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v1_0_disable_clock_gating()
626 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v1_0_enable_clock_gating()
Dvcn_v2_0.c579 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v2_0_disable_clock_gating()
688 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v2_0_enable_clock_gating()
Dvcn_v2_5.c649 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v2_5_disable_clock_gating()
759 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v2_5_enable_clock_gating()
Dvcn_v3_0.c801 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v3_0_disable_clock_gating()
917 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK in vcn_v3_0_enable_clock_gating()
Duvd_v6_0.c1370 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | in uvd_v6_0_set_sw_clock_gating()
Duvd_v7_0.c1652 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h547 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK … macro
Dvcn_2_5_sh_mask.h2180 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK … macro
Dvcn_2_0_0_sh_mask.h3306 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK … macro
Dvcn_2_6_0_sh_mask.h3851 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK … macro
Dvcn_3_0_0_sh_mask.h2937 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK … macro
Dvcn_4_0_0_sh_mask.h2865 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK … macro