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Searched refs:REG_FIELD_GET (Results 1 – 25 of 25) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_fw.c96 u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, val); in guc_ready()
132 REG_FIELD_GET(GS_MIA_IN_RESET, status), in guc_wait_ucode()
133 REG_FIELD_GET(GS_BOOTROM_MASK, status), in guc_wait_ucode()
134 REG_FIELD_GET(GS_UKERNEL_MASK, status), in guc_wait_ucode()
135 REG_FIELD_GET(GS_MIA_MASK, status), in guc_wait_ucode()
136 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); in guc_wait_ucode()
143 if (REG_FIELD_GET(GS_UKERNEL_MASK, status) == INTEL_GUC_LOAD_STATUS_EXCEPTION) { in guc_wait_ucode()
Dintel_guc_slpc.c350 return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK, in slpc_decode_min_freq()
361 return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK, in slpc_decode_max_freq()
/Linux-v6.1/drivers/gpu/drm/i915/display/
Dintel_color.c436 entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8); in i9xx_lut_8_pack()
437 entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8); in i9xx_lut_8_pack()
438 entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8); in i9xx_lut_8_pack()
459 entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 | in i965_lut_10p6_pack()
460 REG_FIELD_GET(PALETTE_RED_MASK, ldw); in i965_lut_10p6_pack()
461 entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 | in i965_lut_10p6_pack()
462 REG_FIELD_GET(PALETTE_GREEN_MASK, ldw); in i965_lut_10p6_pack()
463 entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 | in i965_lut_10p6_pack()
464 REG_FIELD_GET(PALETTE_BLUE_MASK, ldw); in i965_lut_10p6_pack()
482 entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10); in ilk_lut_10_pack()
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Dintel_bw.c48 dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val); in dg1_mchbar_read_qgv_point_info()
63 sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val); in dg1_mchbar_read_qgv_point_info()
64 sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val); in dg1_mchbar_read_qgv_point_info()
67 sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val); in dg1_mchbar_read_qgv_point_info()
68 sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val); in dg1_mchbar_read_qgv_point_info()
152 dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); in mtl_read_qgv_point_info()
154 sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); in mtl_read_qgv_point_info()
155 sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val); in mtl_read_qgv_point_info()
157 sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2); in mtl_read_qgv_point_info()
158 sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2); in mtl_read_qgv_point_info()
Dintel_lvds.c165 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); in intel_lvds_pps_get_hw_state()
166 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
167 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
170 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
171 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
174 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); in intel_lvds_pps_get_hw_state()
175 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
Dintel_vrr.c251 REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl); in intel_vrr_get_config()
255 REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl); in intel_vrr_get_config()
Dskl_watermark.c80 return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val); in intel_sagv_block_time()
742 REG_FIELD_GET(PLANE_BUF_START_MASK, reg), in skl_ddb_entry_init_from_hw()
743 REG_FIELD_GET(PLANE_BUF_END_MASK, reg)); in skl_ddb_entry_init_from_hw()
2820 level->blocks = REG_FIELD_GET(PLANE_WM_BLOCKS_MASK, val); in skl_wm_level_from_reg_val()
2821 level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val); in skl_wm_level_from_reg_val()
3225 wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); in mtl_read_wm_latency()
3226 wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); in mtl_read_wm_latency()
3229 wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); in mtl_read_wm_latency()
3230 wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); in mtl_read_wm_latency()
3233 wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); in mtl_read_wm_latency()
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Dintel_snps_phy.c1869 refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1; in intel_mpllb_calc_port_clock()
1871 frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1); in intel_mpllb_calc_port_clock()
1874 frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2); in intel_mpllb_calc_port_clock()
1875 frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2); in intel_mpllb_calc_port_clock()
1876 frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1); in intel_mpllb_calc_port_clock()
1879 multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16; in intel_mpllb_calc_port_clock()
1881 tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div); in intel_mpllb_calc_port_clock()
Dintel_pps.c1125 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); in intel_pps_readout_hw_state()
1126 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on); in intel_pps_readout_hw_state()
1127 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
1128 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
1135 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; in intel_pps_readout_hw_state()
1137 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000; in intel_pps_readout_hw_state()
Di9xx_plane.c686 *pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val); in i9xx_plane_get_hw_state()
1039 fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1; in i9xx_get_initial_plane_config()
1040 fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1; in i9xx_get_initial_plane_config()
Dskl_universal_plane.c2415 alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl); in skl_get_initial_plane_config()
2417 alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val); in skl_get_initial_plane_config()
2502 fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1; in skl_get_initial_plane_config()
2503 fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1; in skl_get_initial_plane_config()
2508 fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult; in skl_get_initial_plane_config()
Dintel_dpll_mgr.c2263 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, pll_state->pll0) << 22; in bxt_ddi_pll_get_freq()
2265 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, pll_state->pll2); in bxt_ddi_pll_get_freq()
2266 clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, pll_state->pll1); in bxt_ddi_pll_get_freq()
2267 clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, pll_state->ebb0); in bxt_ddi_pll_get_freq()
2268 clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, pll_state->ebb0); in bxt_ddi_pll_get_freq()
3192 return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state); in intel_get_hti_plls()
Dintel_display.c3015 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, in intel_get_pipe_src_size()
3016 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); in intel_get_pipe_src_size()
3267 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp); in i9xx_get_pipe_config()
3269 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; in i9xx_get_pipe_config()
3539 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; in intel_get_m_n()
3695 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp); in ilk_get_pipe_config()
3697 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; in ilk_get_pipe_config()
3699 pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp); in ilk_get_pipe_config()
4115 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); in hsw_get_pipe_config()
4118 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); in hsw_get_pipe_config()
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Dintel_cursor.c589 *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val); in i9xx_cursor_get_hw_state()
Dintel_ddi.c2244 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); in intel_ddi_mso_get_config()
3239 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); in bdw_transcoder_master_readout()
3246 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); in bdw_transcoder_master_readout()
3391 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); in intel_ddi_read_func_ctl()
Dintel_cdclk.c1530 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; in bxt_get_cdclk()
1531 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); in bxt_get_cdclk()
Dintel_display_debugfs.c236 status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val); in psr_source_status()
/Linux-v6.1/drivers/gpu/drm/i915/
Dintel_dram.c474 switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) { in xelpdp_get_dram_info()
498 dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val); in xelpdp_get_dram_info()
499 dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val); in xelpdp_get_dram_info()
Di915_reg_defs.h87 #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) macro
Dintel_pm.c2847 wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd); in snb_read_wm_latency()
2848 wm[1] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd); in snb_read_wm_latency()
2849 wm[2] = REG_FIELD_GET(SSKPD_WM2_MASK_SNB, sskpd); in snb_read_wm_latency()
2850 wm[3] = REG_FIELD_GET(SSKPD_WM3_MASK_SNB, sskpd); in snb_read_wm_latency()
2861 wm[1] = REG_FIELD_GET(MLTR_WM1_MASK, mltr); in ilk_read_wm_latency()
2862 wm[2] = REG_FIELD_GET(MLTR_WM2_MASK, mltr); in ilk_read_wm_latency()
3633 active->wm[0].pri_val = REG_FIELD_GET(WM0_PIPE_PRIMARY_MASK, tmp); in ilk_pipe_wm_get_hw_state()
3634 active->wm[0].spr_val = REG_FIELD_GET(WM0_PIPE_SPRITE_MASK, tmp); in ilk_pipe_wm_get_hw_state()
3635 active->wm[0].cur_val = REG_FIELD_GET(WM0_PIPE_CURSOR_MASK, tmp); in ilk_pipe_wm_get_hw_state()
4226 if (REG_FIELD_GET(SSKPD_WM0_MASK_SNB, tmp) != 12) in gen6_check_mch_setup()
/Linux-v6.1/drivers/gpu/drm/i915/gt/
Dintel_sseu.c604 switch (REG_FIELD_GET(HSW_F1_EU_DIS_MASK, fuse1)) { in hsw_sseu_info_init()
606 MISSING_CASE(REG_FIELD_GET(HSW_F1_EU_DIS_MASK, fuse1)); in hsw_sseu_info_init()
Dintel_gt_sysfs_pm.c636 mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ? in media_freq_factor_show()
Dintel_engine_cs.c693 gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1); in engine_mask_apply_media_fuses()
772 meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask); in engine_mask_apply_copy_fuses()
Dintel_rps.c1111 caps->rp1_freq = REG_FIELD_GET(RPE_MASK, in gen6_rps_get_freq_caps()
/Linux-v6.1/drivers/gpu/drm/i915/gvt/
Dhandlers.c565 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, in bxt_vgpu_get_dp_bitrate()
568 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, in bxt_vgpu_get_dp_bitrate()
570 clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, in bxt_vgpu_get_dp_bitrate()
572 clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, in bxt_vgpu_get_dp_bitrate()
574 clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, in bxt_vgpu_get_dp_bitrate()