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Searched refs:DPIO_PHY0 (Results 1 – 12 of 12) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c1116 MMIO_D(BXT_PHY_CTL_FAMILY(DPIO_PHY0)); in iterate_bxt_mmio()
1124 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0)); in iterate_bxt_mmio()
1125 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0)); in iterate_bxt_mmio()
1126 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0)); in iterate_bxt_mmio()
1127 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0)); in iterate_bxt_mmio()
1128 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0)); in iterate_bxt_mmio()
1129 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0)); in iterate_bxt_mmio()
1130 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0)); in iterate_bxt_mmio()
1131 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0)); in iterate_bxt_mmio()
1132 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0)); in iterate_bxt_mmio()
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Dvlv_sideband.c222 return phy == DPIO_PHY0 ? IOSF_PORT_DPIO_2 : IOSF_PORT_DPIO; in vlv_dpio_phy_iosf_port()
Di915_reg.h1528 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
/Linux-v6.1/drivers/gpu/drm/i915/display/
Dintel_display_power_well.c1316 if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY0]) in assert_chv_phy_status()
1317 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | in assert_chv_phy_status()
1318 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | in assert_chv_phy_status()
1319 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | in assert_chv_phy_status()
1320 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | in assert_chv_phy_status()
1321 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | in assert_chv_phy_status()
1322 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); in assert_chv_phy_status()
1330 phy_status |= PHY_POWERGOOD(DPIO_PHY0); in assert_chv_phy_status()
1333 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) in assert_chv_phy_status()
1334 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); in assert_chv_phy_status()
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Dintel_display_power.c1723 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | in chv_phy_control_init()
1725 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | in chv_phy_control_init()
1726 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | in chv_phy_control_init()
1745 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); in chv_phy_control_init()
1748 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); in chv_phy_control_init()
1755 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); in chv_phy_control_init()
1758 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); in chv_phy_control_init()
1760 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); in chv_phy_control_init()
1762 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = false; in chv_phy_control_init()
1764 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = true; in chv_phy_control_init()
Dintel_dpio_phy.c164 [DPIO_PHY0] = {
186 [DPIO_PHY0] = {
267 *phy = DPIO_PHY0; in bxt_port_to_phy_channel()
818 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); in chv_phy_pre_pll_enable()
966 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); in chv_phy_release_cl2_override()
Dintel_display_power_map.c460 .bxt.phy = DPIO_PHY0,
556 .bxt.phy = DPIO_PHY0,
Dintel_display.h288 DPIO_PHY0, enumerator
Dintel_display_types.h1826 return DPIO_PHY0; in vlv_dig_port_to_phy()
/Linux-v6.1/drivers/gpu/drm/i915/gvt/
Ddisplay.c232 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in emulate_monitor_status_change()
236 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30); in emulate_monitor_status_change()
295 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in emulate_monitor_status_change()
297 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= in emulate_monitor_status_change()
325 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in emulate_monitor_status_change()
327 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= in emulate_monitor_status_change()
Dmmio.c263 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in intel_vgpu_reset_mmio()
267 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= in intel_vgpu_reset_mmio()
Dhandlers.c533 enum dpio_phy phy = DPIO_PHY0; in bxt_vgpu_get_dp_bitrate()
545 phy = DPIO_PHY0; in bxt_vgpu_get_dp_bitrate()
549 phy = DPIO_PHY0; in bxt_vgpu_get_dp_bitrate()
1873 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in bxt_gt_disp_pwron_write()
1875 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in bxt_gt_disp_pwron_write()
2748 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, in init_bxt_mmio_info()
2759 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
2761 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
2763 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, in init_bxt_mmio_info()
2765 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT, in init_bxt_mmio_info()