Searched refs:Bits (Results 1 – 25 of 75) sorted by relevance
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29 - Bits [3:0]33 - Bits [7:4]37 - Bits [3:0]41 - Bits [7:4]45 - Bits [3:0]49 - Bits [7:4]78 - Bits [3:0]82 - Bits [3:0]86 - Bits [3:0]90 - Bits [7:4][all …]
8 * - Bits 7..4: Panel ID: 0x0 (AUO)9 * - Bits 3..0: SKU ID: 0x0 (default)
8 * - Bits 7..4: Panel ID: 0xb (BOE)9 * - Bits 3..0: SKU ID: 0x0 (default)
51 Bits 0:15 次要 版本52 Bits 16:31 主要 版本
1 Maxim Integrated MAX2175 RF to Bits tuner5 RF to Bits® front-end designed for software-defined radio solutions.
29 Bits [6:5] - transaction length. b01 - 72B is supported,42 Bits [7:1] - the 7bit Address of the I2C device.
11 * Bits [15:8] are the Bus number.12 * Bits [7:3] are the Device number.13 * Bits [2:0] are the Function number.
43 Bits 0:15 Minor version44 Bits 16:31 Major version
8 as decoded from the fuse registers. Bits order/assignment
28 Bits Per Colour/Component31 Bits Per Pixel
26 Resolution: 8 Bits
20 Bits 0-3 of byte n refer to confidence value of depth pixel 2*n,
119 * - Bits 0-2121 * - Bits 3-5
18 * Bits 0-54 page frame number (PFN) if present19 * Bits 0-4 swap type if swapped20 * Bits 5-54 swap offset if swapped26 * Bits 58-60 zero
112 0x11 TLB Entry High-order Bits TLBEHI113 0x12 TLB Entry Low-order Bits 0 TLBELO0114 0x13 TLB Entry Low-order Bits 1 TLBELO1148 Bits 0150 Bits 1152 Bits
11 - bits-per-pixel: Bits per pixel.
24 respectively. Bits 2-7 are ignored, so it's safe to write ASCII data.
40 represent the state of PIO_0/PIO_1. Bits 2..7 do not care. The PIO's are
82 01 Bit 8 is set if the effect is playing. Bits 0 to 7 are the effect id.111 Bits 4-7: Val 2 = effect along one axis. Byte 05 indicates direction115 Bits 0-3: Val 0 = No trigger
14 - bits-per-pixel: Bits per pixel
37 See Section 4.3.12.4 of ISA; Bits::
1316 enum MT2063_Mask_Bits Bits) in MT2063_ClearPowerMaskBits() argument1321 Bits = (enum MT2063_Mask_Bits)(Bits & MT2063_ALL_SD); /* Only valid bits for this tuner */ in MT2063_ClearPowerMaskBits()1322 if ((Bits & 0xFF00) != 0) { in MT2063_ClearPowerMaskBits()1323 state->reg[MT2063_REG_PWR_2] &= ~(u8) (Bits >> 8); in MT2063_ClearPowerMaskBits()1329 if ((Bits & 0xFF) != 0) { in MT2063_ClearPowerMaskBits()1330 state->reg[MT2063_REG_PWR_1] &= ~(u8) (Bits & 0xFF); in MT2063_ClearPowerMaskBits()
9 - bpp: Bits per pixel
49 Bits[5:0] pagetable bit number used to activate memory51 Bits[11:6] reduction in physical address space, in bits, when
