Searched refs:xive_tima (Results 1 – 5 of 5) sorted by relevance
346 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_HV_REG)); in xive_native_update_pending()405 if (in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2) & TM_QW2W2_VP) in xive_native_setup_cpu()406 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX); in xive_native_setup_cpu()430 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff); in xive_native_setup_cpu()431 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2, TM_QW2W2_VP | vp_cam); in xive_native_setup_cpu()443 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX); in xive_native_teardown_cpu()
53 void __iomem *xive_tima; variable54 EXPORT_SYMBOL_GPL(xive_tima);191 out_8(xive_tima + xive_tima_offset + TM_CPPR, prio); in xive_scan_interrupts()1346 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff); in xive_setup_cpu()1439 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0); in xive_smp_disable_cpu()1446 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff); in xive_smp_disable_cpu()1469 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0); in xive_teardown_cpu()1491 xive_tima = area; in xive_core_init()
584 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_OS_REG)); in xive_spapr_update_pending()624 in_be32(xive_tima + TM_QW1_OS + TM_WORD0), in xive_spapr_setup_cpu()625 in_be32(xive_tima + TM_QW1_OS + TM_WORD1), in xive_spapr_setup_cpu()626 in_be32(xive_tima + TM_QW1_OS + TM_WORD2)); in xive_spapr_setup_cpu()
21 extern void __iomem *xive_tima;
45 #define __x_tima xive_tima
