Searched refs:ttbr (Results 1 – 13 of 13) sorted by relevance
| /Linux-v5.4/arch/arm64/include/asm/ |
| D | mmu_context.h | 43 unsigned long ttbr = phys_to_ttbr(__pa_symbol(empty_zero_page)); in cpu_set_reserved_ttbr0() local
45 write_sysreg(ttbr, ttbr0_el1); in cpu_set_reserved_ttbr0()
184 u64 ttbr; in update_saved_ttbr0() local
190 ttbr = __pa_symbol(empty_zero_page); in update_saved_ttbr0()
192 ttbr = virt_to_phys(mm->pgd) | ASID(mm) << 48; in update_saved_ttbr0()
194 WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr); in update_saved_ttbr0()
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| D | assembler.h | 537 .macro offset_ttbr1, ttbr, tmp
542 orr \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
552 .macro restore_ttbr1, ttbr
554 bic \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
565 .macro phys_to_ttbr, ttbr, phys
567 orr \ttbr, \phys, \phys, lsr #46
568 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
570 mov \ttbr, \phys
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| D | uaccess.h | 105 unsigned long flags, ttbr; in __uaccess_ttbr0_disable() local
108 ttbr = read_sysreg(ttbr1_el1); in __uaccess_ttbr0_disable()
109 ttbr &= ~TTBR_ASID_MASK; in __uaccess_ttbr0_disable()
111 write_sysreg(ttbr - RESERVED_TTBR0_SIZE, ttbr0_el1); in __uaccess_ttbr0_disable()
114 write_sysreg(ttbr, ttbr1_el1); in __uaccess_ttbr0_disable()
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| /Linux-v5.4/arch/arm/include/asm/ |
| D | proc-fns.h | 160 u64 ttbr; \
162 : "=r" (ttbr)); \
163 ttbr; \
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| /Linux-v5.4/include/linux/ |
| D | io-pgtable.h | 103 u64 ttbr[2]; member
114 u32 ttbr[2]; member
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| /Linux-v5.4/drivers/iommu/ |
| D | arm-smmu.c | 94 u64 ttbr[2]; member
521 cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr[0]; in arm_smmu_init_context_bank()
522 cb->ttbr[1] = pgtbl_cfg->arm_v7s_cfg.ttbr[1]; in arm_smmu_init_context_bank()
524 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; in arm_smmu_init_context_bank()
525 cb->ttbr[0] |= FIELD_PREP(TTBRn_ASID, cfg->asid); in arm_smmu_init_context_bank()
526 cb->ttbr[1] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1]; in arm_smmu_init_context_bank()
527 cb->ttbr[1] |= FIELD_PREP(TTBRn_ASID, cfg->asid); in arm_smmu_init_context_bank()
530 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; in arm_smmu_init_context_bank()
603 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
604 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR1, cb->ttbr[1]); in arm_smmu_write_context_bank()
[all …]
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| D | ipmmu-vmsa.c | 415 u64 ttbr; in ipmmu_domain_setup_context() local
419 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0]; in ipmmu_domain_setup_context()
420 ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); in ipmmu_domain_setup_context()
421 ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); in ipmmu_domain_setup_context()
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| D | mtk_iommu.c | 395 writel(dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK, in mtk_iommu_attach_device()
800 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK, in mtk_iommu_resume()
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| D | qcom_iommu.c | 272 pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0] | in qcom_iommu_init_domain()
275 pgtbl_cfg.arm_lpae_s1_cfg.ttbr[1] | in qcom_iommu_init_domain()
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| D | msm_iommu.c | 282 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[0]); in __program_context()
283 SET_TTBR1(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[1]); in __program_context()
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| D | io-pgtable-arm-v7s.c | 826 cfg->arm_v7s_cfg.ttbr[0] = virt_to_phys(data->pgd) | in arm_v7s_alloc_pgtable()
833 cfg->arm_v7s_cfg.ttbr[1] = 0; in arm_v7s_alloc_pgtable()
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| D | io-pgtable-arm.c | 879 cfg->arm_lpae_s1_cfg.ttbr[0] = virt_to_phys(data->pgd); in arm_64_lpae_alloc_pgtable_s1()
880 cfg->arm_lpae_s1_cfg.ttbr[1] = 0; in arm_64_lpae_alloc_pgtable_s1()
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| D | arm-smmu-v3.c | 556 u64 ttbr; member
1486 val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK; in arm_smmu_write_ctx_desc()
2173 cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; in arm_smmu_domain_finalise_s1()
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