Home
last modified time | relevance | path

Searched refs:t4_read_reg (Results 1 – 14 of 14) sorted by relevance

/Linux-v5.4/drivers/net/ethernet/chelsio/cxgb4/
Dcudbg_lib.c150 lo = t4_read_reg(padap, MA_TARGET_MEM_ENABLE_A); in cudbg_fill_meminfo()
152 hi = t4_read_reg(padap, MA_EDRAM0_BAR_A); in cudbg_fill_meminfo()
163 hi = t4_read_reg(padap, MA_EDRAM1_BAR_A); in cudbg_fill_meminfo()
175 hi = t4_read_reg(padap, MA_EXT_MEMORY0_BAR_A); in cudbg_fill_meminfo()
186 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A); in cudbg_fill_meminfo()
197 hi = t4_read_reg(padap, MA_EXT_MEMORY_BAR_A); in cudbg_fill_meminfo()
208 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A); in cudbg_fill_meminfo()
225 (md++)->base = t4_read_reg(padap, SGE_DBQ_CTXT_BADDR_A); in cudbg_fill_meminfo()
226 (md++)->base = t4_read_reg(padap, SGE_IMSG_CTXT_BADDR_A); in cudbg_fill_meminfo()
227 (md++)->base = t4_read_reg(padap, SGE_FLM_CACHE_BADDR_A); in cudbg_fill_meminfo()
[all …]
Dcxgb4_cudbg.c140 value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); in cxgb4_get_entity_length()
142 value = t4_read_reg(adap, MA_EDRAM0_BAR_A); in cxgb4_get_entity_length()
148 value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); in cxgb4_get_entity_length()
150 value = t4_read_reg(adap, MA_EDRAM1_BAR_A); in cxgb4_get_entity_length()
156 value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); in cxgb4_get_entity_length()
158 value = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); in cxgb4_get_entity_length()
164 value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); in cxgb4_get_entity_length()
166 value = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); in cxgb4_get_entity_length()
293 value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); in cxgb4_get_entity_length()
298 value = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); in cxgb4_get_entity_length()
Dt4_hw.c61 u32 val = t4_read_reg(adapter, reg); in t4_wait_op_done_val()
95 u32 v = t4_read_reg(adapter, addr) & ~mask; in t4_set_reg_field()
98 (void) t4_read_reg(adapter, addr); /* flush */ in t4_set_reg_field()
119 *vals++ = t4_read_reg(adap, data_reg); in t4_read_indirect()
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A); in t4_hw_pci_read_cfg4()
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A); in t4_report_fw_error()
335 pcie_fw = t4_read_reg(adap, PCIE_FW_A); in t4_wr_mbox_meat_timeout()
366 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); in t4_wr_mbox_meat_timeout()
368 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); in t4_wr_mbox_meat_timeout()
384 t4_read_reg(adap, ctl_reg); /* flush write */ in t4_wr_mbox_meat_timeout()
[all …]
Dcxgb4_debugfs.c644 switch (DBGLAMODE_G(t4_read_reg(adap, TP_DBG_LA_CONFIG_A))) { in tp_la_open()
908 u32 res = t4_read_reg(adap, TP_TIMER_RESOLUTION_A); in clk_show()
924 t4_read_reg(adap, TP_DACK_TIMER_A)); in clk_show()
926 tp_tick_us * t4_read_reg(adap, TP_RXT_MIN_A)); in clk_show()
928 tp_tick_us * t4_read_reg(adap, TP_RXT_MAX_A)); in clk_show()
930 tp_tick_us * t4_read_reg(adap, TP_PERS_MIN_A)); in clk_show()
932 tp_tick_us * t4_read_reg(adap, TP_PERS_MAX_A)); in clk_show()
934 tp_tick_us * t4_read_reg(adap, TP_KEEP_IDLE_A)); in clk_show()
936 tp_tick_us * t4_read_reg(adap, TP_KEEP_INTVL_A)); in clk_show()
938 tp_tick_us * INITSRTT_G(t4_read_reg(adap, TP_INIT_SRTT_A))); in clk_show()
[all …]
Dcxgb4_main.c675 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A)); in t4_nondata_intr()
1746 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); in cxgb4_dbfifo_count()
1747 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); in cxgb4_dbfifo_count()
1816 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8; in read_eq_indices()
1884 size = t4_read_reg(adap, MA_EDRAM0_BAR_A); in cxgb4_read_tpte()
1886 size = t4_read_reg(adap, MA_EDRAM1_BAR_A); in cxgb4_read_tpte()
1888 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); in cxgb4_read_tpte()
1891 if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) { in cxgb4_read_tpte()
1892 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); in cxgb4_read_tpte()
1913 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); in cxgb4_read_tpte()
[all …]
Dcxgb4_uld.c666 lld->iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A)); in uld_init()
667 lld->iscsi_tagmask = t4_read_reg(adap, ULP_RX_ISCSI_TAGMASK_A); in uld_init()
668 lld->iscsi_pgsz_order = t4_read_reg(adap, ULP_RX_ISCSI_PSZ_A); in uld_init()
669 lld->iscsi_llimit = t4_read_reg(adap, ULP_RX_ISCSI_LLIMIT_A); in uld_init()
Dcxgb4_ptp.c106 tx_ts = t4_read_reg(adapter, in cxgb4_ptp_read_hwstamp()
109 tx_ts |= (u64)t4_read_reg(adapter, in cxgb4_ptp_read_hwstamp()
Dcxgb4_ethtool.c272 v = t4_read_reg(adap, SGE_STAT_CFG_A); in collect_adapter_stats()
274 val2 = t4_read_reg(adap, SGE_STAT_MATCH_A); in collect_adapter_stats()
275 val1 = t4_read_reg(adap, SGE_STAT_TOTAL_A); in collect_adapter_stats()
1220 pcie_fw = t4_read_reg(adap, PCIE_FW_A); in set_flash()
Dcxgb4_filter.c362 tcb_base = t4_read_reg(adapter, TP_CMM_TCB_BASE_A); in get_filter_count()
772 sb = t4_read_reg(adapter, LE_DB_SRVR_START_INDEX_A); in clear_all_filters()
1842 if (!(t4_read_reg(adap, TP_GLOBAL_CONFIG_A) in init_hash_filter()
1848 reg = t4_read_reg(adap, LE_DB_RSP_CODE_0_A); in init_hash_filter()
1854 reg = t4_read_reg(adap, LE_DB_RSP_CODE_1_A); in init_hash_filter()
Dsge.c4197 if ((t4_read_reg(adap, SGE_CONTROL_A) & RXPKTCPLMODE_F) != in t4_sge_init_soft()
4212 t4_read_reg(adap, SGE_FL_BUFFER_SIZE0_A+(x)*sizeof(u32)) in t4_sge_init_soft()
4250 timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1_A); in t4_sge_init_soft()
4251 timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3_A); in t4_sge_init_soft()
4252 timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5_A); in t4_sge_init_soft()
4266 ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD_A); in t4_sge_init_soft()
4292 sge_control = t4_read_reg(adap, SGE_CONTROL_A); in t4_sge_init()
4313 sge_conm_ctrl = t4_read_reg(adap, SGE_CONM_CTRL_A); in t4_sge_init()
Dcxgb4.h1296 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) in t4_read_reg() function
/Linux-v5.4/drivers/net/ethernet/chelsio/cxgb4vf/
Dt4vf_hw.c57 val = t4_read_reg(adapter, whoami); in t4vf_wait_dev_ready()
61 val = t4_read_reg(adapter, whoami); in t4vf_wait_dev_ready()
209 v = MBOWNER_G(t4_read_reg(adapter, mbox_ctl)); in t4vf_wr_mbox_core()
211 v = MBOWNER_G(t4_read_reg(adapter, mbox_ctl)); in t4vf_wr_mbox_core()
238 t4_read_reg(adapter, mbox_data); /* flush write */ in t4vf_wr_mbox_core()
242 t4_read_reg(adapter, mbox_ctl); /* flush write */ in t4vf_wr_mbox_core()
262 v = t4_read_reg(adapter, mbox_ctl); in t4vf_wr_mbox_core()
835 whoami = t4_read_reg(adapter, T4VF_PL_BASE_ADDR + PL_VF_WHOAMI_A); in t4vf_get_pf_from_vf()
2166 chipid = REV_G(t4_read_reg(adapter, PL_VF_REV_A)); in t4vf_prep_adapter()
2174 chipid = REV_G(t4_read_reg(adapter, PL_VF_REV_A)); in t4vf_prep_adapter()
Dadapter.h429 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr) in t4_read_reg() function
Dcxgb4vf_main.c1863 *bp++ = t4_read_reg(adapter, start); in reg_block_dump()