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Searched refs:smnPCIE_LC_LINK_WIDTH_CNTL (Results 1 – 2 of 2) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/powerplay/
Dvega20_ppt.c43 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 macro
1063 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega20_print_clk_levels()
/Linux-v5.4/drivers/gpu/drm/amd/powerplay/hwmgr/
Dvega20_hwmgr.c56 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 macro
3358 current_lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega20_print_clock_levels()