Searched refs:res_cap (Results 1 – 13 of 13) sorted by relevance
354 static const struct resource_caps res_cap = { variable755 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in destruct()884 pool->base.res_cap = &res_cap; in dce80_construct()892 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()893 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct()1008 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_construct()1081 pool->base.res_cap = &res_cap_81; in dce81_construct()1205 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce81_construct()1278 pool->base.res_cap = &res_cap_83; in dce83_construct()1398 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce83_construct()
842 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in destruct()873 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in destruct()886 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in destruct()891 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in destruct()898 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in destruct()1278 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; in update_bw_bounding_box()1446 pool->base.res_cap = &res_cap_rn; in construct()1450 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; in construct()1567 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in construct()1585 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in construct()[all …]
361 static const struct resource_caps res_cap = { variable707 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in destruct()918 pool->base.res_cap = &res_cap; in construct()993 pool->base.pipe_count = res_cap.num_timing_generator; in construct()994 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in construct()1045 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in construct()
450 static const struct resource_caps res_cap = { variable577 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in destruct()996 pool->base.res_cap = &res_cap; in construct()1000 pool->base.pipe_count = res_cap.num_timing_generator; in construct()1001 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in construct()1144 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in construct()
494 static const struct resource_caps res_cap = { variable931 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in destruct()1284 pool->base.res_cap = &rv2_res_cap; in construct()1286 pool->base.res_cap = &res_cap; in construct()1300 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in construct()1497 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in construct()
355 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn10_log_hw_state()1258 for (i = 0; i < res_pool->res_cap->num_dsc; i++) in dcn10_init_hw()
764 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in destruct()1282 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); in construct()1289 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in construct()1291 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in construct()1403 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in construct()
726 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in destruct()1153 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); in construct()1160 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in construct()1161 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in construct()1292 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in construct()
1205 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in destruct()1236 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in destruct()1249 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in destruct()1254 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in destruct()1261 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in destruct()1430 for (i = 0; i < pool->res_cap->num_dsc; i++) in acquire_dsc()1444 for (i = 0; i < pool->res_cap->num_dsc; i++) in release_dsc()2901 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_dwbc_create()2926 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_mmhubbub_create()3300 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; in init_soc_bounding_box()[all …]
216 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn20_init_blank()221 ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp); in dcn20_init_blank()2028 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { in dcn20_fpga_init_hw()2063 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn20_fpga_init_hw()
229 const struct resource_caps *res_cap; member
394 if (line < pool->res_cap->num_ddc) in acquire_i2c_hw_engine()
253 const struct resource_caps *caps = pool->res_cap; in resource_construct()
