Home
last modified time | relevance | path

Searched refs:rb_bufsz (Results 1 – 25 of 35) sorted by relevance

12

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ih.c44 u32 rb_bufsz; in amdgpu_ih_ring_init() local
48 rb_bufsz = order_base_2(ring_size / 4); in amdgpu_ih_ring_init()
49 ring_size = (1 << rb_bufsz) * 4; in amdgpu_ih_ring_init()
Dsi_ih.c63 int rb_bufsz; in si_ih_irq_init() local
74 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in si_ih_irq_init()
78 (rb_bufsz << 1) | in si_ih_irq_init()
Duvd_v4_2.c257 uint32_t rb_bufsz; in uvd_v4_2_start() local
367 rb_bufsz = order_base_2(ring->ring_size); in uvd_v4_2_start()
368 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v4_2_start()
369 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v4_2_start()
Dcik_ih.c109 int rb_bufsz; in cik_ih_irq_init() local
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cik_ih_irq_init()
131 (rb_bufsz << 1)); in cik_ih_irq_init()
Dcz_ih.c110 int rb_bufsz; in cz_ih_irq_init() local
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cz_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
Diceland_ih.c109 int rb_bufsz; in iceland_ih_irq_init() local
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in iceland_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
Dtonga_ih.c106 int rb_bufsz; in tonga_ih_irq_init() local
125 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in tonga_ih_irq_init()
127 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in tonga_ih_irq_init()
Duvd_v5_0.c295 uint32_t rb_bufsz, tmp; in uvd_v5_0_start() local
392 rb_bufsz = order_base_2(ring->ring_size); in uvd_v5_0_start()
394 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v5_0_start()
Dnavi10_ih.c78 int rb_bufsz = order_base_2(ih->ring_size / 4); in navi10_ih_rb_cntl() local
86 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in navi10_ih_rb_cntl()
Dsi_dma.c134 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; in si_dma_start() local
145 rb_bufsz = order_base_2(ring->ring_size / 4); in si_dma_start()
146 rb_cntl = rb_bufsz << 1; in si_dma_start()
Dvega10_ih.c168 int rb_bufsz = order_base_2(ih->ring_size / 4); in vega10_ih_rb_cntl() local
176 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in vega10_ih_rb_cntl()
Dvcn_v2_0.c931 uint32_t rb_bufsz, tmp; in vcn_v2_0_start_dpg_mode() local
1021 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_0_start_dpg_mode()
1022 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start_dpg_mode()
1057 uint32_t rb_bufsz, tmp; in vcn_v2_0_start() local
1186 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_0_start()
1187 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start()
Dsdma_v2_4.c414 u32 rb_bufsz; in sdma_v2_4_gfx_resume() local
438 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v2_4_gfx_resume()
440 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v2_4_gfx_resume()
Dvcn_v1_0.c785 uint32_t rb_bufsz, tmp; in vcn_v1_0_start_spg_mode() local
904 rb_bufsz = order_base_2(ring->ring_size); in vcn_v1_0_start_spg_mode()
905 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start_spg_mode()
974 uint32_t rb_bufsz, tmp; in vcn_v1_0_start_dpg_mode() local
1077 rb_bufsz = order_base_2(ring->ring_size); in vcn_v1_0_start_dpg_mode()
1078 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start_dpg_mode()
Dcik_sdma.c436 u32 rb_bufsz; in cik_sdma_gfx_resume() local
462 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()
463 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
Dgfx_v6_0.c2094 u32 rb_bufsz; in gfx_v6_0_cp_gfx_resume() local
2110 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v6_0_cp_gfx_resume()
2111 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v6_0_cp_gfx_resume()
2191 u32 rb_bufsz; in gfx_v6_0_cp_compute_resume() local
2199 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v6_0_cp_compute_resume()
2200 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v6_0_cp_compute_resume()
2219 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v6_0_cp_compute_resume()
2220 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v6_0_cp_compute_resume()
Dsdma_v3_0.c649 u32 rb_bufsz; in sdma_v3_0_gfx_resume() local
676 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v3_0_gfx_resume()
678 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v3_0_gfx_resume()
Duvd_v6_0.c702 uint32_t rb_bufsz, tmp; in uvd_v6_0_start() local
811 rb_bufsz = order_base_2(ring->ring_size); in uvd_v6_0_start()
812 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v6_0_start()
Dvcn_v2_5.c716 uint32_t rb_bufsz, tmp; in vcn_v2_5_start() local
849 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_start()
850 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start()
Dgfx_v10_0.c2774 u32 rb_bufsz; in gfx_v10_0_cp_gfx_resume() local
2790 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v10_0_cp_gfx_resume()
2791 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume()
2792 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
2831 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v10_0_cp_gfx_resume()
2832 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume()
2833 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
2983 uint32_t rb_bufsz; in gfx_v10_0_gfx_mqd_init() local
3033 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; in gfx_v10_0_gfx_mqd_init()
3035 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_gfx_mqd_init()
[all …]
/Linux-v5.4/drivers/gpu/drm/radeon/
Duvd_v1_0.c266 uint32_t rb_bufsz; in uvd_v1_0_start() local
377 rb_bufsz = order_base_2(ring->ring_size); in uvd_v1_0_start()
378 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v1_0_start()
379 WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v1_0_start()
Dni_dma.c191 u32 rb_bufsz; in cayman_dma_resume() local
210 rb_bufsz = order_base_2(ring->ring_size / 4); in cayman_dma_resume()
211 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
Dr600_dma.c124 u32 rb_bufsz; in r600_dma_resume() local
131 rb_bufsz = order_base_2(ring->ring_size / 4); in r600_dma_resume()
132 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
Dcik_sdma.c369 u32 rb_bufsz; in cik_sdma_gfx_resume() local
388 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()
389 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
Dr600.c2719 u32 rb_bufsz; in r600_cp_resume() local
2729 rb_bufsz = order_base_2(ring->ring_size / 8); in r600_cp_resume()
2730 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in r600_cp_resume()
2781 u32 rb_bufsz; in r600_ring_init() local
2785 rb_bufsz = order_base_2(ring_size / 8); in r600_ring_init()
2786 ring_size = (1 << (rb_bufsz + 1)) * 4; in r600_ring_init()
3471 u32 rb_bufsz; in r600_ih_ring_init() local
3474 rb_bufsz = order_base_2(ring_size / 4); in r600_ih_ring_init()
3475 ring_size = (1 << rb_bufsz) * 4; in r600_ih_ring_init()
3677 int rb_bufsz; in r600_irq_init() local
[all …]

12