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Searched refs:plane_res (Results 1 – 14 of 14) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c551 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; in calculate_viewport()
666 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x; in calculate_recout()
668 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x in calculate_recout()
672 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width * in calculate_recout()
674 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x > in calculate_recout()
676 pipe_ctx->plane_res.scl_data.recout.width = in calculate_recout()
678 - pipe_ctx->plane_res.scl_data.recout.x; in calculate_recout()
680 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y; in calculate_recout()
682 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y in calculate_recout()
686 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height * in calculate_recout()
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Ddc_stream.c348 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || in dc_stream_set_cursor_position()
350 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || in dc_stream_set_cursor_position()
351 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp)) in dc_stream_set_cursor_position()
618 hubp = pipe_ctx->plane_res.hubp; in dc_stream_set_dynamic_metadata()
Ddc.c441 if (pipes->plane_res.xfm && in dc_stream_set_dither_option()
442 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) { in dc_stream_set_dither_option()
443 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth( in dc_stream_set_dither_option()
444 pipes->plane_res.xfm, in dc_stream_set_dither_option()
445 pipes->plane_res.scl_data.lb_params.depth, in dc_stream_set_dither_option()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c274 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; in dce110_set_input_transfer_func()
602 struct transform *xfm = pipe_ctx->plane_res.xfm; in dce110_set_output_transfer_func()
1198 switch (pipe_ctx->plane_res.scl_data.format) { in get_surface_visual_confirm_color()
1235 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) in program_scaler()
1246 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( in program_scaler()
1247 pipe_ctx->plane_res.xfm, in program_scaler()
1248 pipe_ctx->plane_res.scl_data.lb_params.depth, in program_scaler()
1265 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, in program_scaler()
1266 &pipe_ctx->plane_res.scl_data); in program_scaler()
1419 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; in apply_single_controller_ctx_to_hw()
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Ddce110_resource.c1062 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; in dce110_acquire_underlay()
1064 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; in dce110_acquire_underlay()
1098 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, in dce110_acquire_underlay()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c426 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_did_underflow_occur()
888 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
913 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
926 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
936 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
948 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
979 struct hubp *hubp = pipe_ctx->plane_res.hubp; in hwss1_plane_atomic_disconnect()
980 int dpp_id = pipe_ctx->plane_res.dpp->inst; in hwss1_plane_atomic_disconnect()
995 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in hwss1_plane_atomic_disconnect()
1031 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_plane_atomic_disable()
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Ddcn10_resource.c1110 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1111 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1112 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1113 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn10_acquire_idle_pipe_for_layer()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c313 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { in pipe_ctx_to_e2e_pipe_params()
328 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
336 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
337 input->src.viewport_height = pipe->plane_res.scl_data.viewport.height; in pipe_ctx_to_e2e_pipe_params()
338 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
339 input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
387 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; in pipe_ctx_to_e2e_pipe_params()
388 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
389 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
390 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
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Ddce_calcs.c2799 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); in populate_initial_data()
2801 data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height); in populate_initial_data()
2802 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
2803 data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps); in populate_initial_data()
2804 …data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.h… in populate_initial_data()
2805 …data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.v… in populate_initial_data()
2853 …data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.v… in populate_initial_data()
2854 …data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.vi… in populate_initial_data()
2857 …data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
2858 …data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
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/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c186 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { in dcn20_program_tripleBuffer()
187 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( in dcn20_program_tripleBuffer()
188 pipe_ctx->plane_res.hubp, in dcn20_program_tripleBuffer()
478 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn20_plane_atomic_disable()
479 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn20_plane_atomic_disable()
499 pipe_ctx->plane_res.dpp, in dcn20_plane_atomic_disable()
500 pipe_ctx->plane_res.hubp); in dcn20_plane_atomic_disable()
504 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); in dcn20_plane_atomic_disable()
515 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) in dcn20_disable_plane()
632 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn20_program_output_csc()
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Ddcn20_resource.c1615 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1616 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1617 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1618 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1619 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1620 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; in dcn20_split_stream_for_odm()
1634 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; in dcn20_split_stream_for_odm()
1651 sd = &next_odm_pipe->plane_res.scl_data; in dcn20_split_stream_for_odm()
1695 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
1696 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
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/Linux-v5.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c113 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; in dcn20_update_clocks_update_dpp_dto()
114 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
287 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; in dcn2_update_clocks()
288 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in dcn2_update_clocks()
304 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; in dcn2_update_clocks()
305 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in dcn2_update_clocks()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr.c107 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control( in ramp_up_dispclk_with_dpp()
108 pipe_ctx->plane_res.dpp, in ramp_up_dispclk_with_dpp()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h292 struct plane_resource plane_res; member